source: rtems/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @ 2987c4f

5
Last change on this file since 2987c4f was 9704d86f, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 26, 2018 at 6:53:28 AM

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 2013, 2018 embedded brains GmbH
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifndef _RTEMS_SCORE_CPUIMPL_H
33#define _RTEMS_SCORE_CPUIMPL_H
34
35#include <rtems/score/cpu.h>
36
37#define CPU_PER_CPU_CONTROL_SIZE 0
38
39#if __riscv_xlen == 32
40
41#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140
42
43#define CPU_INTERRUPT_FRAME_SIZE 144
44
45#elif __riscv_xlen == 64
46
47#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280
48
49#define CPU_INTERRUPT_FRAME_SIZE 288
50
51#endif /* __riscv_xlen */
52
53#ifndef ASM
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
59#ifdef RTEMS_SMP
60
61static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
62{
63  struct Per_CPU_Control *cpu_self;
64
65  __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
66
67  return cpu_self;
68}
69
70#define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control()
71
72#endif /* RTEMS_SMP */
73
74#ifdef __cplusplus
75}
76#endif
77
78#endif /* ASM */
79
80#endif /* _RTEMS_SCORE_CPUIMPL_H */
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