[660db8c8] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief CPU Port Implementation API |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[2086948a] | 8 | * Copyright (c) 2013, 2018 embedded brains GmbH |
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[660db8c8] | 9 | * |
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| 10 | * Redistribution and use in source and binary forms, with or without |
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| 11 | * modification, are permitted provided that the following conditions |
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| 12 | * are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 16 | * notice, this list of conditions and the following disclaimer in the |
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| 17 | * documentation and/or other materials provided with the distribution. |
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| 18 | * |
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 29 | * SUCH DAMAGE. |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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| 33 | #define _RTEMS_SCORE_CPUIMPL_H |
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| 34 | |
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| 35 | #include <rtems/score/cpu.h> |
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| 36 | |
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| 37 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 38 | |
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[2086948a] | 39 | #if __riscv_xlen == 32 |
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| 40 | |
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[b706b4a] | 41 | #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128 |
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[9704d86f] | 42 | |
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[b706b4a] | 43 | #define CPU_INTERRUPT_FRAME_SIZE 140 |
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[2086948a] | 44 | |
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| 45 | #elif __riscv_xlen == 64 |
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| 46 | |
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[b706b4a] | 47 | #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256 |
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[9704d86f] | 48 | |
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[b706b4a] | 49 | #define CPU_INTERRUPT_FRAME_SIZE 280 |
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[2086948a] | 50 | |
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| 51 | #endif /* __riscv_xlen */ |
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| 52 | |
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[660db8c8] | 53 | #ifndef ASM |
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| 54 | |
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| 55 | #ifdef __cplusplus |
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| 56 | extern "C" { |
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| 57 | #endif |
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| 58 | |
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[b706b4a] | 59 | typedef struct { |
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| 60 | unsigned long x[32]; |
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| 61 | unsigned long mstatus; |
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| 62 | unsigned long mcause; |
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| 63 | unsigned long mepc; |
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| 64 | } CPU_Interrupt_frame; |
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| 65 | |
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[0fd8287] | 66 | #ifdef RTEMS_SMP |
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| 67 | |
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| 68 | static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) |
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| 69 | { |
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| 70 | struct Per_CPU_Control *cpu_self; |
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| 71 | |
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| 72 | __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) ); |
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| 73 | |
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| 74 | return cpu_self; |
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| 75 | } |
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| 76 | |
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| 77 | #define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control() |
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| 78 | |
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| 79 | #endif /* RTEMS_SMP */ |
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| 80 | |
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[660db8c8] | 81 | #ifdef __cplusplus |
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| 82 | } |
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| 83 | #endif |
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| 84 | |
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| 85 | #endif /* ASM */ |
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| 86 | |
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| 87 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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