[660db8c8] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief CPU Port Implementation API |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[2086948a] | 8 | * Copyright (c) 2013, 2018 embedded brains GmbH |
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[660db8c8] | 9 | * |
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| 10 | * Redistribution and use in source and binary forms, with or without |
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| 11 | * modification, are permitted provided that the following conditions |
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| 12 | * are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 16 | * notice, this list of conditions and the following disclaimer in the |
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| 17 | * documentation and/or other materials provided with the distribution. |
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| 18 | * |
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 29 | * SUCH DAMAGE. |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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| 33 | #define _RTEMS_SCORE_CPUIMPL_H |
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| 34 | |
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| 35 | #include <rtems/score/cpu.h> |
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| 36 | |
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[e755782] | 37 | #ifdef __riscv_atomic |
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| 38 | #define CPU_PER_CPU_CONTROL_SIZE 16 |
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| 39 | #else |
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[660db8c8] | 40 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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[e755782] | 41 | #endif |
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[660db8c8] | 42 | |
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[e43994d] | 43 | #ifdef RTEMS_SMP |
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| 44 | #define RISCV_CONTEXT_IS_EXECUTING 0 |
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| 45 | #endif |
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[2086948a] | 46 | |
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[e43994d] | 47 | #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4 |
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[9704d86f] | 48 | |
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[e43994d] | 49 | #if __riscv_xlen == 32 |
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[2086948a] | 50 | |
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[e43994d] | 51 | #define RISCV_CONTEXT_RA 8 |
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| 52 | #define RISCV_CONTEXT_SP 12 |
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| 53 | #define RISCV_CONTEXT_TP 16 |
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| 54 | #define RISCV_CONTEXT_S0 20 |
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| 55 | #define RISCV_CONTEXT_S1 24 |
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| 56 | #define RISCV_CONTEXT_S2 28 |
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| 57 | #define RISCV_CONTEXT_S3 32 |
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| 58 | #define RISCV_CONTEXT_S4 36 |
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| 59 | #define RISCV_CONTEXT_S5 40 |
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| 60 | #define RISCV_CONTEXT_S6 44 |
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| 61 | #define RISCV_CONTEXT_S7 48 |
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| 62 | #define RISCV_CONTEXT_S8 52 |
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| 63 | #define RISCV_CONTEXT_S9 56 |
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| 64 | #define RISCV_CONTEXT_S10 60 |
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| 65 | #define RISCV_CONTEXT_S11 64 |
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| 66 | |
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| 67 | #define RISCV_INTERRUPT_FRAME_MSTATUS 0 |
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| 68 | #define RISCV_INTERRUPT_FRAME_MEPC 4 |
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| 69 | #define RISCV_INTERRUPT_FRAME_A2 8 |
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| 70 | #define RISCV_INTERRUPT_FRAME_S0 12 |
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| 71 | #define RISCV_INTERRUPT_FRAME_S1 16 |
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| 72 | #define RISCV_INTERRUPT_FRAME_RA 20 |
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| 73 | #define RISCV_INTERRUPT_FRAME_A3 24 |
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| 74 | #define RISCV_INTERRUPT_FRAME_A4 28 |
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| 75 | #define RISCV_INTERRUPT_FRAME_A5 32 |
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| 76 | #define RISCV_INTERRUPT_FRAME_A6 36 |
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| 77 | #define RISCV_INTERRUPT_FRAME_A7 40 |
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| 78 | #define RISCV_INTERRUPT_FRAME_T0 44 |
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| 79 | #define RISCV_INTERRUPT_FRAME_T1 48 |
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| 80 | #define RISCV_INTERRUPT_FRAME_T2 52 |
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| 81 | #define RISCV_INTERRUPT_FRAME_T3 56 |
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| 82 | #define RISCV_INTERRUPT_FRAME_T4 60 |
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| 83 | #define RISCV_INTERRUPT_FRAME_T5 64 |
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| 84 | #define RISCV_INTERRUPT_FRAME_T6 68 |
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[52352387] | 85 | |
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| 86 | #if __riscv_flen == 0 |
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| 87 | |
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[e43994d] | 88 | #define RISCV_INTERRUPT_FRAME_A0 72 |
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| 89 | #define RISCV_INTERRUPT_FRAME_A1 76 |
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| 90 | |
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| 91 | #define CPU_INTERRUPT_FRAME_SIZE 80 |
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[2086948a] | 92 | |
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[52352387] | 93 | #elif __riscv_flen == 32 |
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| 94 | |
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| 95 | #define RISCV_CONTEXT_FCSR 68 |
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| 96 | |
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[5694b0c] | 97 | #define RISCV_CONTEXT_F( x ) ( 72 + 4 * x ) |
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[52352387] | 98 | |
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| 99 | #define RISCV_INTERRUPT_FRAME_FCSR 72 |
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| 100 | |
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[5694b0c] | 101 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 76 + 4 * x ) |
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[52352387] | 102 | |
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| 103 | #define RISCV_INTERRUPT_FRAME_A0 156 |
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| 104 | #define RISCV_INTERRUPT_FRAME_A1 160 |
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| 105 | |
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| 106 | #define CPU_INTERRUPT_FRAME_SIZE 176 |
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| 107 | |
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| 108 | #elif __riscv_flen == 64 |
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| 109 | |
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| 110 | #define RISCV_CONTEXT_FCSR 68 |
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| 111 | |
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[5694b0c] | 112 | #define RISCV_CONTEXT_F( x ) ( 72 + 8 * x ) |
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[52352387] | 113 | |
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| 114 | #define RISCV_INTERRUPT_FRAME_FCSR 72 |
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| 115 | |
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[5694b0c] | 116 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 80 + 8 * x ) |
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[52352387] | 117 | |
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| 118 | #define RISCV_INTERRUPT_FRAME_A0 240 |
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| 119 | #define RISCV_INTERRUPT_FRAME_A1 244 |
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| 120 | |
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| 121 | #define CPU_INTERRUPT_FRAME_SIZE 256 |
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| 122 | |
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| 123 | #endif /* __riscv_flen */ |
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| 124 | |
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[5694b0c] | 125 | #define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 4 * x ) |
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| 126 | |
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[e43994d] | 127 | #elif __riscv_xlen == 64 |
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[9704d86f] | 128 | |
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[e43994d] | 129 | #define RISCV_CONTEXT_RA 8 |
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| 130 | #define RISCV_CONTEXT_SP 16 |
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| 131 | #define RISCV_CONTEXT_TP 24 |
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| 132 | #define RISCV_CONTEXT_S0 32 |
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| 133 | #define RISCV_CONTEXT_S1 40 |
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| 134 | #define RISCV_CONTEXT_S2 48 |
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| 135 | #define RISCV_CONTEXT_S3 56 |
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| 136 | #define RISCV_CONTEXT_S4 64 |
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| 137 | #define RISCV_CONTEXT_S5 72 |
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| 138 | #define RISCV_CONTEXT_S6 80 |
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| 139 | #define RISCV_CONTEXT_S7 88 |
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| 140 | #define RISCV_CONTEXT_S8 96 |
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| 141 | #define RISCV_CONTEXT_S9 104 |
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| 142 | #define RISCV_CONTEXT_S10 112 |
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| 143 | #define RISCV_CONTEXT_S11 120 |
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| 144 | |
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| 145 | #define RISCV_INTERRUPT_FRAME_MSTATUS 0 |
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| 146 | #define RISCV_INTERRUPT_FRAME_MEPC 8 |
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| 147 | #define RISCV_INTERRUPT_FRAME_A2 16 |
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| 148 | #define RISCV_INTERRUPT_FRAME_S0 24 |
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| 149 | #define RISCV_INTERRUPT_FRAME_S1 32 |
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| 150 | #define RISCV_INTERRUPT_FRAME_RA 40 |
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| 151 | #define RISCV_INTERRUPT_FRAME_A3 48 |
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| 152 | #define RISCV_INTERRUPT_FRAME_A4 56 |
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| 153 | #define RISCV_INTERRUPT_FRAME_A5 64 |
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| 154 | #define RISCV_INTERRUPT_FRAME_A6 72 |
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| 155 | #define RISCV_INTERRUPT_FRAME_A7 80 |
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| 156 | #define RISCV_INTERRUPT_FRAME_T0 88 |
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| 157 | #define RISCV_INTERRUPT_FRAME_T1 96 |
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| 158 | #define RISCV_INTERRUPT_FRAME_T2 104 |
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| 159 | #define RISCV_INTERRUPT_FRAME_T3 112 |
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| 160 | #define RISCV_INTERRUPT_FRAME_T4 120 |
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| 161 | #define RISCV_INTERRUPT_FRAME_T5 128 |
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| 162 | #define RISCV_INTERRUPT_FRAME_T6 136 |
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[52352387] | 163 | |
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| 164 | #if __riscv_flen == 0 |
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| 165 | |
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[e43994d] | 166 | #define RISCV_INTERRUPT_FRAME_A0 144 |
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| 167 | #define RISCV_INTERRUPT_FRAME_A1 152 |
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| 168 | |
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| 169 | #define CPU_INTERRUPT_FRAME_SIZE 160 |
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[2086948a] | 170 | |
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[52352387] | 171 | #elif __riscv_flen == 32 |
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| 172 | |
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| 173 | #define RISCV_CONTEXT_FCSR 128 |
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| 174 | |
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[5694b0c] | 175 | #define RISCV_CONTEXT_F( x ) ( 132 + 4 * x ) |
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[52352387] | 176 | |
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| 177 | #define RISCV_INTERRUPT_FRAME_FCSR 144 |
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| 178 | |
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[5694b0c] | 179 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 148 + 4 * x ) |
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[52352387] | 180 | |
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| 181 | #define RISCV_INTERRUPT_FRAME_A0 232 |
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| 182 | #define RISCV_INTERRUPT_FRAME_A1 240 |
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| 183 | |
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| 184 | #define CPU_INTERRUPT_FRAME_SIZE 256 |
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| 185 | |
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| 186 | #elif __riscv_flen == 64 |
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| 187 | |
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| 188 | #define RISCV_CONTEXT_FCSR 128 |
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| 189 | |
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[5694b0c] | 190 | #define RISCV_CONTEXT_F( x ) ( 136 + 8 * x ) |
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[52352387] | 191 | |
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| 192 | #define RISCV_INTERRUPT_FRAME_FCSR 144 |
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| 193 | |
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[5694b0c] | 194 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 152 + 8 * x ) |
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[52352387] | 195 | |
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| 196 | #define RISCV_INTERRUPT_FRAME_A0 312 |
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| 197 | #define RISCV_INTERRUPT_FRAME_A1 320 |
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| 198 | |
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| 199 | #define CPU_INTERRUPT_FRAME_SIZE 336 |
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| 200 | |
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| 201 | #endif /* __riscv_flen */ |
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| 202 | |
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[5694b0c] | 203 | #define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 8 * x ) |
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| 204 | |
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[2086948a] | 205 | #endif /* __riscv_xlen */ |
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| 206 | |
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[5694b0c] | 207 | #define RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 ) |
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| 208 | #define RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 ) |
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| 209 | #define RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 ) |
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| 210 | #define RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 ) |
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| 211 | #define RISCV_EXCEPTION_FRAME_S2 RISCV_EXCEPTION_FRAME_X( 4 ) |
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| 212 | #define RISCV_EXCEPTION_FRAME_S3 RISCV_EXCEPTION_FRAME_X( 5 ) |
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| 213 | #define RISCV_EXCEPTION_FRAME_S4 RISCV_EXCEPTION_FRAME_X( 6 ) |
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| 214 | #define RISCV_EXCEPTION_FRAME_S5 RISCV_EXCEPTION_FRAME_X( 7 ) |
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| 215 | #define RISCV_EXCEPTION_FRAME_S6 RISCV_EXCEPTION_FRAME_X( 8 ) |
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| 216 | #define RISCV_EXCEPTION_FRAME_S7 RISCV_EXCEPTION_FRAME_X( 9 ) |
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| 217 | #define RISCV_EXCEPTION_FRAME_S8 RISCV_EXCEPTION_FRAME_X( 10 ) |
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| 218 | #define RISCV_EXCEPTION_FRAME_S9 RISCV_EXCEPTION_FRAME_X( 11 ) |
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| 219 | #define RISCV_EXCEPTION_FRAME_S10 RISCV_EXCEPTION_FRAME_X( 12 ) |
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| 220 | #define RISCV_EXCEPTION_FRAME_S11 RISCV_EXCEPTION_FRAME_X( 13 ) |
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| 221 | |
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[52352387] | 222 | #if __riscv_flen > 0 |
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| 223 | |
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| 224 | #define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 ) |
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| 225 | #define RISCV_CONTEXT_FS1 RISCV_CONTEXT_F( 1 ) |
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| 226 | #define RISCV_CONTEXT_FS2 RISCV_CONTEXT_F( 2 ) |
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| 227 | #define RISCV_CONTEXT_FS3 RISCV_CONTEXT_F( 3 ) |
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| 228 | #define RISCV_CONTEXT_FS4 RISCV_CONTEXT_F( 4 ) |
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| 229 | #define RISCV_CONTEXT_FS5 RISCV_CONTEXT_F( 5 ) |
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| 230 | #define RISCV_CONTEXT_FS6 RISCV_CONTEXT_F( 6 ) |
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| 231 | #define RISCV_CONTEXT_FS7 RISCV_CONTEXT_F( 7 ) |
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| 232 | #define RISCV_CONTEXT_FS8 RISCV_CONTEXT_F( 8 ) |
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| 233 | #define RISCV_CONTEXT_FS9 RISCV_CONTEXT_F( 9 ) |
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| 234 | #define RISCV_CONTEXT_FS10 RISCV_CONTEXT_F( 10 ) |
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| 235 | #define RISCV_CONTEXT_FS11 RISCV_CONTEXT_F( 11 ) |
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| 236 | |
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| 237 | #define RISCV_INTERRUPT_FRAME_FT0 RISCV_INTERRUPT_FRAME_F( 0 ) |
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| 238 | #define RISCV_INTERRUPT_FRAME_FT1 RISCV_INTERRUPT_FRAME_F( 1 ) |
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| 239 | #define RISCV_INTERRUPT_FRAME_FT2 RISCV_INTERRUPT_FRAME_F( 2 ) |
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| 240 | #define RISCV_INTERRUPT_FRAME_FT3 RISCV_INTERRUPT_FRAME_F( 3 ) |
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| 241 | #define RISCV_INTERRUPT_FRAME_FT4 RISCV_INTERRUPT_FRAME_F( 4 ) |
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| 242 | #define RISCV_INTERRUPT_FRAME_FT5 RISCV_INTERRUPT_FRAME_F( 5 ) |
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| 243 | #define RISCV_INTERRUPT_FRAME_FT6 RISCV_INTERRUPT_FRAME_F( 6 ) |
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| 244 | #define RISCV_INTERRUPT_FRAME_FT7 RISCV_INTERRUPT_FRAME_F( 7 ) |
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| 245 | #define RISCV_INTERRUPT_FRAME_FT8 RISCV_INTERRUPT_FRAME_F( 8 ) |
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| 246 | #define RISCV_INTERRUPT_FRAME_FT9 RISCV_INTERRUPT_FRAME_F( 9 ) |
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| 247 | #define RISCV_INTERRUPT_FRAME_FT10 RISCV_INTERRUPT_FRAME_F( 10 ) |
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| 248 | #define RISCV_INTERRUPT_FRAME_FT11 RISCV_INTERRUPT_FRAME_F( 11 ) |
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| 249 | #define RISCV_INTERRUPT_FRAME_FA0 RISCV_INTERRUPT_FRAME_F( 12 ) |
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| 250 | #define RISCV_INTERRUPT_FRAME_FA1 RISCV_INTERRUPT_FRAME_F( 13 ) |
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| 251 | #define RISCV_INTERRUPT_FRAME_FA2 RISCV_INTERRUPT_FRAME_F( 14 ) |
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| 252 | #define RISCV_INTERRUPT_FRAME_FA3 RISCV_INTERRUPT_FRAME_F( 15 ) |
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| 253 | #define RISCV_INTERRUPT_FRAME_FA4 RISCV_INTERRUPT_FRAME_F( 16 ) |
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| 254 | #define RISCV_INTERRUPT_FRAME_FA5 RISCV_INTERRUPT_FRAME_F( 17 ) |
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| 255 | #define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 ) |
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| 256 | #define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 ) |
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| 257 | |
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[5694b0c] | 258 | #if __riscv_flen == 32 |
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| 259 | #define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 4 * x ) |
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| 260 | #elif __riscv_flen == 64 |
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| 261 | #define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 8 * x ) |
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| 262 | #endif |
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| 263 | |
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| 264 | #define RISCV_EXCEPTION_FRAME_FS0 RISCV_EXCEPTION_FRAME_F( 0 ) |
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| 265 | #define RISCV_EXCEPTION_FRAME_FS1 RISCV_EXCEPTION_FRAME_F( 1 ) |
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| 266 | #define RISCV_EXCEPTION_FRAME_FS2 RISCV_EXCEPTION_FRAME_F( 2 ) |
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| 267 | #define RISCV_EXCEPTION_FRAME_FS3 RISCV_EXCEPTION_FRAME_F( 3 ) |
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| 268 | #define RISCV_EXCEPTION_FRAME_FS4 RISCV_EXCEPTION_FRAME_F( 4 ) |
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| 269 | #define RISCV_EXCEPTION_FRAME_FS5 RISCV_EXCEPTION_FRAME_F( 5 ) |
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| 270 | #define RISCV_EXCEPTION_FRAME_FS6 RISCV_EXCEPTION_FRAME_F( 6 ) |
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| 271 | #define RISCV_EXCEPTION_FRAME_FS7 RISCV_EXCEPTION_FRAME_F( 7 ) |
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| 272 | #define RISCV_EXCEPTION_FRAME_FS8 RISCV_EXCEPTION_FRAME_F( 8 ) |
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| 273 | #define RISCV_EXCEPTION_FRAME_FS9 RISCV_EXCEPTION_FRAME_F( 9 ) |
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| 274 | #define RISCV_EXCEPTION_FRAME_FS10 RISCV_EXCEPTION_FRAME_F( 10 ) |
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| 275 | #define RISCV_EXCEPTION_FRAME_FS11 RISCV_EXCEPTION_FRAME_F( 11 ) |
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| 276 | |
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[52352387] | 277 | #endif /* __riscv_flen */ |
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| 278 | |
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[660db8c8] | 279 | #ifndef ASM |
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| 280 | |
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| 281 | #ifdef __cplusplus |
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| 282 | extern "C" { |
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| 283 | #endif |
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| 284 | |
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[e755782] | 285 | #ifdef __riscv_atomic |
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| 286 | typedef struct { |
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| 287 | uint64_t clear_reservations; |
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| 288 | uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ]; |
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| 289 | } CPU_Per_CPU_control; |
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| 290 | #endif |
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| 291 | |
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[8db3f0e] | 292 | struct Per_CPU_Control; |
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| 293 | |
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| 294 | void _RISCV_Interrupt_dispatch( |
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| 295 | uintptr_t mcause, |
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| 296 | struct Per_CPU_Control *cpu_self |
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| 297 | ); |
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| 298 | |
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[e07b51a7] | 299 | static inline uint32_t _RISCV_Read_FCSR( void ) |
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| 300 | { |
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| 301 | uint32_t fcsr; |
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| 302 | |
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| 303 | __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) ); |
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| 304 | |
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| 305 | return fcsr; |
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| 306 | } |
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| 307 | |
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[0fd8287] | 308 | #ifdef RTEMS_SMP |
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| 309 | |
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| 310 | static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) |
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| 311 | { |
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| 312 | struct Per_CPU_Control *cpu_self; |
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| 313 | |
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| 314 | __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) ); |
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| 315 | |
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| 316 | return cpu_self; |
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| 317 | } |
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| 318 | |
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| 319 | #define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control() |
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| 320 | |
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| 321 | #endif /* RTEMS_SMP */ |
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| 322 | |
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[42f2fdfd] | 323 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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| 324 | |
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| 325 | void _CPU_Context_validate( uintptr_t pattern ); |
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| 326 | |
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[3a646426] | 327 | RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) |
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| 328 | { |
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| 329 | __asm__ volatile ( "unimp" ); |
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| 330 | } |
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| 331 | |
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[b74353e] | 332 | RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) |
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| 333 | { |
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| 334 | __asm__ volatile ( "nop" ); |
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| 335 | } |
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| 336 | |
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[660db8c8] | 337 | #ifdef __cplusplus |
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| 338 | } |
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| 339 | #endif |
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| 340 | |
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| 341 | #endif /* ASM */ |
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| 342 | |
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| 343 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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