1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief CPU Port Implementation API |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG |
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9 | * |
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10 | * Redistribution and use in source and binary forms, with or without |
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11 | * modification, are permitted provided that the following conditions |
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12 | * are met: |
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13 | * 1. Redistributions of source code must retain the above copyright |
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14 | * notice, this list of conditions and the following disclaimer. |
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15 | * 2. Redistributions in binary form must reproduce the above copyright |
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16 | * notice, this list of conditions and the following disclaimer in the |
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17 | * documentation and/or other materials provided with the distribution. |
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18 | * |
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19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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29 | * SUCH DAMAGE. |
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30 | */ |
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31 | |
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32 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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33 | #define _RTEMS_SCORE_CPUIMPL_H |
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34 | |
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35 | #include <rtems/score/cpu.h> |
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36 | |
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37 | /** |
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38 | * @defgroup RTEMSScoreCPURISCV RISC-V |
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39 | * |
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40 | * @ingroup RTEMSScoreCPU |
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41 | * |
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42 | * @brief RISCV Architecture Support |
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43 | * |
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44 | * @{ |
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45 | */ |
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46 | |
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47 | #if defined(__riscv_atomic) && __riscv_xlen == 64 |
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48 | #define CPU_PER_CPU_CONTROL_SIZE 48 |
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49 | #elif defined(__riscv_atomic) && __riscv_xlen == 32 |
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50 | #define CPU_PER_CPU_CONTROL_SIZE 32 |
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51 | #elif __riscv_xlen == 64 |
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52 | #define CPU_PER_CPU_CONTROL_SIZE 32 |
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53 | #elif __riscv_xlen == 32 |
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54 | #define CPU_PER_CPU_CONTROL_SIZE 16 |
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55 | #endif |
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56 | |
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57 | #define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 |
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58 | |
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59 | #ifdef RTEMS_SMP |
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60 | #define RISCV_CONTEXT_IS_EXECUTING 0 |
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61 | #endif |
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62 | |
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63 | #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4 |
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64 | |
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65 | #if __riscv_xlen == 32 |
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66 | |
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67 | #define RISCV_CONTEXT_RA 8 |
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68 | #define RISCV_CONTEXT_SP 12 |
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69 | #define RISCV_CONTEXT_TP 16 |
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70 | #define RISCV_CONTEXT_S0 20 |
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71 | #define RISCV_CONTEXT_S1 24 |
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72 | #define RISCV_CONTEXT_S2 28 |
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73 | #define RISCV_CONTEXT_S3 32 |
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74 | #define RISCV_CONTEXT_S4 36 |
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75 | #define RISCV_CONTEXT_S5 40 |
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76 | #define RISCV_CONTEXT_S6 44 |
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77 | #define RISCV_CONTEXT_S7 48 |
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78 | #define RISCV_CONTEXT_S8 52 |
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79 | #define RISCV_CONTEXT_S9 56 |
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80 | #define RISCV_CONTEXT_S10 60 |
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81 | #define RISCV_CONTEXT_S11 64 |
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82 | |
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83 | #define RISCV_INTERRUPT_FRAME_MSTATUS 0 |
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84 | #define RISCV_INTERRUPT_FRAME_MEPC 4 |
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85 | #define RISCV_INTERRUPT_FRAME_A2 8 |
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86 | #define RISCV_INTERRUPT_FRAME_S0 12 |
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87 | #define RISCV_INTERRUPT_FRAME_S1 16 |
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88 | #define RISCV_INTERRUPT_FRAME_RA 20 |
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89 | #define RISCV_INTERRUPT_FRAME_A3 24 |
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90 | #define RISCV_INTERRUPT_FRAME_A4 28 |
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91 | #define RISCV_INTERRUPT_FRAME_A5 32 |
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92 | #define RISCV_INTERRUPT_FRAME_A6 36 |
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93 | #define RISCV_INTERRUPT_FRAME_A7 40 |
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94 | #define RISCV_INTERRUPT_FRAME_T0 44 |
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95 | #define RISCV_INTERRUPT_FRAME_T1 48 |
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96 | #define RISCV_INTERRUPT_FRAME_T2 52 |
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97 | #define RISCV_INTERRUPT_FRAME_T3 56 |
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98 | #define RISCV_INTERRUPT_FRAME_T4 60 |
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99 | #define RISCV_INTERRUPT_FRAME_T5 64 |
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100 | #define RISCV_INTERRUPT_FRAME_T6 68 |
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101 | |
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102 | #if __riscv_flen == 0 |
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103 | |
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104 | #define RISCV_INTERRUPT_FRAME_A0 72 |
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105 | #define RISCV_INTERRUPT_FRAME_A1 76 |
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106 | |
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107 | #define CPU_INTERRUPT_FRAME_SIZE 80 |
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108 | |
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109 | #elif __riscv_flen == 32 |
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110 | |
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111 | #define RISCV_CONTEXT_FCSR 68 |
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112 | |
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113 | #define RISCV_CONTEXT_F( x ) ( 72 + 4 * x ) |
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114 | |
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115 | #define RISCV_INTERRUPT_FRAME_FCSR 72 |
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116 | |
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117 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 76 + 4 * x ) |
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118 | |
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119 | #define RISCV_INTERRUPT_FRAME_A0 156 |
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120 | #define RISCV_INTERRUPT_FRAME_A1 160 |
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121 | |
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122 | #define CPU_INTERRUPT_FRAME_SIZE 176 |
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123 | |
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124 | #elif __riscv_flen == 64 |
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125 | |
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126 | #define RISCV_CONTEXT_FCSR 68 |
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127 | |
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128 | #define RISCV_CONTEXT_F( x ) ( 72 + 8 * x ) |
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129 | |
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130 | #define RISCV_INTERRUPT_FRAME_FCSR 72 |
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131 | |
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132 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 80 + 8 * x ) |
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133 | |
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134 | #define RISCV_INTERRUPT_FRAME_A0 240 |
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135 | #define RISCV_INTERRUPT_FRAME_A1 244 |
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136 | |
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137 | #define CPU_INTERRUPT_FRAME_SIZE 256 |
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138 | |
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139 | #endif /* __riscv_flen */ |
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140 | |
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141 | #define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 4 * x ) |
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142 | |
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143 | #elif __riscv_xlen == 64 |
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144 | |
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145 | #define RISCV_CONTEXT_RA 8 |
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146 | #define RISCV_CONTEXT_SP 16 |
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147 | #define RISCV_CONTEXT_TP 24 |
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148 | #define RISCV_CONTEXT_S0 32 |
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149 | #define RISCV_CONTEXT_S1 40 |
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150 | #define RISCV_CONTEXT_S2 48 |
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151 | #define RISCV_CONTEXT_S3 56 |
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152 | #define RISCV_CONTEXT_S4 64 |
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153 | #define RISCV_CONTEXT_S5 72 |
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154 | #define RISCV_CONTEXT_S6 80 |
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155 | #define RISCV_CONTEXT_S7 88 |
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156 | #define RISCV_CONTEXT_S8 96 |
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157 | #define RISCV_CONTEXT_S9 104 |
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158 | #define RISCV_CONTEXT_S10 112 |
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159 | #define RISCV_CONTEXT_S11 120 |
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160 | |
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161 | #define RISCV_INTERRUPT_FRAME_MSTATUS 0 |
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162 | #define RISCV_INTERRUPT_FRAME_MEPC 8 |
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163 | #define RISCV_INTERRUPT_FRAME_A2 16 |
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164 | #define RISCV_INTERRUPT_FRAME_S0 24 |
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165 | #define RISCV_INTERRUPT_FRAME_S1 32 |
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166 | #define RISCV_INTERRUPT_FRAME_RA 40 |
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167 | #define RISCV_INTERRUPT_FRAME_A3 48 |
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168 | #define RISCV_INTERRUPT_FRAME_A4 56 |
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169 | #define RISCV_INTERRUPT_FRAME_A5 64 |
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170 | #define RISCV_INTERRUPT_FRAME_A6 72 |
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171 | #define RISCV_INTERRUPT_FRAME_A7 80 |
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172 | #define RISCV_INTERRUPT_FRAME_T0 88 |
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173 | #define RISCV_INTERRUPT_FRAME_T1 96 |
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174 | #define RISCV_INTERRUPT_FRAME_T2 104 |
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175 | #define RISCV_INTERRUPT_FRAME_T3 112 |
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176 | #define RISCV_INTERRUPT_FRAME_T4 120 |
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177 | #define RISCV_INTERRUPT_FRAME_T5 128 |
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178 | #define RISCV_INTERRUPT_FRAME_T6 136 |
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179 | |
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180 | #if __riscv_flen == 0 |
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181 | |
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182 | #define RISCV_INTERRUPT_FRAME_A0 144 |
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183 | #define RISCV_INTERRUPT_FRAME_A1 152 |
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184 | |
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185 | #define CPU_INTERRUPT_FRAME_SIZE 160 |
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186 | |
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187 | #elif __riscv_flen == 32 |
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188 | |
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189 | #define RISCV_CONTEXT_FCSR 128 |
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190 | |
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191 | #define RISCV_CONTEXT_F( x ) ( 132 + 4 * x ) |
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192 | |
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193 | #define RISCV_INTERRUPT_FRAME_FCSR 144 |
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194 | |
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195 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 148 + 4 * x ) |
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196 | |
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197 | #define RISCV_INTERRUPT_FRAME_A0 232 |
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198 | #define RISCV_INTERRUPT_FRAME_A1 240 |
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199 | |
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200 | #define CPU_INTERRUPT_FRAME_SIZE 256 |
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201 | |
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202 | #elif __riscv_flen == 64 |
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203 | |
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204 | #define RISCV_CONTEXT_FCSR 128 |
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205 | |
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206 | #define RISCV_CONTEXT_F( x ) ( 136 + 8 * x ) |
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207 | |
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208 | #define RISCV_INTERRUPT_FRAME_FCSR 144 |
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209 | |
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210 | #define RISCV_INTERRUPT_FRAME_F( x ) ( 152 + 8 * x ) |
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211 | |
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212 | #define RISCV_INTERRUPT_FRAME_A0 312 |
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213 | #define RISCV_INTERRUPT_FRAME_A1 320 |
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214 | |
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215 | #define CPU_INTERRUPT_FRAME_SIZE 336 |
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216 | |
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217 | #endif /* __riscv_flen */ |
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218 | |
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219 | #define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 8 * x ) |
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220 | |
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221 | #endif /* __riscv_xlen */ |
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222 | |
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223 | #define RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 ) |
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224 | #define RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 ) |
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225 | #define RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 ) |
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226 | #define RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 ) |
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227 | #define RISCV_EXCEPTION_FRAME_S2 RISCV_EXCEPTION_FRAME_X( 4 ) |
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228 | #define RISCV_EXCEPTION_FRAME_S3 RISCV_EXCEPTION_FRAME_X( 5 ) |
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229 | #define RISCV_EXCEPTION_FRAME_S4 RISCV_EXCEPTION_FRAME_X( 6 ) |
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230 | #define RISCV_EXCEPTION_FRAME_S5 RISCV_EXCEPTION_FRAME_X( 7 ) |
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231 | #define RISCV_EXCEPTION_FRAME_S6 RISCV_EXCEPTION_FRAME_X( 8 ) |
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232 | #define RISCV_EXCEPTION_FRAME_S7 RISCV_EXCEPTION_FRAME_X( 9 ) |
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233 | #define RISCV_EXCEPTION_FRAME_S8 RISCV_EXCEPTION_FRAME_X( 10 ) |
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234 | #define RISCV_EXCEPTION_FRAME_S9 RISCV_EXCEPTION_FRAME_X( 11 ) |
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235 | #define RISCV_EXCEPTION_FRAME_S10 RISCV_EXCEPTION_FRAME_X( 12 ) |
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236 | #define RISCV_EXCEPTION_FRAME_S11 RISCV_EXCEPTION_FRAME_X( 13 ) |
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237 | |
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238 | #if __riscv_flen > 0 |
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239 | |
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240 | #define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 ) |
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241 | #define RISCV_CONTEXT_FS1 RISCV_CONTEXT_F( 1 ) |
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242 | #define RISCV_CONTEXT_FS2 RISCV_CONTEXT_F( 2 ) |
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243 | #define RISCV_CONTEXT_FS3 RISCV_CONTEXT_F( 3 ) |
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244 | #define RISCV_CONTEXT_FS4 RISCV_CONTEXT_F( 4 ) |
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245 | #define RISCV_CONTEXT_FS5 RISCV_CONTEXT_F( 5 ) |
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246 | #define RISCV_CONTEXT_FS6 RISCV_CONTEXT_F( 6 ) |
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247 | #define RISCV_CONTEXT_FS7 RISCV_CONTEXT_F( 7 ) |
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248 | #define RISCV_CONTEXT_FS8 RISCV_CONTEXT_F( 8 ) |
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249 | #define RISCV_CONTEXT_FS9 RISCV_CONTEXT_F( 9 ) |
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250 | #define RISCV_CONTEXT_FS10 RISCV_CONTEXT_F( 10 ) |
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251 | #define RISCV_CONTEXT_FS11 RISCV_CONTEXT_F( 11 ) |
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252 | |
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253 | #define RISCV_INTERRUPT_FRAME_FT0 RISCV_INTERRUPT_FRAME_F( 0 ) |
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254 | #define RISCV_INTERRUPT_FRAME_FT1 RISCV_INTERRUPT_FRAME_F( 1 ) |
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255 | #define RISCV_INTERRUPT_FRAME_FT2 RISCV_INTERRUPT_FRAME_F( 2 ) |
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256 | #define RISCV_INTERRUPT_FRAME_FT3 RISCV_INTERRUPT_FRAME_F( 3 ) |
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257 | #define RISCV_INTERRUPT_FRAME_FT4 RISCV_INTERRUPT_FRAME_F( 4 ) |
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258 | #define RISCV_INTERRUPT_FRAME_FT5 RISCV_INTERRUPT_FRAME_F( 5 ) |
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259 | #define RISCV_INTERRUPT_FRAME_FT6 RISCV_INTERRUPT_FRAME_F( 6 ) |
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260 | #define RISCV_INTERRUPT_FRAME_FT7 RISCV_INTERRUPT_FRAME_F( 7 ) |
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261 | #define RISCV_INTERRUPT_FRAME_FT8 RISCV_INTERRUPT_FRAME_F( 8 ) |
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262 | #define RISCV_INTERRUPT_FRAME_FT9 RISCV_INTERRUPT_FRAME_F( 9 ) |
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263 | #define RISCV_INTERRUPT_FRAME_FT10 RISCV_INTERRUPT_FRAME_F( 10 ) |
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264 | #define RISCV_INTERRUPT_FRAME_FT11 RISCV_INTERRUPT_FRAME_F( 11 ) |
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265 | #define RISCV_INTERRUPT_FRAME_FA0 RISCV_INTERRUPT_FRAME_F( 12 ) |
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266 | #define RISCV_INTERRUPT_FRAME_FA1 RISCV_INTERRUPT_FRAME_F( 13 ) |
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267 | #define RISCV_INTERRUPT_FRAME_FA2 RISCV_INTERRUPT_FRAME_F( 14 ) |
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268 | #define RISCV_INTERRUPT_FRAME_FA3 RISCV_INTERRUPT_FRAME_F( 15 ) |
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269 | #define RISCV_INTERRUPT_FRAME_FA4 RISCV_INTERRUPT_FRAME_F( 16 ) |
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270 | #define RISCV_INTERRUPT_FRAME_FA5 RISCV_INTERRUPT_FRAME_F( 17 ) |
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271 | #define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 ) |
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272 | #define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 ) |
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273 | |
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274 | #if __riscv_flen == 32 |
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275 | #define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 4 * x ) |
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276 | #elif __riscv_flen == 64 |
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277 | #define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 8 * x ) |
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278 | #endif |
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279 | |
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280 | #define RISCV_EXCEPTION_FRAME_FS0 RISCV_EXCEPTION_FRAME_F( 0 ) |
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281 | #define RISCV_EXCEPTION_FRAME_FS1 RISCV_EXCEPTION_FRAME_F( 1 ) |
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282 | #define RISCV_EXCEPTION_FRAME_FS2 RISCV_EXCEPTION_FRAME_F( 2 ) |
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283 | #define RISCV_EXCEPTION_FRAME_FS3 RISCV_EXCEPTION_FRAME_F( 3 ) |
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284 | #define RISCV_EXCEPTION_FRAME_FS4 RISCV_EXCEPTION_FRAME_F( 4 ) |
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285 | #define RISCV_EXCEPTION_FRAME_FS5 RISCV_EXCEPTION_FRAME_F( 5 ) |
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286 | #define RISCV_EXCEPTION_FRAME_FS6 RISCV_EXCEPTION_FRAME_F( 6 ) |
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287 | #define RISCV_EXCEPTION_FRAME_FS7 RISCV_EXCEPTION_FRAME_F( 7 ) |
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288 | #define RISCV_EXCEPTION_FRAME_FS8 RISCV_EXCEPTION_FRAME_F( 8 ) |
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289 | #define RISCV_EXCEPTION_FRAME_FS9 RISCV_EXCEPTION_FRAME_F( 9 ) |
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290 | #define RISCV_EXCEPTION_FRAME_FS10 RISCV_EXCEPTION_FRAME_F( 10 ) |
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291 | #define RISCV_EXCEPTION_FRAME_FS11 RISCV_EXCEPTION_FRAME_F( 11 ) |
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292 | |
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293 | #endif /* __riscv_flen */ |
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294 | |
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295 | #ifndef ASM |
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296 | |
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297 | #ifdef __cplusplus |
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298 | extern "C" { |
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299 | #endif |
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300 | |
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301 | static inline uint32_t _RISCV_Map_hardid_to_cpu_index( uint32_t hardid ) |
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302 | { |
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303 | return hardid - RISCV_BOOT_HARTID; |
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304 | } |
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305 | |
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306 | static inline uint32_t _RISCV_Map_cpu_index_to_hardid( uint32_t cpu_index ) |
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307 | { |
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308 | return cpu_index + RISCV_BOOT_HARTID; |
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309 | } |
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310 | |
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311 | /* Core Local Interruptor (CLINT) */ |
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312 | |
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313 | typedef union { |
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314 | uint64_t val_64; |
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315 | uint32_t val_32[2]; |
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316 | } RISCV_CLINT_timer_reg; |
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317 | |
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318 | typedef struct { |
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319 | uint32_t msip[4096]; |
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320 | RISCV_CLINT_timer_reg mtimecmp[2048]; |
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321 | uint32_t reserved_8000[4094]; |
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322 | RISCV_CLINT_timer_reg mtime; |
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323 | uint32_t reserved_c000[4096]; |
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324 | } RISCV_CLINT_regs; |
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325 | |
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326 | /* Platform-Level Interrupt Controller (PLIC) */ |
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327 | |
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328 | #define RISCV_PLIC_MAX_INTERRUPTS 1024 |
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329 | |
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330 | typedef struct { |
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331 | uint32_t priority_threshold; |
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332 | uint32_t claim_complete; |
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333 | uint32_t reserved_8[1022]; |
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334 | } RISCV_PLIC_hart_regs; |
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335 | |
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336 | typedef struct { |
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337 | uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS]; |
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338 | uint32_t pending[1024]; |
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339 | uint32_t enable[16320][32]; |
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340 | RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RISCV_BOOT_HARTID]; |
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341 | } RISCV_PLIC_regs; |
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342 | |
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343 | typedef struct { |
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344 | #ifdef __riscv_atomic |
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345 | uint64_t clear_reservations; |
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346 | uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ]; |
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347 | #endif |
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348 | volatile RISCV_PLIC_hart_regs *plic_hart_regs; |
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349 | volatile uint32_t *plic_m_ie; |
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350 | volatile RISCV_CLINT_timer_reg *clint_mtimecmp; |
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351 | volatile uint32_t *clint_msip; |
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352 | } CPU_Per_CPU_control; |
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353 | |
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354 | struct Per_CPU_Control; |
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355 | |
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356 | void _RISCV_Interrupt_dispatch( |
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357 | uintptr_t mcause, |
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358 | struct Per_CPU_Control *cpu_self |
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359 | ); |
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360 | |
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361 | static inline uint32_t _RISCV_Read_FCSR( void ) |
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362 | { |
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363 | uint32_t fcsr; |
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364 | |
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365 | __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) ); |
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366 | |
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367 | return fcsr; |
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368 | } |
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369 | |
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370 | /* |
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371 | * The RISC-V ISA provides a rdtime instruction, however, it is implemented in |
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372 | * most chips via a trap-and-emulate. Using this in machine mode makes no |
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373 | * sense. Use the memory-mapped mtime register directly instead. The address |
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374 | * of this register is platform-specific and provided via the device tree. |
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375 | * |
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376 | * To allow better code generation provide a const (_RISCV_Counter) and a |
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377 | * mutable (_RISCV_Counter_mutable) declaration for this pointer variable |
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378 | * (defined in assembler code). |
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379 | * |
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380 | * See code generated for this test case: |
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381 | * |
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382 | * extern volatile int * const c; |
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383 | * |
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384 | * extern volatile int *v; |
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385 | * |
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386 | * int fc(void) |
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387 | * { |
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388 | * int a = *c; |
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389 | * __asm__ volatile("" ::: "memory"); |
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390 | * return *c - a; |
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391 | * } |
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392 | * |
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393 | * int fv(void) |
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394 | * { |
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395 | * int a = *v; |
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396 | * __asm__ volatile("" ::: "memory"); |
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397 | * return *v - a; |
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398 | * } |
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399 | */ |
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400 | extern volatile uint32_t *_RISCV_Counter_mutable; |
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401 | |
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402 | /* |
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403 | * Initial value of _RISCV_Counter and _RISCV_Counter_mutable. Must be |
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404 | * provided by the BSP. |
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405 | */ |
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406 | extern volatile uint32_t _RISCV_Counter_register; |
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407 | |
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408 | #ifdef RTEMS_SMP |
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409 | |
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410 | static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) |
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411 | { |
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412 | struct Per_CPU_Control *cpu_self; |
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413 | |
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414 | __asm__ volatile ( |
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415 | ".option push\n" |
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416 | ".option arch, +zicsr\n" |
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417 | "csrr %0, mscratch\n" |
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418 | ".option pop" : |
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419 | "=r" ( cpu_self ) |
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420 | ); |
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421 | |
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422 | return cpu_self; |
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423 | } |
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424 | |
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425 | #define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control() |
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426 | |
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427 | #endif /* RTEMS_SMP */ |
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428 | |
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429 | RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); |
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430 | |
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431 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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432 | |
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433 | void _CPU_Context_validate( uintptr_t pattern ); |
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434 | |
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435 | static inline void _CPU_Instruction_illegal( void ) |
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436 | { |
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437 | __asm__ volatile ( "unimp" ); |
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438 | } |
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439 | |
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440 | static inline void _CPU_Instruction_no_operation( void ) |
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441 | { |
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442 | __asm__ volatile ( "nop" ); |
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443 | } |
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444 | |
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445 | static inline void _CPU_Use_thread_local_storage( |
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446 | const Context_Control *context |
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447 | ) |
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448 | { |
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449 | register uintptr_t tp __asm__( "tp" ); |
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450 | |
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451 | tp = context->tp; |
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452 | |
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453 | /* Make sure that the register assignment is not optimized away */ |
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454 | __asm__ volatile ( "" : : "r" ( tp ) ); |
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455 | } |
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456 | |
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457 | static inline void *_CPU_Get_TLS_thread_pointer( |
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458 | const Context_Control *context |
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459 | ) |
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460 | { |
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461 | return (void *) context->tp; |
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462 | } |
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463 | |
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464 | #ifdef __cplusplus |
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465 | } |
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466 | #endif |
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467 | |
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468 | #endif /* ASM */ |
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469 | |
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470 | /** @} */ |
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471 | |
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472 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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