1 | /** |
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2 | * @file |
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3 | * |
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4 | */ |
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5 | |
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6 | /* |
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7 | * Copyright (c) 2018 embedded brains GmbH |
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8 | * |
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9 | * Copyright (c) 2015 University of York. |
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10 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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11 | * |
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12 | * COPYRIGHT (c) 1989-1999. |
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13 | * On-Line Applications Research Corporation (OAR). |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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34 | * SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #ifndef _RISCV_CPU_H |
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38 | #define _RISCV_CPU_H |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | #include <rtems/score/basedefs.h> |
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45 | #include <rtems/score/riscv.h> |
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46 | |
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47 | #define RISCV_MSTATUS_MIE 0x8 |
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48 | |
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49 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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50 | |
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51 | #define CPU_HARDWARE_FP FALSE |
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52 | #define CPU_SOFTWARE_FP FALSE |
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53 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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54 | #define CPU_IDLE_TASK_IS_FP FALSE |
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55 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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56 | |
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57 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE |
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58 | |
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59 | #define CPU_STACK_GROWS_UP FALSE |
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60 | |
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61 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) |
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62 | #define CPU_BIG_ENDIAN FALSE |
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63 | #define CPU_LITTLE_ENDIAN TRUE |
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64 | #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 |
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65 | |
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66 | #define CPU_CACHE_LINE_BYTES 64 |
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67 | |
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68 | #if __riscv_xlen == 32 |
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69 | |
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70 | #define CPU_SIZEOF_POINTER 4 |
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71 | |
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72 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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73 | |
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74 | #elif __riscv_xlen == 64 |
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75 | |
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76 | #define CPU_SIZEOF_POINTER 8 |
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77 | |
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78 | #define CPU_STACK_MINIMUM_SIZE 8192 |
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79 | |
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80 | #endif /* __riscv_xlen */ |
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81 | |
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82 | /* RISC-V ELF psABI specification */ |
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83 | #define CPU_ALIGNMENT 16 |
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84 | |
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85 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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86 | |
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87 | /* RISC-V ELF psABI specification */ |
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88 | #define CPU_STACK_ALIGNMENT 16 |
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89 | |
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90 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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91 | |
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92 | /* |
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93 | * Processor defined structures required for cpukit/score. |
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94 | */ |
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95 | |
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96 | #ifndef ASM |
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97 | |
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98 | #if __riscv_flen == 32 |
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99 | typedef float RISCV_Float; |
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100 | #elif __riscv_flen == 64 |
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101 | typedef double RISCV_Float; |
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102 | #endif |
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103 | |
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104 | typedef struct { |
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105 | #ifdef RTEMS_SMP |
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106 | volatile uint32_t is_executing; |
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107 | #else |
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108 | uint32_t reserved; |
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109 | #endif |
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110 | uint32_t isr_dispatch_disable; |
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111 | uintptr_t ra; |
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112 | uintptr_t sp; |
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113 | uintptr_t tp; |
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114 | uintptr_t s0; |
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115 | uintptr_t s1; |
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116 | uintptr_t s2; |
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117 | uintptr_t s3; |
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118 | uintptr_t s4; |
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119 | uintptr_t s5; |
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120 | uintptr_t s6; |
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121 | uintptr_t s7; |
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122 | uintptr_t s8; |
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123 | uintptr_t s9; |
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124 | uintptr_t s10; |
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125 | uintptr_t s11; |
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126 | #if __riscv_flen > 0 |
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127 | uint32_t fcsr; |
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128 | RISCV_Float fs0; |
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129 | RISCV_Float fs1; |
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130 | RISCV_Float fs2; |
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131 | RISCV_Float fs3; |
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132 | RISCV_Float fs4; |
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133 | RISCV_Float fs5; |
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134 | RISCV_Float fs6; |
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135 | RISCV_Float fs7; |
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136 | RISCV_Float fs8; |
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137 | RISCV_Float fs9; |
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138 | RISCV_Float fs10; |
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139 | RISCV_Float fs11; |
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140 | #endif |
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141 | } Context_Control; |
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142 | |
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143 | #define _CPU_Context_Get_SP( _context ) \ |
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144 | (_context)->sp |
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145 | |
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146 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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147 | |
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148 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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149 | |
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150 | static inline uint32_t riscv_interrupt_disable( void ) |
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151 | { |
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152 | unsigned long mstatus; |
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153 | |
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154 | __asm__ volatile ( |
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155 | "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) : |
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156 | "=&r" ( mstatus ) |
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157 | ); |
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158 | |
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159 | return mstatus & RISCV_MSTATUS_MIE; |
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160 | } |
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161 | |
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162 | static inline void riscv_interrupt_enable( uint32_t level ) |
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163 | { |
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164 | __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) ); |
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165 | } |
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166 | |
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167 | #define _CPU_ISR_Disable( _level ) \ |
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168 | _level = riscv_interrupt_disable() |
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169 | |
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170 | #define _CPU_ISR_Enable( _level ) \ |
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171 | riscv_interrupt_enable( _level ) |
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172 | |
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173 | #define _CPU_ISR_Flash( _level ) \ |
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174 | do{ \ |
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175 | _CPU_ISR_Enable( _level ); \ |
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176 | riscv_interrupt_disable(); \ |
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177 | } while(0) |
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178 | |
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179 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) |
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180 | { |
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181 | return ( level & RISCV_MSTATUS_MIE ) != 0; |
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182 | } |
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183 | |
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184 | RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level ) |
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185 | { |
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186 | if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) { |
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187 | __asm__ volatile ( |
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188 | "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) |
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189 | ); |
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190 | } else { |
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191 | __asm__ volatile ( |
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192 | "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) |
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193 | ); |
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194 | } |
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195 | } |
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196 | |
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197 | uint32_t _CPU_ISR_Get_level( void ); |
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198 | |
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199 | /* end of ISR handler macros */ |
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200 | |
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201 | void _CPU_Context_Initialize( |
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202 | Context_Control *context, |
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203 | void *stack_area_begin, |
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204 | size_t stack_area_size, |
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205 | uint32_t new_level, |
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206 | void ( *entry_point )( void ), |
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207 | bool is_fp, |
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208 | void *tls_area |
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209 | ); |
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210 | |
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211 | #define _CPU_Context_Restart_self( _the_context ) \ |
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212 | _CPU_Context_restore( (_the_context) ) |
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213 | |
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214 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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215 | |
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216 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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217 | |
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218 | #define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE |
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219 | |
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220 | #define CPU_MAXIMUM_PROCESSORS 32 |
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221 | |
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222 | typedef uint16_t Priority_bit_map_Word; |
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223 | |
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224 | /* |
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225 | * See The RISC-V Instruction Set Manual, Volume II: RISC-V Privileged |
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226 | * Architectures V1.10, Table 3.6: Machine cause register (mcause) values after |
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227 | * trap. |
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228 | */ |
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229 | typedef enum { |
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230 | RISCV_INTERRUPT_SOFTWARE_USER = 0, |
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231 | RISCV_INTERRUPT_SOFTWARE_SUPERVISOR = 1, |
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232 | RISCV_INTERRUPT_SOFTWARE_MACHINE = 3, |
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233 | RISCV_INTERRUPT_TIMER_USER = 4, |
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234 | RISCV_INTERRUPT_TIMER_SUPERVISOR = 5, |
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235 | RISCV_INTERRUPT_TIMER_MACHINE = 7, |
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236 | RISCV_INTERRUPT_EXTERNAL_USER = 8, |
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237 | RISCV_INTERRUPT_EXTERNAL_SUPERVISOR = 9, |
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238 | RISCV_INTERRUPT_EXTERNAL_MACHINE = 11 |
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239 | } RISCV_Interrupt_code; |
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240 | |
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241 | /* |
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242 | * See The RISC-V Instruction Set Manual, Volume II: RISC-V Privileged |
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243 | * Architectures V1.10, Table 3.6: Machine cause register (mcause) values after |
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244 | * trap. |
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245 | */ |
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246 | typedef enum { |
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247 | RISCV_EXCEPTION_INSTRUCTION_ADDRESS_MISALIGNED = 0, |
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248 | RISCV_EXCEPTION_INSTRUCTION_ACCESS_FAULT = 1, |
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249 | RISCV_EXCEPTION_ILLEGAL_INSTRUCTION = 2, |
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250 | RISCV_EXCEPTION_BREAKPOINT = 3, |
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251 | RISCV_EXCEPTION_LOAD_ADDRESS_MISALIGNED = 4, |
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252 | RISCV_EXCEPTION_LOAD_ACCESS_FAULT = 5, |
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253 | RISCV_EXCEPTION_STORE_OR_AMO_ADDRESS_MISALIGNED = 6, |
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254 | RISCV_EXCEPTION_STORE_OR_AMO_ACCESS_FAULT = 7, |
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255 | RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_U_MODE = 8, |
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256 | RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_S_MODE = 9, |
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257 | RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_M_MODE = 11, |
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258 | RISCV_EXCEPTION_INSTRUCTION_PAGE_FAULT = 12, |
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259 | RISCV_EXCEPTION_LOAD_PAGE_FAULT = 13, |
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260 | RISCV_EXCEPTION_STORE_OR_AMO_PAGE_FAULT = 15 |
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261 | } RISCV_Exception_code; |
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262 | |
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263 | typedef struct { |
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264 | uintptr_t mstatus; |
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265 | uintptr_t mepc; |
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266 | uintptr_t a2; |
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267 | uintptr_t s0; |
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268 | uintptr_t s1; |
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269 | uintptr_t ra; |
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270 | uintptr_t a3; |
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271 | uintptr_t a4; |
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272 | uintptr_t a5; |
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273 | uintptr_t a6; |
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274 | uintptr_t a7; |
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275 | uintptr_t t0; |
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276 | uintptr_t t1; |
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277 | uintptr_t t2; |
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278 | uintptr_t t3; |
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279 | uintptr_t t4; |
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280 | uintptr_t t5; |
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281 | uintptr_t t6; |
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282 | #if __riscv_flen > 0 |
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283 | uint32_t fcsr; |
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284 | RISCV_Float ft0; |
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285 | RISCV_Float ft1; |
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286 | RISCV_Float ft2; |
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287 | RISCV_Float ft3; |
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288 | RISCV_Float ft4; |
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289 | RISCV_Float ft5; |
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290 | RISCV_Float ft6; |
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291 | RISCV_Float ft7; |
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292 | RISCV_Float ft8; |
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293 | RISCV_Float ft9; |
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294 | RISCV_Float ft10; |
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295 | RISCV_Float ft11; |
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296 | RISCV_Float fa0; |
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297 | RISCV_Float fa1; |
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298 | RISCV_Float fa2; |
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299 | RISCV_Float fa3; |
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300 | RISCV_Float fa4; |
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301 | RISCV_Float fa5; |
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302 | RISCV_Float fa6; |
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303 | RISCV_Float fa7; |
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304 | #endif |
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305 | uintptr_t a0; |
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306 | uintptr_t a1; |
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307 | } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame; |
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308 | |
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309 | typedef struct { |
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310 | CPU_Interrupt_frame Interrupt_frame; |
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311 | uintptr_t mcause; |
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312 | uintptr_t sp; |
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313 | uintptr_t gp; |
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314 | uintptr_t tp; |
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315 | uintptr_t s2; |
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316 | uintptr_t s3; |
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317 | uintptr_t s4; |
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318 | uintptr_t s5; |
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319 | uintptr_t s6; |
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320 | uintptr_t s7; |
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321 | uintptr_t s8; |
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322 | uintptr_t s9; |
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323 | uintptr_t s10; |
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324 | uintptr_t s11; |
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325 | #if __riscv_flen > 0 |
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326 | RISCV_Float fs0; |
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327 | RISCV_Float fs1; |
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328 | RISCV_Float fs2; |
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329 | RISCV_Float fs3; |
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330 | RISCV_Float fs4; |
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331 | RISCV_Float fs5; |
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332 | RISCV_Float fs6; |
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333 | RISCV_Float fs7; |
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334 | RISCV_Float fs8; |
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335 | RISCV_Float fs9; |
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336 | RISCV_Float fs10; |
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337 | RISCV_Float fs11; |
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338 | #endif |
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339 | } CPU_Exception_frame; |
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340 | |
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341 | /** |
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342 | * @brief Prints the exception frame via printk(). |
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343 | * |
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344 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
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345 | */ |
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346 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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347 | |
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348 | |
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349 | /* end of Priority handler macros */ |
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350 | |
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351 | /* functions */ |
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352 | |
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353 | /* |
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354 | * _CPU_Initialize |
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355 | * |
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356 | * This routine performs CPU dependent initialization. |
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357 | * |
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358 | */ |
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359 | |
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360 | void _CPU_Initialize( |
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361 | void |
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362 | ); |
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363 | |
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364 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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365 | |
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366 | /* |
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367 | * _CPU_Context_switch |
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368 | * |
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369 | * This routine switches from the run context to the heir context. |
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370 | * |
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371 | * RISCV Specific Information: |
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372 | * |
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373 | * Please see the comments in the .c file for a description of how |
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374 | * this function works. There are several things to be aware of. |
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375 | */ |
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376 | |
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377 | void _CPU_Context_switch( |
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378 | Context_Control *run, |
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379 | Context_Control *heir |
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380 | ); |
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381 | |
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382 | RTEMS_NO_RETURN void _CPU_Context_switch_no_return( |
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383 | Context_Control *executing, |
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384 | Context_Control *heir |
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385 | ); |
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386 | |
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387 | /* |
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388 | * _CPU_Context_restore |
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389 | * |
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390 | * This routine is generally used only to restart self in an |
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391 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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392 | * |
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393 | * NOTE: May be unnecessary to reload some registers. |
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394 | * |
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395 | */ |
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396 | |
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397 | RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); |
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398 | |
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399 | /* The following routine swaps the endian format of an unsigned int. |
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400 | * It must be static because it is referenced indirectly. |
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401 | * |
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402 | * This version will work on any processor, but if there is a better |
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403 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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404 | * |
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405 | * swap least significant two bytes with 16-bit rotate |
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406 | * swap upper and lower 16-bits |
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407 | * swap most significant two bytes with 16-bit rotate |
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408 | * |
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409 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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410 | * a single instruction (e.g. i486). It is probably best to avoid |
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411 | * an "endian swapping control bit" in the CPU. One good reason is |
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412 | * that interrupts would probably have to be disabled to insure that |
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413 | * an interrupt does not try to access the same "chunk" with the wrong |
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414 | * endian. Another good reason is that on some CPUs, the endian bit |
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415 | * endianness for ALL fetches -- both code and data -- so the code |
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416 | * will be fetched incorrectly. |
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417 | * |
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418 | */ |
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419 | |
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420 | static inline uint32_t CPU_swap_u32( |
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421 | uint32_t value |
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422 | ) |
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423 | { |
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424 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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425 | |
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426 | byte4 = (value >> 24) & 0xff; |
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427 | byte3 = (value >> 16) & 0xff; |
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428 | byte2 = (value >> 8) & 0xff; |
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429 | byte1 = value & 0xff; |
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430 | |
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431 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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432 | return ( swapped ); |
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433 | } |
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434 | |
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435 | #define CPU_swap_u16( value ) \ |
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436 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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437 | |
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438 | typedef uint32_t CPU_Counter_ticks; |
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439 | |
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440 | uint32_t _CPU_Counter_frequency( void ); |
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441 | |
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442 | extern volatile uint32_t * const _RISCV_Counter; |
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443 | |
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444 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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445 | |
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446 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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447 | CPU_Counter_ticks second, |
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448 | CPU_Counter_ticks first |
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449 | ) |
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450 | { |
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451 | return second - first; |
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452 | } |
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453 | |
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454 | #ifdef RTEMS_SMP |
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455 | |
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456 | uint32_t _CPU_SMP_Initialize( void ); |
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457 | |
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458 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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459 | |
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460 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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461 | |
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462 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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463 | |
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464 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
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465 | { |
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466 | unsigned long mhartid; |
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467 | |
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468 | __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) ); |
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469 | |
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470 | return (uint32_t) mhartid; |
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471 | } |
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472 | |
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473 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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474 | |
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475 | static inline bool _CPU_Context_Get_is_executing( |
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476 | const Context_Control *context |
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477 | ) |
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478 | { |
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479 | return context->is_executing; |
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480 | } |
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481 | |
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482 | static inline void _CPU_Context_Set_is_executing( |
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483 | Context_Control *context, |
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484 | bool is_executing |
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485 | ) |
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486 | { |
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487 | context->is_executing = is_executing; |
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488 | } |
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489 | |
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490 | #endif /* RTEMS_SMP */ |
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491 | |
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492 | /** Type that can store a 32-bit integer or a pointer. */ |
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493 | typedef uintptr_t CPU_Uint32ptr; |
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494 | |
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495 | #endif /* ASM */ |
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496 | |
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497 | #ifdef __cplusplus |
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498 | } |
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499 | #endif |
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500 | |
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501 | #endif |
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