source: rtems/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @ 5b88ec5

5
Last change on this file since 5b88ec5 was 5b88ec5, checked in by Joel Sherrill <joel@…>, on Mar 8, 2018 at 11:23:21 PM

riscv/include/rtems/score/types.h: Eliminate this file

Updates #3327.

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1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *
7 * Copyright (c) 2015 University of York.
8 * Hesham Almatary <hesham@alumni.york.ac.uk>
9 *
10 * COPYRIGHT (c) 1989-1999.
11 * On-Line Applications Research Corporation (OAR).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef _RISCV_CPU_H
36#define _RISCV_CPU_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/basedefs.h>
43#include <rtems/score/riscv.h> /* pick up machine definitions */
44#include <rtems/score/riscv-utility.h>
45#ifndef ASM
46#include <rtems/bspIo.h>
47#include <stdint.h>
48#include <stdio.h> /* for printk */
49#endif
50
51#define CPU_INLINE_ENABLE_DISPATCH       FALSE
52#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
53#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
54#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
55#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
56#define CPU_ISR_PASSES_FRAME_POINTER 1
57#define CPU_HARDWARE_FP                  FALSE
58#define CPU_SOFTWARE_FP                  FALSE
59#define CPU_ALL_TASKS_ARE_FP             FALSE
60#define CPU_IDLE_TASK_IS_FP              FALSE
61#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
62#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
63#define CPU_STACK_GROWS_UP               FALSE
64
65#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64)))
66#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
67#define CPU_BIG_ENDIAN                           FALSE
68#define CPU_LITTLE_ENDIAN                        TRUE
69#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
70
71/*
72 *  Processor defined structures required for cpukit/score.
73 */
74
75#ifndef ASM
76
77typedef struct {
78  /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
79  unsigned long x[32];
80
81  /* Special purpose registers */
82  unsigned long mstatus;
83  unsigned long mcause;
84  unsigned long mepc;
85#ifdef RTEMS_SMP
86  /**
87   * @brief On SMP configurations the thread context must contain a boolean
88   * indicator to signal if this context is executing on a processor.
89   *
90   * This field must be updated during a context switch.  The context switch
91   * to the heir must wait until the heir context indicates that it is no
92   * longer executing on a processor.  The context switch must also check if
93   * a thread dispatch is necessary to honor updates of the heir thread for
94   * this processor.  This indicator must be updated using an atomic test and
95   * set operation to ensure that at most one processor uses the heir
96   * context at the same time.
97   *
98   * @code
99   * void _CPU_Context_switch(
100   *   Context_Control *executing,
101   *   Context_Control *heir
102   * )
103   * {
104   *   save( executing );
105   *
106   *   executing->is_executing = false;
107   *   memory_barrier();
108   *
109   *   if ( test_and_set( &heir->is_executing ) ) {
110   *     do {
111   *       Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot();
112   *
113   *       if ( cpu_self->dispatch_necessary ) {
114   *         heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
115   *       }
116   *     } while ( test_and_set( &heir->is_executing ) );
117   *   }
118   *
119   *   restore( heir );
120   * }
121   * @endcode
122   */
123  volatile bool is_executing;
124#endif
125} Context_Control;
126
127#define _CPU_Context_Get_SP( _context ) \
128  (_context)->x[2]
129
130typedef struct {
131  /** TODO FPU registers are listed here */
132  double  some_float_register;
133} Context_Control_fp;
134
135typedef Context_Control CPU_Interrupt_frame;
136
137#define CPU_CONTEXT_FP_SIZE  0
138Context_Control_fp  _CPU_Null_fp_context;
139
140#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
141#if __riscv_xlen == 32
142#define CPU_STACK_MINIMUM_SIZE  4096
143#else
144#define CPU_STACK_MINIMUM_SIZE  4096 * 2
145#endif
146#define CPU_ALIGNMENT 8
147#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
148#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
149#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
150#define CPU_STACK_ALIGNMENT        8
151#define _CPU_Initialize_vectors()
152
153/*
154 *  Disable all interrupts for an RTEMS critical section.  The previous
155 *  level is returned in _level.
156 *
157 */
158
159static inline unsigned long riscv_interrupt_disable( void )
160{
161  register unsigned long status = read_csr(mstatus);
162  clear_csr(mstatus, MSTATUS_MIE);
163  return status;
164}
165
166static inline void riscv_interrupt_enable(unsigned long level)
167{
168  write_csr(mstatus, level);
169}
170
171#define _CPU_ISR_Disable( _level ) \
172    _level = riscv_interrupt_disable()
173
174#define _CPU_ISR_Enable( _level )  \
175  riscv_interrupt_enable( _level )
176
177#define _CPU_ISR_Flash( _level ) \
178  do{ \
179      _CPU_ISR_Enable( _level ); \
180      riscv_interrupt_disable(); \
181    } while(0)
182
183RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
184{
185  return ( level & MSTATUS_MIE ) != 0;
186}
187
188void _CPU_ISR_Set_level( unsigned long level );
189
190unsigned long _CPU_ISR_Get_level( void );
191
192/* end of ISR handler macros */
193
194/* Context handler macros */
195#define RISCV_GCC_RED_ZONE_SIZE 128
196
197void _CPU_Context_Initialize(
198  Context_Control *context,
199  void *stack_area_begin,
200  size_t stack_area_size,
201  unsigned long new_level,
202  void (*entry_point)( void ),
203  bool is_fp,
204  void *tls_area
205);
206
207#define _CPU_Context_Restart_self( _the_context ) \
208   _CPU_Context_restore( (_the_context) )
209
210
211#define _CPU_Context_Fp_start( _base, _offset ) \
212   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
213
214#define _CPU_Context_Initialize_fp( _destination ) \
215  { \
216   *(*(_destination)) = _CPU_Null_fp_context; \
217  }
218
219extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN;
220
221/* end of Fatal Error manager macros */
222
223#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
224#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
225
226#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
227
228#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
229  { \
230    (_output) = 0;   /* do something to prevent warnings */ \
231  }
232#endif
233
234/* end of Bitfield handler macros */
235
236/*
237 *  This routine builds the mask which corresponds to the bit fields
238 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
239 *  for that routine.
240 *
241 */
242
243#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
244
245#define _CPU_Priority_Mask( _bit_number ) \
246    (1 << _bit_number)
247
248#endif
249
250#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
251
252#define _CPU_Priority_bits_index( _priority ) \
253  (_priority)
254
255#endif
256
257#define CPU_MAXIMUM_PROCESSORS 32
258
259#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE
260#define CPU_TIMESTAMP_USE_INT64 TRUE
261#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
262
263typedef struct {
264  /* There is no CPU specific per-CPU state */
265} CPU_Per_CPU_control;
266#endif /* ASM */
267
268#if __riscv_xlen == 32
269#define CPU_SIZEOF_POINTER 4
270
271/* 32-bit load/store instructions */
272#define LREG lw
273#define SREG sw
274
275#define CPU_EXCEPTION_FRAME_SIZE 128
276#else /* xlen = 64 */
277#define CPU_SIZEOF_POINTER 8
278
279/* 64-bit load/store instructions */
280#define LREG ld
281#define SREG sd
282
283#define CPU_EXCEPTION_FRAME_SIZE 256
284#endif
285
286#define CPU_PER_CPU_CONTROL_SIZE 0
287
288#ifndef ASM
289typedef uint16_t Priority_bit_map_Word;
290
291typedef struct {
292  unsigned long x[32];;
293} CPU_Exception_frame;
294
295/**
296 * @brief Prints the exception frame via printk().
297 *
298 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
299 */
300void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
301
302
303/* end of Priority handler macros */
304
305/* functions */
306
307/*
308 *  _CPU_Initialize
309 *
310 *  This routine performs CPU dependent initialization.
311 *
312 */
313
314void _CPU_Initialize(
315  void
316);
317
318/*
319 *  _CPU_ISR_install_raw_handler
320 *
321 *  This routine installs a "raw" interrupt handler directly into the
322 *  processor's vector table.
323 *
324 */
325
326void _CPU_ISR_install_raw_handler(
327  uint32_t    vector,
328  proc_ptr    new_handler,
329  proc_ptr   *old_handler
330);
331
332/*
333 *  _CPU_ISR_install_vector
334 *
335 *  This routine installs an interrupt vector.
336 *
337 *  NO_CPU Specific Information:
338 *
339 *  XXX document implementation including references if appropriate
340 */
341
342void _CPU_ISR_install_vector(
343  unsigned long    vector,
344  proc_ptr   new_handler,
345  proc_ptr   *old_handler
346);
347
348/*
349 *  _CPU_Install_interrupt_stack
350 *
351 *  This routine installs the hardware interrupt stack pointer.
352 *
353 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
354 *         is TRUE.
355 *
356 */
357
358void _CPU_Install_interrupt_stack( void );
359
360/*
361 *  _CPU_Thread_Idle_body
362 *
363 *  This routine is the CPU dependent IDLE thread body.
364 *
365 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
366 *         is TRUE.
367 *
368 */
369
370void *_CPU_Thread_Idle_body( uintptr_t ignored );
371
372/*
373 *  _CPU_Context_switch
374 *
375 *  This routine switches from the run context to the heir context.
376 *
377 *  RISCV Specific Information:
378 *
379 *  Please see the comments in the .c file for a description of how
380 *  this function works. There are several things to be aware of.
381 */
382
383void _CPU_Context_switch(
384  Context_Control  *run,
385  Context_Control  *heir
386);
387
388/*
389 *  _CPU_Context_restore
390 *
391 *  This routine is generally used only to restart self in an
392 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
393 *
394 *  NOTE: May be unnecessary to reload some registers.
395 *
396 */
397
398void _CPU_Context_restore(
399  Context_Control *new_context
400) RTEMS_NO_RETURN;
401
402/*
403 *  _CPU_Context_save_fp
404 *
405 *  This routine saves the floating point context passed to it.
406 *
407 */
408
409void _CPU_Context_save_fp(
410  void **fp_context_ptr
411);
412
413/*
414 *  _CPU_Context_restore_fp
415 *
416 *  This routine restores the floating point context passed to it.
417 *
418 */
419
420void _CPU_Context_restore_fp(
421  void **fp_context_ptr
422);
423
424/*  The following routine swaps the endian format of an unsigned int.
425 *  It must be static because it is referenced indirectly.
426 *
427 *  This version will work on any processor, but if there is a better
428 *  way for your CPU PLEASE use it.  The most common way to do this is to:
429 *
430 *     swap least significant two bytes with 16-bit rotate
431 *     swap upper and lower 16-bits
432 *     swap most significant two bytes with 16-bit rotate
433 *
434 *  Some CPUs have special instructions which swap a 32-bit quantity in
435 *  a single instruction (e.g. i486).  It is probably best to avoid
436 *  an "endian swapping control bit" in the CPU.  One good reason is
437 *  that interrupts would probably have to be disabled to insure that
438 *  an interrupt does not try to access the same "chunk" with the wrong
439 *  endian.  Another good reason is that on some CPUs, the endian bit
440 *  endianness for ALL fetches -- both code and data -- so the code
441 *  will be fetched incorrectly.
442 *
443 */
444
445static inline uint32_t CPU_swap_u32(
446  uint32_t value
447)
448{
449  uint32_t   byte1, byte2, byte3, byte4, swapped;
450
451  byte4 = (value >> 24) & 0xff;
452  byte3 = (value >> 16) & 0xff;
453  byte2 = (value >> 8)  & 0xff;
454  byte1 =  value        & 0xff;
455
456  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
457  return ( swapped );
458}
459
460#define CPU_swap_u16( value ) \
461  (((value&0xff) << 8) | ((value >> 8)&0xff))
462
463static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
464{
465  /* TODO */
466}
467
468static inline void _CPU_Context_validate( uintptr_t pattern )
469{
470  while (1) {
471    /* TODO */
472  }
473}
474
475typedef uint32_t CPU_Counter_ticks;
476
477CPU_Counter_ticks _CPU_Counter_read( void );
478
479#ifdef RTEMS_SMP
480/**
481 * @brief Performs CPU specific SMP initialization in the context of the boot
482 * processor.
483 *
484 * This function is invoked on the boot processor during system
485 * initialization.  All interrupt stacks are allocated at this point in case
486 * the CPU port allocates the interrupt stacks.  This function is called
487 * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
488 * used.
489 *
490 * @return The count of physically or virtually available processors.
491 * Depending on the configuration the application may use not all processors.
492 */
493uint32_t _CPU_SMP_Initialize( void );
494
495/**
496 * @brief Starts a processor specified by its index.
497 *
498 * This function is invoked on the boot processor during system
499 * initialization.
500 *
501 * This function will be called after _CPU_SMP_Initialize().
502 *
503 * @param[in] cpu_index The processor index.
504 *
505 * @retval true Successful operation.
506 * @retval false Unable to start this processor.
507 */
508bool _CPU_SMP_Start_processor( uint32_t cpu_index );
509
510/**
511 * @brief Performs final steps of CPU specific SMP initialization in the
512 * context of the boot processor.
513 *
514 * This function is invoked on the boot processor during system
515 * initialization.
516 *
517 * This function will be called after all processors requested by the
518 * application have been started.
519 *
520 * @param[in] cpu_count The minimum value of the count of processors
521 * requested by the application configuration and the count of physically or
522 * virtually available processors.
523 */
524void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
525
526/**
527 * @brief Returns the index of the current processor.
528 *
529 * An architecture specific method must be used to obtain the index of the
530 * current processor in the system.  The set of processor indices is the
531 * range of integers starting with zero up to the processor count minus one.
532 */
533uint32_t _CPU_SMP_Get_current_processor( void );
534
535/**
536 * @brief Sends an inter-processor interrupt to the specified target
537 * processor.
538 *
539 * This operation is undefined for target processor indices out of range.
540 *
541 * @param[in] target_processor_index The target processor index.
542 */
543void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
544
545/**
546 * @brief Broadcasts a processor event.
547 *
548 * Some architectures provide a low-level synchronization primitive for
549 * processors in a multi-processor environment.  Processors waiting for this
550 * event may go into a low-power state and stop generating system bus
551 * transactions.  This function must ensure that preceding store operations
552 * can be observed by other processors.
553 *
554 * @see _CPU_SMP_Processor_event_receive().
555 */
556void _CPU_SMP_Processor_event_broadcast( void );
557
558/**
559 * @brief Receives a processor event.
560 *
561 * This function will wait for the processor event and may wait forever if no
562 * such event arrives.
563 *
564 * @see _CPU_SMP_Processor_event_broadcast().
565 */
566static inline void _CPU_SMP_Processor_event_receive( void )
567{
568  __asm__ volatile ( "" : : : "memory" );
569}
570
571/**
572 * @brief Gets the is executing indicator of the thread context.
573 *
574 * @param[in] context The context.
575 */
576static inline bool _CPU_Context_Get_is_executing(
577  const Context_Control *context
578)
579{
580  return context->is_executing;
581}
582
583/**
584 * @brief Sets the is executing indicator of the thread context.
585 *
586 * @param[in] context The context.
587 * @param[in] is_executing The new value for the is executing indicator.
588 */
589static inline void _CPU_Context_Set_is_executing(
590  Context_Control *context,
591  bool is_executing
592)
593{
594  context->is_executing = is_executing;
595}
596#endif /* RTEMS_SMP */
597
598/** Type that can store a 32-bit integer or a pointer. */
599typedef uintptr_t CPU_Uint32ptr;
600
601#endif /* ASM */
602
603#ifdef __cplusplus
604}
605#endif
606
607#endif
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