[660db8c8] | 1 | /** |
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| 2 | * @file rtems/score/cpu.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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| 6 | * |
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| 7 | * Copyright (c) 2015 University of York. |
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| 8 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 9 | * |
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| 10 | * COPYRIGHT (c) 1989-1999. |
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| 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * |
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| 13 | * Redistribution and use in source and binary forms, with or without |
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| 14 | * modification, are permitted provided that the following conditions |
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| 15 | * are met: |
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| 16 | * 1. Redistributions of source code must retain the above copyright |
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| 17 | * notice, this list of conditions and the following disclaimer. |
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 19 | * notice, this list of conditions and the following disclaimer in the |
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| 20 | * documentation and/or other materials provided with the distribution. |
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| 21 | * |
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| 22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 32 | * SUCH DAMAGE. |
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| 33 | */ |
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| 34 | |
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| 35 | #ifndef _RISCV_CPU_H |
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| 36 | #define _RISCV_CPU_H |
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| 37 | |
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| 38 | #ifdef __cplusplus |
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| 39 | extern "C" { |
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| 40 | #endif |
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| 41 | |
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[5b88ec5] | 42 | #include <rtems/score/basedefs.h> |
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[660db8c8] | 43 | #include <rtems/score/riscv.h> /* pick up machine definitions */ |
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| 44 | #include <rtems/score/riscv-utility.h> |
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| 45 | #ifndef ASM |
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| 46 | #include <rtems/bspIo.h> |
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| 47 | #include <stdint.h> |
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| 48 | #include <stdio.h> /* for printk */ |
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| 49 | #endif |
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| 50 | |
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| 51 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 52 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 53 | #define CPU_ISR_PASSES_FRAME_POINTER 1 |
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| 54 | #define CPU_HARDWARE_FP FALSE |
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| 55 | #define CPU_SOFTWARE_FP FALSE |
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| 56 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 57 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 58 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 59 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 60 | #define CPU_STACK_GROWS_UP FALSE |
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| 61 | |
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| 62 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) |
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| 63 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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| 64 | #define CPU_BIG_ENDIAN FALSE |
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| 65 | #define CPU_LITTLE_ENDIAN TRUE |
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[11ff3a9] | 66 | #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 |
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[660db8c8] | 67 | |
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| 68 | /* |
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| 69 | * Processor defined structures required for cpukit/score. |
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| 70 | */ |
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| 71 | |
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| 72 | #ifndef ASM |
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| 73 | |
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| 74 | typedef struct { |
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[11ff3a9] | 75 | /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/ |
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| 76 | unsigned long x[32]; |
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[660db8c8] | 77 | |
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| 78 | /* Special purpose registers */ |
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[11ff3a9] | 79 | unsigned long mstatus; |
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| 80 | unsigned long mcause; |
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| 81 | unsigned long mepc; |
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[660db8c8] | 82 | #ifdef RTEMS_SMP |
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| 83 | volatile bool is_executing; |
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| 84 | #endif |
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| 85 | } Context_Control; |
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| 86 | |
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| 87 | #define _CPU_Context_Get_SP( _context ) \ |
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| 88 | (_context)->x[2] |
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| 89 | |
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| 90 | typedef struct { |
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| 91 | /** TODO FPU registers are listed here */ |
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| 92 | double some_float_register; |
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| 93 | } Context_Control_fp; |
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| 94 | |
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| 95 | typedef Context_Control CPU_Interrupt_frame; |
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| 96 | |
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| 97 | #define CPU_CONTEXT_FP_SIZE 0 |
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| 98 | Context_Control_fp _CPU_Null_fp_context; |
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| 99 | |
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[c8df844] | 100 | #define CPU_CACHE_LINE_BYTES 64 |
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| 101 | |
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[660db8c8] | 102 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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[11ff3a9] | 103 | #if __riscv_xlen == 32 |
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[660db8c8] | 104 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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[11ff3a9] | 105 | #else |
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| 106 | #define CPU_STACK_MINIMUM_SIZE 4096 * 2 |
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| 107 | #endif |
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[660db8c8] | 108 | #define CPU_ALIGNMENT 8 |
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| 109 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 110 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 111 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 112 | #define CPU_STACK_ALIGNMENT 8 |
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[c8df844] | 113 | |
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| 114 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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| 115 | |
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[660db8c8] | 116 | #define _CPU_Initialize_vectors() |
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| 117 | |
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| 118 | /* |
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| 119 | * Disable all interrupts for an RTEMS critical section. The previous |
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| 120 | * level is returned in _level. |
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| 121 | * |
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| 122 | */ |
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| 123 | |
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[11ff3a9] | 124 | static inline unsigned long riscv_interrupt_disable( void ) |
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[660db8c8] | 125 | { |
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[f35c3be9] | 126 | unsigned long status = read_csr(mstatus); |
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[660db8c8] | 127 | clear_csr(mstatus, MSTATUS_MIE); |
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| 128 | return status; |
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| 129 | } |
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| 130 | |
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[11ff3a9] | 131 | static inline void riscv_interrupt_enable(unsigned long level) |
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[660db8c8] | 132 | { |
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| 133 | write_csr(mstatus, level); |
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| 134 | } |
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| 135 | |
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| 136 | #define _CPU_ISR_Disable( _level ) \ |
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| 137 | _level = riscv_interrupt_disable() |
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| 138 | |
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| 139 | #define _CPU_ISR_Enable( _level ) \ |
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| 140 | riscv_interrupt_enable( _level ) |
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| 141 | |
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| 142 | #define _CPU_ISR_Flash( _level ) \ |
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| 143 | do{ \ |
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| 144 | _CPU_ISR_Enable( _level ); \ |
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| 145 | riscv_interrupt_disable(); \ |
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| 146 | } while(0) |
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| 147 | |
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[11ff3a9] | 148 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) |
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[660db8c8] | 149 | { |
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| 150 | return ( level & MSTATUS_MIE ) != 0; |
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| 151 | } |
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| 152 | |
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[7c3b0df1] | 153 | RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level ) |
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| 154 | { |
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| 155 | if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) { |
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| 156 | __asm__ volatile ( |
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| 157 | "csrrs zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE ) |
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| 158 | ); |
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| 159 | } else { |
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| 160 | __asm__ volatile ( |
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| 161 | "csrrc zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE ) |
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| 162 | ); |
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| 163 | } |
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| 164 | } |
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[660db8c8] | 165 | |
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[7c3b0df1] | 166 | uint32_t _CPU_ISR_Get_level( void ); |
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[660db8c8] | 167 | |
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| 168 | /* end of ISR handler macros */ |
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| 169 | |
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| 170 | /* Context handler macros */ |
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| 171 | #define RISCV_GCC_RED_ZONE_SIZE 128 |
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| 172 | |
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| 173 | void _CPU_Context_Initialize( |
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| 174 | Context_Control *context, |
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| 175 | void *stack_area_begin, |
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| 176 | size_t stack_area_size, |
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[11ff3a9] | 177 | unsigned long new_level, |
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[660db8c8] | 178 | void (*entry_point)( void ), |
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| 179 | bool is_fp, |
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| 180 | void *tls_area |
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| 181 | ); |
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| 182 | |
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| 183 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 184 | _CPU_Context_restore( (_the_context) ) |
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| 185 | |
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| 186 | |
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| 187 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 188 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 189 | |
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| 190 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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| 191 | { \ |
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| 192 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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| 193 | } |
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| 194 | |
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[c3897697] | 195 | extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; |
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[660db8c8] | 196 | |
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| 197 | /* end of Fatal Error manager macros */ |
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| 198 | |
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| 199 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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| 200 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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| 201 | |
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| 202 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 203 | |
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| 204 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 205 | { \ |
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| 206 | (_output) = 0; /* do something to prevent warnings */ \ |
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| 207 | } |
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| 208 | #endif |
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| 209 | |
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| 210 | /* end of Bitfield handler macros */ |
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| 211 | |
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| 212 | /* |
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| 213 | * This routine builds the mask which corresponds to the bit fields |
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| 214 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
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| 215 | * for that routine. |
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| 216 | * |
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| 217 | */ |
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| 218 | |
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| 219 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 220 | |
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| 221 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 222 | (1 << _bit_number) |
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| 223 | |
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| 224 | #endif |
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| 225 | |
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| 226 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 227 | |
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| 228 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 229 | (_priority) |
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| 230 | |
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| 231 | #endif |
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| 232 | |
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| 233 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 234 | |
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| 235 | #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE |
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| 236 | #define CPU_TIMESTAMP_USE_INT64 TRUE |
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| 237 | #define CPU_TIMESTAMP_USE_INT64_INLINE FALSE |
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| 238 | |
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| 239 | typedef struct { |
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| 240 | /* There is no CPU specific per-CPU state */ |
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| 241 | } CPU_Per_CPU_control; |
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| 242 | #endif /* ASM */ |
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| 243 | |
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[11ff3a9] | 244 | #if __riscv_xlen == 32 |
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[660db8c8] | 245 | #define CPU_SIZEOF_POINTER 4 |
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[11ff3a9] | 246 | |
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| 247 | /* 32-bit load/store instructions */ |
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| 248 | #define LREG lw |
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| 249 | #define SREG sw |
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| 250 | |
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[660db8c8] | 251 | #define CPU_EXCEPTION_FRAME_SIZE 128 |
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[11ff3a9] | 252 | #else /* xlen = 64 */ |
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| 253 | #define CPU_SIZEOF_POINTER 8 |
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| 254 | |
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| 255 | /* 64-bit load/store instructions */ |
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| 256 | #define LREG ld |
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| 257 | #define SREG sd |
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| 258 | |
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| 259 | #define CPU_EXCEPTION_FRAME_SIZE 256 |
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| 260 | #endif |
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| 261 | |
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[660db8c8] | 262 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 263 | |
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| 264 | #ifndef ASM |
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| 265 | typedef uint16_t Priority_bit_map_Word; |
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| 266 | |
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| 267 | typedef struct { |
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[11ff3a9] | 268 | unsigned long x[32];; |
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[660db8c8] | 269 | } CPU_Exception_frame; |
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| 270 | |
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| 271 | /** |
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| 272 | * @brief Prints the exception frame via printk(). |
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| 273 | * |
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| 274 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
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| 275 | */ |
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| 276 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 277 | |
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| 278 | |
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| 279 | /* end of Priority handler macros */ |
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| 280 | |
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| 281 | /* functions */ |
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| 282 | |
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| 283 | /* |
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| 284 | * _CPU_Initialize |
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| 285 | * |
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| 286 | * This routine performs CPU dependent initialization. |
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| 287 | * |
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| 288 | */ |
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| 289 | |
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| 290 | void _CPU_Initialize( |
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| 291 | void |
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| 292 | ); |
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| 293 | |
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| 294 | /* |
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| 295 | * _CPU_ISR_install_raw_handler |
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| 296 | * |
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| 297 | * This routine installs a "raw" interrupt handler directly into the |
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| 298 | * processor's vector table. |
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| 299 | * |
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| 300 | */ |
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| 301 | |
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| 302 | void _CPU_ISR_install_raw_handler( |
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| 303 | uint32_t vector, |
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| 304 | proc_ptr new_handler, |
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| 305 | proc_ptr *old_handler |
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| 306 | ); |
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| 307 | |
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| 308 | /* |
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| 309 | * _CPU_ISR_install_vector |
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| 310 | * |
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| 311 | * This routine installs an interrupt vector. |
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| 312 | * |
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| 313 | * NO_CPU Specific Information: |
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| 314 | * |
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| 315 | * XXX document implementation including references if appropriate |
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| 316 | */ |
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| 317 | |
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| 318 | void _CPU_ISR_install_vector( |
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[11ff3a9] | 319 | unsigned long vector, |
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[660db8c8] | 320 | proc_ptr new_handler, |
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| 321 | proc_ptr *old_handler |
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| 322 | ); |
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| 323 | |
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| 324 | /* |
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| 325 | * _CPU_Thread_Idle_body |
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| 326 | * |
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| 327 | * This routine is the CPU dependent IDLE thread body. |
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| 328 | * |
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| 329 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
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| 330 | * is TRUE. |
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| 331 | * |
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| 332 | */ |
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| 333 | |
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| 334 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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| 335 | |
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| 336 | /* |
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| 337 | * _CPU_Context_switch |
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| 338 | * |
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| 339 | * This routine switches from the run context to the heir context. |
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| 340 | * |
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| 341 | * RISCV Specific Information: |
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| 342 | * |
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| 343 | * Please see the comments in the .c file for a description of how |
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| 344 | * this function works. There are several things to be aware of. |
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| 345 | */ |
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| 346 | |
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| 347 | void _CPU_Context_switch( |
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| 348 | Context_Control *run, |
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| 349 | Context_Control *heir |
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| 350 | ); |
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| 351 | |
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| 352 | /* |
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| 353 | * _CPU_Context_restore |
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| 354 | * |
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| 355 | * This routine is generally used only to restart self in an |
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| 356 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 357 | * |
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| 358 | * NOTE: May be unnecessary to reload some registers. |
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| 359 | * |
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| 360 | */ |
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| 361 | |
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| 362 | void _CPU_Context_restore( |
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| 363 | Context_Control *new_context |
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[c3897697] | 364 | ) RTEMS_NO_RETURN; |
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[660db8c8] | 365 | |
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| 366 | /* |
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| 367 | * _CPU_Context_save_fp |
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| 368 | * |
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| 369 | * This routine saves the floating point context passed to it. |
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| 370 | * |
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| 371 | */ |
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| 372 | |
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| 373 | void _CPU_Context_save_fp( |
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| 374 | void **fp_context_ptr |
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| 375 | ); |
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| 376 | |
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| 377 | /* |
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| 378 | * _CPU_Context_restore_fp |
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| 379 | * |
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| 380 | * This routine restores the floating point context passed to it. |
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| 381 | * |
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| 382 | */ |
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| 383 | |
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| 384 | void _CPU_Context_restore_fp( |
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| 385 | void **fp_context_ptr |
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| 386 | ); |
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| 387 | |
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| 388 | /* The following routine swaps the endian format of an unsigned int. |
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| 389 | * It must be static because it is referenced indirectly. |
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| 390 | * |
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| 391 | * This version will work on any processor, but if there is a better |
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| 392 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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| 393 | * |
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| 394 | * swap least significant two bytes with 16-bit rotate |
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| 395 | * swap upper and lower 16-bits |
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| 396 | * swap most significant two bytes with 16-bit rotate |
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| 397 | * |
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| 398 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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| 399 | * a single instruction (e.g. i486). It is probably best to avoid |
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| 400 | * an "endian swapping control bit" in the CPU. One good reason is |
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| 401 | * that interrupts would probably have to be disabled to insure that |
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| 402 | * an interrupt does not try to access the same "chunk" with the wrong |
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| 403 | * endian. Another good reason is that on some CPUs, the endian bit |
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| 404 | * endianness for ALL fetches -- both code and data -- so the code |
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| 405 | * will be fetched incorrectly. |
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| 406 | * |
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| 407 | */ |
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| 408 | |
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[11ff3a9] | 409 | static inline uint32_t CPU_swap_u32( |
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| 410 | uint32_t value |
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[660db8c8] | 411 | ) |
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| 412 | { |
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| 413 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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| 414 | |
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| 415 | byte4 = (value >> 24) & 0xff; |
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| 416 | byte3 = (value >> 16) & 0xff; |
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| 417 | byte2 = (value >> 8) & 0xff; |
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| 418 | byte1 = value & 0xff; |
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| 419 | |
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| 420 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 421 | return ( swapped ); |
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| 422 | } |
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| 423 | |
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| 424 | #define CPU_swap_u16( value ) \ |
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| 425 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 426 | |
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| 427 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
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| 428 | { |
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| 429 | /* TODO */ |
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| 430 | } |
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| 431 | |
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| 432 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
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| 433 | { |
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| 434 | while (1) { |
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| 435 | /* TODO */ |
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| 436 | } |
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| 437 | } |
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| 438 | |
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| 439 | typedef uint32_t CPU_Counter_ticks; |
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| 440 | |
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[65f868c] | 441 | uint32_t _CPU_Counter_frequency( void ); |
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| 442 | |
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[660db8c8] | 443 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 444 | |
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| 445 | #ifdef RTEMS_SMP |
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[2086948a] | 446 | |
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[660db8c8] | 447 | uint32_t _CPU_SMP_Initialize( void ); |
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| 448 | |
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| 449 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 450 | |
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| 451 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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| 452 | |
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[2086948a] | 453 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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| 454 | |
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| 455 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
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| 456 | { |
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| 457 | unsigned long mhartid; |
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| 458 | |
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| 459 | __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) ); |
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| 460 | |
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| 461 | return (uint32_t) mhartid; |
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| 462 | } |
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[660db8c8] | 463 | |
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| 464 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 465 | |
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[2086948a] | 466 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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| 467 | { |
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| 468 | __asm__ volatile ( "" : : : "memory" ); |
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| 469 | } |
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[660db8c8] | 470 | |
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| 471 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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| 472 | { |
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| 473 | __asm__ volatile ( "" : : : "memory" ); |
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| 474 | } |
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| 475 | |
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| 476 | static inline bool _CPU_Context_Get_is_executing( |
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| 477 | const Context_Control *context |
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| 478 | ) |
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| 479 | { |
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| 480 | return context->is_executing; |
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| 481 | } |
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| 482 | |
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| 483 | static inline void _CPU_Context_Set_is_executing( |
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| 484 | Context_Control *context, |
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| 485 | bool is_executing |
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| 486 | ) |
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| 487 | { |
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| 488 | context->is_executing = is_executing; |
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| 489 | } |
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[2086948a] | 490 | |
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[660db8c8] | 491 | #endif /* RTEMS_SMP */ |
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| 492 | |
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[5b88ec5] | 493 | /** Type that can store a 32-bit integer or a pointer. */ |
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| 494 | typedef uintptr_t CPU_Uint32ptr; |
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| 495 | |
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[660db8c8] | 496 | #endif /* ASM */ |
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| 497 | |
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| 498 | #ifdef __cplusplus |
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| 499 | } |
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| 500 | #endif |
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| 501 | |
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| 502 | #endif |
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