1 | /* |
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2 | * Copyright (c) 2018 embedded brains GmbH |
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3 | * |
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4 | * Copyright (c) 2015 University of York. |
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5 | * Hesham ALmatary <hesham@alumni.york.ac.uk> |
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6 | * |
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7 | * COPYRIGHT (c) 1989-1999. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * Redistribution and use in source and binary forms, with or without |
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11 | * modification, are permitted provided that the following conditions |
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12 | * are met: |
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13 | * 1. Redistributions of source code must retain the above copyright |
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14 | * notice, this list of conditions and the following disclaimer. |
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15 | * 2. Redistributions in binary form must reproduce the above copyright |
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16 | * notice, this list of conditions and the following disclaimer in the |
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17 | * documentation and/or other materials provided with the distribution. |
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18 | * |
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19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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29 | * SUCH DAMAGE. |
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30 | */ |
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31 | |
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32 | #include <rtems/score/cpuimpl.h> |
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33 | #include <rtems/score/isr.h> |
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34 | #include <rtems/score/riscv-utility.h> |
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35 | |
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36 | #define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \ |
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37 | RTEMS_STATIC_ASSERT( \ |
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38 | offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \ |
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39 | riscv_context_offset_ ## field \ |
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40 | ) |
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41 | |
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42 | RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE ); |
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43 | #ifdef RTEMS_SMP |
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44 | RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING ); |
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45 | #endif |
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46 | RISCV_ASSERT_CONTEXT_OFFSET( ra, RA ); |
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47 | RISCV_ASSERT_CONTEXT_OFFSET( sp, SP ); |
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48 | RISCV_ASSERT_CONTEXT_OFFSET( tp, TP ); |
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49 | RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 ); |
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50 | RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 ); |
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51 | RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 ); |
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52 | RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 ); |
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53 | RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 ); |
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54 | RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 ); |
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55 | RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 ); |
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56 | RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 ); |
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57 | RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 ); |
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58 | RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 ); |
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59 | RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 ); |
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60 | RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 ); |
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61 | |
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62 | #define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \ |
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63 | RTEMS_STATIC_ASSERT( \ |
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64 | offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \ |
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65 | riscv_interrupt_frame_offset_ ## field \ |
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66 | ) |
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67 | |
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68 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS ); |
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69 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC ); |
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70 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 ); |
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71 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 ); |
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72 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 ); |
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73 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA ); |
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74 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 ); |
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75 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 ); |
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76 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 ); |
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77 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 ); |
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78 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 ); |
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79 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 ); |
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80 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 ); |
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81 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 ); |
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82 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 ); |
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83 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 ); |
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84 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 ); |
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85 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 ); |
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86 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 ); |
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87 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 ); |
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88 | |
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89 | RTEMS_STATIC_ASSERT( |
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90 | sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0, |
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91 | riscv_interrupt_frame_size |
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92 | ); |
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93 | |
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94 | /* bsp_start_vector_table_begin is the start address of the vector table |
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95 | * containing addresses to ISR Handlers. It's defined at the BSP linkcmds |
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96 | * and may differ from one BSP to another. |
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97 | */ |
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98 | extern char bsp_start_vector_table_begin[]; |
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99 | |
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100 | void init(void); |
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101 | void fini(void); |
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102 | |
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103 | void _init() |
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104 | { |
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105 | } |
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106 | |
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107 | void _fini() |
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108 | { |
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109 | } |
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110 | |
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111 | /** |
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112 | * @brief Performs processor dependent initialization. |
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113 | */ |
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114 | void _CPU_Initialize(void) |
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115 | { |
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116 | /* Do nothing */ |
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117 | } |
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118 | |
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119 | uint32_t _CPU_ISR_Get_level( void ) |
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120 | { |
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121 | if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) { |
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122 | return 0; |
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123 | } |
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124 | |
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125 | return 1; |
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126 | } |
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127 | |
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128 | void _CPU_ISR_install_raw_handler( |
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129 | uint32_t vector, |
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130 | proc_ptr new_handler, |
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131 | proc_ptr *old_handler |
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132 | ) |
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133 | { |
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134 | /* Do nothing */ |
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135 | } |
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136 | |
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137 | void _CPU_ISR_install_vector( |
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138 | unsigned long vector, |
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139 | proc_ptr new_handler, |
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140 | proc_ptr *old_handler |
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141 | ) |
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142 | { |
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143 | proc_ptr *table = |
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144 | (proc_ptr *) bsp_start_vector_table_begin; |
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145 | proc_ptr current_handler; |
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146 | |
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147 | ISR_Level level; |
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148 | |
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149 | _ISR_Local_disable( level ); |
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150 | |
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151 | current_handler = table [vector]; |
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152 | |
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153 | /* The current handler is now the old one */ |
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154 | if (old_handler != NULL) { |
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155 | *old_handler = (proc_ptr) current_handler; |
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156 | } |
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157 | |
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158 | /* Write only if necessary to avoid writes to a maybe read-only |
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159 | * memory */ |
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160 | if (current_handler != new_handler) { |
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161 | table [vector] = new_handler; |
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162 | } |
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163 | |
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164 | _ISR_Local_enable( level ); |
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165 | |
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166 | } |
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167 | |
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168 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
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169 | { |
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170 | do { |
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171 | } while (1); |
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172 | |
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173 | return NULL; |
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174 | } |
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