source: rtems/cpukit/score/cpu/riscv/cpu.c @ e43994d

5
Last change on this file since e43994d was e43994d, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 27, 2018 at 8:05:50 AM

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

  • Property mode set to 100644
File size: 5.1 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-1999.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <rtems/score/cpuimpl.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/riscv-utility.h>
35
36#define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \
37  RTEMS_STATIC_ASSERT( \
38    offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \
39    riscv_context_offset_ ## field \
40  )
41
42RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE );
43#ifdef RTEMS_SMP
44RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING );
45#endif
46RISCV_ASSERT_CONTEXT_OFFSET( ra, RA );
47RISCV_ASSERT_CONTEXT_OFFSET( sp, SP );
48RISCV_ASSERT_CONTEXT_OFFSET( tp, TP );
49RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 );
50RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 );
51RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 );
52RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 );
53RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 );
54RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 );
55RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 );
56RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 );
57RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 );
58RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 );
59RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 );
60RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 );
61
62#define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \
63  RTEMS_STATIC_ASSERT( \
64    offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \
65    riscv_interrupt_frame_offset_ ## field \
66  )
67
68RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS );
69RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC );
70RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 );
71RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 );
72RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 );
73RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA );
74RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 );
75RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 );
76RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 );
77RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 );
78RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 );
79RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 );
80RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 );
81RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 );
82RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 );
83RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 );
84RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 );
85RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 );
86RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 );
87RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 );
88
89RTEMS_STATIC_ASSERT(
90  sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0,
91  riscv_interrupt_frame_size
92);
93
94/* bsp_start_vector_table_begin is the start address of the vector table
95 * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
96 * and may differ from one BSP to another.
97 */
98extern char bsp_start_vector_table_begin[];
99
100void init(void);
101void fini(void);
102
103void _init()
104{
105}
106
107void _fini()
108{
109}
110
111/**
112 * @brief Performs processor dependent initialization.
113 */
114void _CPU_Initialize(void)
115{
116  /* Do nothing */
117}
118
119uint32_t _CPU_ISR_Get_level( void )
120{
121  if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) {
122    return 0;
123  }
124
125  return 1;
126}
127
128void _CPU_ISR_install_raw_handler(
129  uint32_t   vector,
130  proc_ptr    new_handler,
131  proc_ptr   *old_handler
132)
133{
134  /* Do nothing */
135}
136
137void _CPU_ISR_install_vector(
138  unsigned long    vector,
139  proc_ptr    new_handler,
140  proc_ptr   *old_handler
141)
142{
143  proc_ptr *table =
144    (proc_ptr *) bsp_start_vector_table_begin;
145  proc_ptr current_handler;
146
147  ISR_Level level;
148
149  _ISR_Local_disable( level );
150
151  current_handler = table [vector];
152
153  /* The current handler is now the old one */
154  if (old_handler != NULL) {
155    *old_handler = (proc_ptr) current_handler;
156  }
157
158  /* Write only if necessary to avoid writes to a maybe read-only
159   * memory */
160  if (current_handler != new_handler) {
161    table [vector] = new_handler;
162  }
163
164  _ISR_Local_enable( level );
165
166}
167
168void *_CPU_Thread_Idle_body( uintptr_t ignored )
169{
170  do {
171  } while (1);
172
173  return NULL;
174}
Note: See TracBrowser for help on using the repository browser.