source: rtems/cpukit/score/cpu/riscv/cpu.c @ 9704d86f

5
Last change on this file since 9704d86f was 9704d86f, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 26, 2018 at 6:53:28 AM

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-1999.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <rtems/score/cpuimpl.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/riscv-utility.h>
35
36#define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \
37  RTEMS_STATIC_ASSERT( \
38    offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \
39    riscv_context_offset_ ## field \
40  )
41
42RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE );
43
44/* bsp_start_vector_table_begin is the start address of the vector table
45 * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
46 * and may differ from one BSP to another.
47 */
48extern char bsp_start_vector_table_begin[];
49
50void init(void);
51void fini(void);
52
53void _init()
54{
55}
56
57void _fini()
58{
59}
60
61/**
62 * @brief Performs processor dependent initialization.
63 */
64void _CPU_Initialize(void)
65{
66  /* Do nothing */
67}
68
69uint32_t _CPU_ISR_Get_level( void )
70{
71  if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) {
72    return 0;
73  }
74
75  return 1;
76}
77
78void _CPU_ISR_install_raw_handler(
79  uint32_t   vector,
80  proc_ptr    new_handler,
81  proc_ptr   *old_handler
82)
83{
84  /* Do nothing */
85}
86
87void _CPU_ISR_install_vector(
88  unsigned long    vector,
89  proc_ptr    new_handler,
90  proc_ptr   *old_handler
91)
92{
93  proc_ptr *table =
94    (proc_ptr *) bsp_start_vector_table_begin;
95  proc_ptr current_handler;
96
97  ISR_Level level;
98
99  _ISR_Local_disable( level );
100
101  current_handler = table [vector];
102
103  /* The current handler is now the old one */
104  if (old_handler != NULL) {
105    *old_handler = (proc_ptr) current_handler;
106  }
107
108  /* Write only if necessary to avoid writes to a maybe read-only
109   * memory */
110  if (current_handler != new_handler) {
111    table [vector] = new_handler;
112  }
113
114  _ISR_Local_enable( level );
115
116}
117
118void *_CPU_Thread_Idle_body( uintptr_t ignored )
119{
120  do {
121  } while (1);
122
123  return NULL;
124}
Note: See TracBrowser for help on using the repository browser.