source: rtems/cpukit/score/cpu/riscv/cpu.c @ 7c3b0df1

5
Last change on this file since 7c3b0df1 was 7c3b0df1, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 22, 2018 at 11:30:49 AM

riscv: Implement ISR set/get level

Fix prototypes.

Update #3433.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * RISC-V CPU Dependent Source
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-1999.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/wkspace.h>
35#include <rtems/score/cpu.h>
36
37/* bsp_start_vector_table_begin is the start address of the vector table
38 * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
39 * and may differ from one BSP to another.
40 */
41extern char bsp_start_vector_table_begin[];
42
43void init(void);
44void fini(void);
45
46void _init()
47{
48}
49
50void _fini()
51{
52}
53
54/**
55 * @brief Performs processor dependent initialization.
56 */
57void _CPU_Initialize(void)
58{
59  /* Do nothing */
60}
61
62uint32_t _CPU_ISR_Get_level( void )
63{
64  if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) {
65    return 0;
66  }
67
68  return 1;
69}
70
71void _CPU_ISR_install_raw_handler(
72  uint32_t   vector,
73  proc_ptr    new_handler,
74  proc_ptr   *old_handler
75)
76{
77  /* Do nothing */
78}
79
80void _CPU_ISR_install_vector(
81  unsigned long    vector,
82  proc_ptr    new_handler,
83  proc_ptr   *old_handler
84)
85{
86  proc_ptr *table =
87    (proc_ptr *) bsp_start_vector_table_begin;
88  proc_ptr current_handler;
89
90  ISR_Level level;
91
92  _ISR_Local_disable( level );
93
94  current_handler = table [vector];
95
96  /* The current handler is now the old one */
97  if (old_handler != NULL) {
98    *old_handler = (proc_ptr) current_handler;
99  }
100
101  /* Write only if necessary to avoid writes to a maybe read-only
102   * memory */
103  if (current_handler != new_handler) {
104    table [vector] = new_handler;
105  }
106
107  _ISR_Local_enable( level );
108
109}
110
111void *_CPU_Thread_Idle_body( uintptr_t ignored )
112{
113  do {
114  } while (1);
115
116  return NULL;
117}
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