source: rtems/cpukit/score/cpu/riscv/cpu.c @ 511dc4b

5
Last change on this file since 511dc4b was 511dc4b, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 19, 2018 at 7:09:51 AM

Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  • interrupts are disabled during the sequential system initialization, and
  • the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  • Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases.
  • Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  • Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

m68k:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

powerpc:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.
  • Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA).

sparc:

  • Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM.

Update #3459.

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 * RISC-V CPU Dependent Source
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-1999.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/wkspace.h>
35#include <rtems/score/cpu.h>
36
37/* bsp_start_vector_table_begin is the start address of the vector table
38 * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
39 * and may differ from one BSP to another.
40 */
41extern char bsp_start_vector_table_begin[];
42
43void init(void);
44void fini(void);
45
46void _init()
47{
48}
49
50void _fini()
51{
52}
53
54/**
55 * @brief Performs processor dependent initialization.
56 */
57void _CPU_Initialize(void)
58{
59  /* Do nothing */
60}
61
62void _CPU_ISR_Set_level(unsigned long level)
63{
64  /* Do nothing */
65}
66
67unsigned long  _CPU_ISR_Get_level( void )
68{
69  /* Do nothing */
70  return 0;
71}
72
73void _CPU_ISR_install_raw_handler(
74  uint32_t   vector,
75  proc_ptr    new_handler,
76  proc_ptr   *old_handler
77)
78{
79  /* Do nothing */
80}
81
82void _CPU_ISR_install_vector(
83  unsigned long    vector,
84  proc_ptr    new_handler,
85  proc_ptr   *old_handler
86)
87{
88  proc_ptr *table =
89    (proc_ptr *) bsp_start_vector_table_begin;
90  proc_ptr current_handler;
91
92  ISR_Level level;
93
94  _ISR_Local_disable( level );
95
96  current_handler = table [vector];
97
98  /* The current handler is now the old one */
99  if (old_handler != NULL) {
100    *old_handler = (proc_ptr) current_handler;
101  }
102
103  /* Write only if necessary to avoid writes to a maybe read-only
104   * memory */
105  if (current_handler != new_handler) {
106    table [vector] = new_handler;
107  }
108
109  _ISR_Local_enable( level );
110
111}
112
113void *_CPU_Thread_Idle_body( uintptr_t ignored )
114{
115  do {
116  } while (1);
117
118  return NULL;
119}
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