source: rtems/cpukit/score/cpu/riscv/cpu.c @ 11ff3a9

Last change on this file since 11ff3a9 was 11ff3a9, checked in by Hesham Almatary <heshamelmatary@…>, on Oct 27, 2017 at 4:18:40 AM

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 * RISC-V CPU Dependent Source
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-1999.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/wkspace.h>
35#include <rtems/score/cpu.h>
36
37/* bsp_start_vector_table_begin is the start address of the vector table
38 * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
39 * and may differ from one BSP to another.
40 */
41extern char bsp_start_vector_table_begin[];
42
43void init(void);
44void fini(void);
45
46void _init()
47{
48}
49
50void _fini()
51{
52}
53
54/**
55 * @brief Performs processor dependent initialization.
56 */
57void _CPU_Initialize(void)
58{
59  /* Do nothing */
60}
61
62void _CPU_ISR_Set_level(unsigned long level)
63{
64  /* Do nothing */
65}
66
67unsigned long  _CPU_ISR_Get_level( void )
68{
69  /* Do nothing */
70  return 0;
71}
72
73void _CPU_ISR_install_raw_handler(
74  uint32_t   vector,
75  proc_ptr    new_handler,
76  proc_ptr   *old_handler
77)
78{
79  /* Do nothing */
80}
81
82void _CPU_ISR_install_vector(
83  unsigned long    vector,
84  proc_ptr    new_handler,
85  proc_ptr   *old_handler
86)
87{
88  proc_ptr *table =
89    (proc_ptr *) bsp_start_vector_table_begin;
90  proc_ptr current_handler;
91
92  ISR_Level level;
93
94  _ISR_Local_disable( level );
95
96  current_handler = table [vector];
97
98  /* The current handler is now the old one */
99  if (old_handler != NULL) {
100    *old_handler = (proc_ptr) current_handler;
101  }
102
103  /* Write only if necessary to avoid writes to a maybe read-only
104   * memory */
105  if (current_handler != new_handler) {
106    table [vector] = new_handler;
107  }
108
109  _ISR_Local_enable( level );
110
111}
112
113void _CPU_Install_interrupt_stack( void )
114{
115  /* Do nothing */
116}
117
118void *_CPU_Thread_Idle_body( uintptr_t ignored )
119{
120  do {
121  } while (1);
122
123  return NULL;
124}
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