[660db8c8] | 1 | /* |
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[9704d86f] | 2 | * Copyright (c) 2018 embedded brains GmbH |
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[660db8c8] | 3 | * |
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| 4 | * Copyright (c) 2015 University of York. |
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| 5 | * Hesham ALmatary <hesham@alumni.york.ac.uk> |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1999. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * Redistribution and use in source and binary forms, with or without |
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| 11 | * modification, are permitted provided that the following conditions |
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| 12 | * are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 16 | * notice, this list of conditions and the following disclaimer in the |
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| 17 | * documentation and/or other materials provided with the distribution. |
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| 18 | * |
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 29 | * SUCH DAMAGE. |
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| 30 | */ |
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| 31 | |
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[9704d86f] | 32 | #include <rtems/score/cpuimpl.h> |
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[3be4478f] | 33 | #include <rtems/score/isr.h> |
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| 34 | #include <rtems/score/riscv-utility.h> |
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[660db8c8] | 35 | |
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[9704d86f] | 36 | #define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \ |
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| 37 | RTEMS_STATIC_ASSERT( \ |
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| 38 | offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \ |
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| 39 | riscv_context_offset_ ## field \ |
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| 40 | ) |
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| 41 | |
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| 42 | RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE ); |
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[e43994d] | 43 | #ifdef RTEMS_SMP |
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| 44 | RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING ); |
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| 45 | #endif |
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| 46 | RISCV_ASSERT_CONTEXT_OFFSET( ra, RA ); |
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| 47 | RISCV_ASSERT_CONTEXT_OFFSET( sp, SP ); |
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| 48 | RISCV_ASSERT_CONTEXT_OFFSET( tp, TP ); |
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| 49 | RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 ); |
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| 50 | RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 ); |
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| 51 | RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 ); |
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| 52 | RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 ); |
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| 53 | RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 ); |
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| 54 | RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 ); |
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| 55 | RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 ); |
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| 56 | RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 ); |
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| 57 | RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 ); |
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| 58 | RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 ); |
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| 59 | RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 ); |
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| 60 | RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 ); |
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| 61 | |
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[52352387] | 62 | #if __riscv_flen > 0 |
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| 63 | |
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| 64 | RISCV_ASSERT_CONTEXT_OFFSET( fcsr, FCSR ); |
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| 65 | RISCV_ASSERT_CONTEXT_OFFSET( fs0, FS0 ); |
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| 66 | RISCV_ASSERT_CONTEXT_OFFSET( fs1, FS1 ); |
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| 67 | RISCV_ASSERT_CONTEXT_OFFSET( fs2, FS2 ); |
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| 68 | RISCV_ASSERT_CONTEXT_OFFSET( fs3, FS3 ); |
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| 69 | RISCV_ASSERT_CONTEXT_OFFSET( fs4, FS4 ); |
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| 70 | RISCV_ASSERT_CONTEXT_OFFSET( fs5, FS5 ); |
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| 71 | RISCV_ASSERT_CONTEXT_OFFSET( fs6, FS6 ); |
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| 72 | RISCV_ASSERT_CONTEXT_OFFSET( fs7, FS7 ); |
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| 73 | RISCV_ASSERT_CONTEXT_OFFSET( fs8, FS8 ); |
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| 74 | RISCV_ASSERT_CONTEXT_OFFSET( fs9, FS9 ); |
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| 75 | RISCV_ASSERT_CONTEXT_OFFSET( fs10, FS10 ); |
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| 76 | RISCV_ASSERT_CONTEXT_OFFSET( fs11, FS11 ); |
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| 77 | |
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| 78 | #endif /* __riscv_flen */ |
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| 79 | |
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[e43994d] | 80 | #define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \ |
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| 81 | RTEMS_STATIC_ASSERT( \ |
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| 82 | offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \ |
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| 83 | riscv_interrupt_frame_offset_ ## field \ |
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| 84 | ) |
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| 85 | |
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| 86 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS ); |
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| 87 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC ); |
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| 88 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 ); |
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| 89 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 ); |
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| 90 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 ); |
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| 91 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA ); |
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| 92 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 ); |
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| 93 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 ); |
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| 94 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 ); |
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| 95 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 ); |
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| 96 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 ); |
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| 97 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 ); |
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| 98 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 ); |
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| 99 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 ); |
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| 100 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 ); |
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| 101 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 ); |
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| 102 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 ); |
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| 103 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 ); |
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| 104 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 ); |
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| 105 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 ); |
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| 106 | |
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[52352387] | 107 | #if __riscv_flen > 0 |
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| 108 | |
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| 109 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fcsr, FCSR ); |
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| 110 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft0, FT0 ); |
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| 111 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft1, FT1 ); |
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| 112 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft2, FT2 ); |
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| 113 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft3, FT3 ); |
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| 114 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft4, FT4 ); |
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| 115 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft5, FT5 ); |
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| 116 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft6, FT6 ); |
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| 117 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft7, FT7 ); |
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| 118 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft8, FT8 ); |
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| 119 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft9, FT9 ); |
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| 120 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft10, FT10 ); |
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| 121 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft11, FT11 ); |
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| 122 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa0, FA0 ); |
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| 123 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa1, FA1 ); |
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| 124 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa2, FA2 ); |
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| 125 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa3, FA3 ); |
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| 126 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa4, FA4 ); |
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| 127 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa5, FA5 ); |
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| 128 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa6, FA6 ); |
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| 129 | RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa7, FA7 ); |
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| 130 | |
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| 131 | #endif /* __riscv_flen */ |
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| 132 | |
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[5694b0c] | 133 | #define RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( field, off ) \ |
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| 134 | RTEMS_STATIC_ASSERT( \ |
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| 135 | offsetof( CPU_Exception_frame, field) == RISCV_EXCEPTION_FRAME_ ## off, \ |
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| 136 | riscv_context_offset_ ## field \ |
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| 137 | ) |
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| 138 | |
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| 139 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( mcause, MCAUSE ); |
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| 140 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( sp, SP ); |
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| 141 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( gp, GP ); |
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| 142 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( tp, TP ); |
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| 143 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s2, S2 ); |
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| 144 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s3, S3 ); |
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| 145 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s4, S4 ); |
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| 146 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s5, S5 ); |
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| 147 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s6, S6 ); |
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| 148 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s7, S7 ); |
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| 149 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s8, S8 ); |
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| 150 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s9, S9 ); |
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| 151 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s10, S10 ); |
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| 152 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s11, S11 ); |
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| 153 | |
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| 154 | #if __riscv_flen > 0 |
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| 155 | |
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| 156 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs0, FS0 ); |
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| 157 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs1, FS1 ); |
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| 158 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs2, FS2 ); |
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| 159 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs3, FS3 ); |
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| 160 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs4, FS4 ); |
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| 161 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs5, FS5 ); |
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| 162 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs6, FS6 ); |
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| 163 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs7, FS7 ); |
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| 164 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs8, FS8 ); |
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| 165 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs9, FS9 ); |
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| 166 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs10, FS10 ); |
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| 167 | RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs11, FS11 ); |
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| 168 | |
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| 169 | #endif /* __riscv_flen */ |
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| 170 | |
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[e43994d] | 171 | RTEMS_STATIC_ASSERT( |
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| 172 | sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0, |
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| 173 | riscv_interrupt_frame_size |
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| 174 | ); |
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[9704d86f] | 175 | |
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[995e91e8] | 176 | void _init(void); |
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[660db8c8] | 177 | |
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[995e91e8] | 178 | void _fini(void); |
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| 179 | |
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| 180 | void _init(void) |
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[660db8c8] | 181 | { |
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| 182 | } |
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| 183 | |
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[995e91e8] | 184 | void _fini(void) |
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[660db8c8] | 185 | { |
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| 186 | } |
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| 187 | |
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| 188 | /** |
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| 189 | * @brief Performs processor dependent initialization. |
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| 190 | */ |
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| 191 | void _CPU_Initialize(void) |
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| 192 | { |
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| 193 | /* Do nothing */ |
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| 194 | } |
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| 195 | |
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[7c3b0df1] | 196 | uint32_t _CPU_ISR_Get_level( void ) |
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[660db8c8] | 197 | { |
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[7c3b0df1] | 198 | if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) { |
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| 199 | return 0; |
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| 200 | } |
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[660db8c8] | 201 | |
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[7c3b0df1] | 202 | return 1; |
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[660db8c8] | 203 | } |
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| 204 | |
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| 205 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
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| 206 | { |
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| 207 | do { |
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| 208 | } while (1); |
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| 209 | |
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| 210 | return NULL; |
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| 211 | } |
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