source: rtems/cpukit/score/cpu/powerpc/rtems/score/ppc.h @ 71f16a4

4.104.114.84.95
Last change on this file since 71f16a4 was 71f16a4, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 19, 1999 at 10:07:00 PM

Support for MPC505 from Sergei Organov <osv@…>. His patch was
against 3.6.0 so was painful to merge. It should be OK but there
is no guarantee and there are no BSPs in the tree to exercise it.

  • Property mode set to 100644
File size: 18.5 KB
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1/*  ppc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *
12 *  To anyone who acknowledges that this file is provided "AS IS"
13 *  without any express or implied warranty:
14 *      permission to use, copy, modify, and distribute this file
15 *      for any purpose is hereby granted without fee, provided that
16 *      the above copyright notice and this notice appears in all
17 *      copies, and that the name of i-cubed limited not be used in
18 *      advertising or publicity pertaining to distribution of the
19 *      software without specific, written prior permission.
20 *      i-cubed limited makes no representations about the suitability
21 *      of this software for any purpose.
22 *
23 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
24 *
25 *  COPYRIGHT (c) 1989-1997.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may in
29 *  the file LICENSE in this distribution or at
30 *  http://www.OARcorp.com/rtems/license.html.
31 *
32 *
33 * Note:
34 *      This file is included by both C and assembler code ( -DASM )
35 *
36 *  $Id$
37 */
38
39
40#ifndef _INCLUDE_PPC_h
41#define _INCLUDE_PPC_h
42
43#ifdef __cplusplus
44extern "C" {
45#endif
46
47/*
48 *  Define the name of the CPU family.
49 */
50
51#define CPU_NAME "PowerPC"
52
53/*
54 *  This file contains the information required to build
55 *  RTEMS for a particular member of the PowerPC family.  It does
56 *  this by setting variables to indicate which implementation
57 *  dependent features are present in a particular member
58 *  of the family.
59 *
60 *  The following architectural feature definitions are defaulted
61 *  unless specifically set by the model definition:
62 *
63 *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
64 *    + PPC_INTERRUPT_MAX        - 16
65 *    + PPC_CACHE_ALIGNMENT      - 32
66 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
67 *    + PPC_HAS_EXCEPTION_PREFIX - 1
68 *    + PPC_HAS_FPU              - 1
69 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
70 *                               - 0 otherwise
71 *    + PPC_USE_MULTIPLE         - 0
72 */
73 
74/*
75 *  Define the debugging assistance models found in the PPC family.
76 *
77 *  Standard:         single step and branch trace
78 *  Single Step Only: single step only
79 *  IBM 4xx:          debug exception
80 */
81
82#define PPC_DEBUG_MODEL_STANDARD         1
83#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
84#define PPC_DEBUG_MODEL_IBM4xx           3
85
86/*
87 *  Define the low power mode models
88 *
89 *  Standard:   as defined for 603e
90 *  Nap Mode:   nap mode only (604)
91 *  XXX 403GB, 603, 603e, 604, 821
92 */
93
94#define PPC_LOW_POWER_MODE_NONE      0
95#define PPC_LOW_POWER_MODE_STANDARD  1
96
97#if defined(ppc403)
98/*
99 *  IBM 403
100 *
101 *  Developed for 403GA.  Book checked for 403GB.
102 *
103 *  Does not have user mode.
104 */
105 
106#define CPU_MODEL_NAME "PowerPC 403"
107#define PPC_ALIGNMENT           4 
108#define PPC_CACHE_ALIGNMENT     16
109#define PPC_HAS_RFCI            1
110#define PPC_HAS_FPU             0
111#define PPC_USE_MULTIPLE        1
112#define PPC_I_CACHE             2048
113#define PPC_D_CACHE             1024
114
115#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
116#define PPC_HAS_EXCEPTION_PREFIX 0
117#define PPC_HAS_EVPR             1
118
119
120#elif defined(mpc505) || defined(mpc509)
121/*
122 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
123 *  3.6.0 long after 4.0 was released.   This is just an attempt
124 *  to get the setting correct.
125 */
126
127#define CPU_MODEL_NAME  "PowerPC 505/509"
128
129#define PPC_ALIGNMENT           4
130#define PPC_CACHE_ALIGNMENT     16
131#define PPC_I_CACHE             4096
132#define PPC_I_CACHE             0
133
134
135#elif defined(ppc601)
136
137/*
138 *  Submitted with original port -- book checked only.
139 */
140 
141#define CPU_MODEL_NAME  "PowerPC 601"
142
143#define PPC_ALIGNMENT           8
144#define PPC_USE_MULTIPLE        1
145#define PPC_I_CACHE             0
146#define PPC_D_CACHE             32768
147
148#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
149
150#elif defined(ppc602)
151/*
152 *  Submitted with original port -- book checked only.
153 */
154 
155#define CPU_MODEL_NAME  "PowerPC 602"
156
157#define PPC_ALIGNMENT           4
158#define PPC_HAS_DOUBLE          0
159#define PPC_I_CACHE             4096
160#define PPC_D_CACHE             4096
161
162#elif defined(ppc603)
163/*
164 *  Submitted with original port -- book checked only.
165 */
166 
167#define CPU_MODEL_NAME  "PowerPC 603"
168
169#define PPC_ALIGNMENT           8
170#define PPC_I_CACHE             8192
171#define PPC_D_CACHE             8192
172
173#elif defined(ppc603e)
174 
175#define CPU_MODEL_NAME  "PowerPC 603e"
176/*
177 *  Submitted with original port.
178 *
179 *  Known to work on real hardware.
180 */
181
182#define PPC_ALIGNMENT           8
183#define PPC_I_CACHE             16384
184#define PPC_D_CACHE             16384
185
186#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
187
188#elif defined(ppc604)
189/*
190 *  Submitted with original port -- book checked only.
191 */
192 
193#define CPU_MODEL_NAME  "PowerPC 604"
194
195#define PPC_ALIGNMENT           8
196#define PPC_I_CACHE             16384
197#define PPC_D_CACHE             16384
198 
199#elif defined(mpc860)
200/*
201 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
202 */ 
203#define CPU_MODEL_NAME  "PowerPC MPC860"
204
205#define PPC_ALIGNMENT           4
206#define PPC_I_CACHE             4096
207#define PPC_D_CACHE             4096
208#define PPC_CACHE_ALIGNMENT     16
209#define PPC_INTERRUPT_MAX       71
210#define PPC_HAS_FPU             0
211#define PPC_HAS_DOUBLE          0
212#define PPC_USE_MULTIPLE        1
213#define PPC_USE_SPRG            1
214
215#define PPC_MSR_0               0x00009000
216#define PPC_MSR_1               0x00001000
217#define PPC_MSR_2               0x00001000
218#define PPC_MSR_3               0x00000000
219
220#elif defined(mpc821)
221/*
222 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
223 */ 
224#define CPU_MODEL_NAME  "PowerPC MPC821"
225
226#define PPC_ALIGNMENT           4
227#define PPC_I_CACHE             4096
228#define PPC_D_CACHE             4096
229#define PPC_CACHE_ALIGNMENT     16
230#define PPC_INTERRUPT_MAX       71
231#define PPC_HAS_FPU             0
232#define PPC_HAS_DOUBLE          0
233
234#define PPC_MSR_0               0x00009000
235#define PPC_MSR_1               0x00001000
236#define PPC_MSR_2               0x00001000
237#define PPC_MSR_3               0x00000000
238
239#elif defined(mpc750)
240
241#define CPU_MODEL_NAME  "PowerPC 750"
242
243#define PPC_ALIGNMENT           8
244#define PPC_I_CACHE             16384
245#define PPC_D_CACHE             16384
246 
247#else
248 
249#error "Unsupported CPU Model"
250 
251#endif
252
253/*
254 *  Application binary interfaces.
255 *
256 *  PPC_ABI MUST be defined as one of these.
257 *  Only PPC_ABI_POWEROPEN is currently fully supported.
258 *  Only EABI will be supported in the end when
259 *  the tools are there.
260 *  Only big endian is currently supported.
261 */
262/*
263 *  PowerOpen ABI.  This is Andy's hack of the
264 *  PowerOpen ABI to ELF.  ELF rather than a
265 *  XCOFF assembler is used.  This may work
266 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
267 */
268#define PPC_ABI_POWEROPEN       0
269/*
270 *  GCC 2.7.0 munched version of EABI, with
271 *  PowerOpen calling convention and stack frames,
272 *  but EABI style indirect function calls.
273 */
274#define PPC_ABI_GCC27           1
275/*
276 *  SVR4 ABI
277 */
278#define PPC_ABI_SVR4            2
279/*
280 *  Embedded ABI
281 */
282#define PPC_ABI_EABI            3
283
284#if (PPC_ABI == PPC_ABI_POWEROPEN)
285#define PPC_STACK_ALIGNMENT     8
286#elif (PPC_ABI == PPC_ABI_GCC27)
287#define PPC_STACK_ALIGNMENT     8
288#elif (PPC_ABI == PPC_ABI_SVR4)
289#define PPC_STACK_ALIGNMENT     16
290#elif (PPC_ABI == PPC_ABI_EABI)
291#define PPC_STACK_ALIGNMENT     8
292#else
293#error  "PPC_ABI is not properly defined"
294#endif
295#ifndef PPC_ABI
296#error  "PPC_ABI is not properly defined"
297#endif
298
299/*
300 *  Assemblers.
301 *  PPC_ASM MUST be defined as one of these.
302 *
303 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
304 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
305 *
306 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
307 */
308
309#define PPC_ASM_ELF   0
310#define PPC_ASM_XCOFF 1
311
312/*
313 *  Use the default debug scheme defined in the architectural specification
314 *  if another model has not been specified.
315 */
316
317#ifndef PPC_DEBUG_MODEL
318#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
319#endif
320
321/*
322 *  If the maximum number of exception sources has not been defined,
323 *  then default it to 16.
324 */
325
326#ifndef PPC_INTERRUPT_MAX
327#define PPC_INTERRUPT_MAX       16
328#endif
329
330/*
331 *  Unless specified otherwise, the cache line size is defaulted to 32.
332 *
333 *  The derive the power of 2 the cache line is.
334 */
335
336#ifndef PPC_CACHE_ALIGNMENT
337#define PPC_CACHE_ALIGNMENT 32
338#endif
339
340#if (PPC_CACHE_ALIGNMENT == 16)
341#define PPC_CACHE_ALIGN_POWER 4
342#elif (PPC_CACHE_ALIGNMENT == 32)
343#define PPC_CACHE_ALIGN_POWER 5
344#else
345#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
346#endif
347
348/*
349 *  Unless otherwise specified, assume the model has an IP/EP bit to
350 *  set the exception address prefix.
351 */
352
353#ifndef PPC_HAS_EXCEPTION_PREFIX
354#define PPC_HAS_EXCEPTION_PREFIX 1
355#endif
356
357/*
358 *  Unless otherwise specified, assume the model does NOT have
359 *  403 style EVPR register to set the exception address prefix.
360 */
361
362#ifndef PPC_HAS_EVPR
363#define PPC_HAS_EVPR 0
364#endif
365
366/*
367 *  If no low power mode model was specified, then assume there is none.
368 */
369
370#ifndef PPC_LOW_POWER_MODE
371#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
372#endif
373
374/*
375 *  Unless specified above, then assume the model has FP support.
376 */
377
378#ifndef PPC_HAS_FPU
379#define PPC_HAS_FPU 1
380#endif
381
382/*
383 *  Unless specified above, If the model has FP support, it is assumed to
384 *  support doubles (8-byte floating point numbers).
385 *
386 *  If the model does NOT have FP support, then the model does
387 *  NOT have double length FP registers.
388 */
389
390#ifndef PPC_HAS_DOUBLE
391#if (PPC_HAS_FPU)
392#define PPC_HAS_DOUBLE 1
393#else
394#define PPC_HAS_DOUBLE 0
395#endif
396#endif
397
398/*
399 *  Unless specified above, then assume the model does NOT have critical
400 *  interrupt support.
401 */
402
403#ifndef PPC_HAS_RFCI
404#define PPC_HAS_RFCI 0
405#endif
406
407/*
408 *  Unless specified above, do not use the load/store multiple instructions
409 *  in a context switch.
410 */
411
412#ifndef PPC_USE_MULTIPLE
413#define PPC_USE_MULTIPLE 0
414#endif
415
416/*
417 *  The following exceptions are not maskable, and are not
418 *  necessarily predictable, so cannot be offered to RTEMS:
419 *    Alignment exception - handled by the CPU module
420 *    Data exceptions.
421 *    Instruction exceptions.
422 */
423
424/*
425 *  Base Interrupt vectors supported on all models.
426 */
427#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
428#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
429#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
430#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
431#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
432#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
433#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
434#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
435#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
436#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
437#define PPC_IRQ_RESERVED_B      10 /* 0x00a00 - Implementation Reserved    */
438#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
439#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
440#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
441#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
442
443#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
444
445#if defined(ppc403)
446                                 
447#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
448#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
449#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
450#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
451#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
452#define PPC_IRQ_LAST     PPC_IRQ_DEBUG   
453
454#elif defined(ppc601)
455#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
456#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
457
458#elif defined(ppc602)
459#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
460
461#elif defined(ppc603)
462#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
463#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
464#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
465#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
466#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
467#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
468
469#elif defined(ppc603e)
470#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
471#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
472#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
473#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
474#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
475#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
476
477
478#elif defined(ppc604)
479#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
480#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
481#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
482
483#elif defined(mpc860) || defined(mpc821)
484#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
485#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
486#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
487#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
488#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
489#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
490#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
491#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
492#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
493#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
494#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
495#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
496#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
497#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
498#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
499#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
500#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
501#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
502#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
503#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
504#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
505#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
506#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
507#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
508#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
509#define PPC_IRQ_CPM_RESERVED_0  (PPC_STD_IRQ_LAST + 26)
510#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
511#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
512#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
513#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
514#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
515#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
516#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
517#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
518#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
519#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
520#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
521#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
522#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
523#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
524#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
525#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
526#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
527#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
528#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
529#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
530#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
531#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
532#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
533#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
534#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
535#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
536#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
537#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
538#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
539#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
540#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
541
542#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
543
544#endif
545
546/*
547 *  If the maximum number of exception sources is too low,
548 *  then fix it
549 */
550
551#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
552#undef PPC_INTERRUPT_MAX
553#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
554#endif
555
556/*
557 *  Machine Status Register (MSR) Constants Used by RTEMS
558 */
559
560/*
561 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
562 *  IP for no apparent reason.
563 */
564
565#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
566#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
567#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
568
569#if (PPC_HAS_EXCEPTION_PREFIX)
570#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
571#else
572#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
573#endif
574
575#if (PPC_HAS_FPU)
576#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
577#else
578#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
579#endif
580
581#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
582#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
583#else
584#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
585#endif
586
587/*
588 *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
589 *  Environments" and the manuals for various PPC models.
590 */
591
592#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
593#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
594#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
595#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
596#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
597#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
598#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
599#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
600#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
601#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
602#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
603#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
604#else
605#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
606#endif
607
608#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
609#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
610
611#if (PPC_HAS_RFCI)
612#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
613#else
614#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
615#endif
616
617#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
618
619/*
620 *  Initial value for the FPSCR register
621 */
622
623#define PPC_INIT_FPSCR          0x000000f8
624
625#ifdef __cplusplus
626}
627#endif
628
629#endif /* ! _INCLUDE_PPC_h */
630/* end of include file */
631
632
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