| 1 | /* ppc.h |
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| 2 | * |
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| 3 | * This file contains definitions for the IBM/Motorola PowerPC |
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| 4 | * family members. |
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| 5 | * |
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| 6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 9 | * |
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| 10 | * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> |
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| 11 | * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> |
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| 12 | * Surrey Satellite Technology Limited |
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| 13 | * |
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| 14 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 15 | * without any express or implied warranty: |
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| 16 | * permission to use, copy, modify, and distribute this file |
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| 17 | * for any purpose is hereby granted without fee, provided that |
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| 18 | * the above copyright notice and this notice appears in all |
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| 19 | * copies, and that the name of i-cubed limited not be used in |
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| 20 | * advertising or publicity pertaining to distribution of the |
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| 21 | * software without specific, written prior permission. |
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| 22 | * i-cubed limited makes no representations about the suitability |
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| 23 | * of this software for any purpose. |
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| 24 | * |
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| 25 | * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: |
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| 26 | * |
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| 27 | * COPYRIGHT (c) 1989-1997. |
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| 28 | * On-Line Applications Research Corporation (OAR). |
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| 29 | * |
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| 30 | * The license and distribution terms for this file may in |
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| 31 | * the file LICENSE in this distribution or at |
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| 32 | * http://www.OARcorp.com/rtems/license.html. |
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| 33 | * |
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| 34 | * |
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| 35 | * Note: |
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| 36 | * This file is included by both C and assembler code ( -DASM ) |
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| 37 | * |
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| 38 | * $Id$ |
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| 39 | */ |
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| 40 | |
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| 41 | |
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| 42 | #ifndef _INCLUDE_PPC_h |
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| 43 | #define _INCLUDE_PPC_h |
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| 44 | |
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| 45 | #ifdef __cplusplus |
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| 46 | extern "C" { |
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| 47 | #endif |
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| 48 | |
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| 49 | #include <rtems/score/types.h> |
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| 50 | |
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| 51 | /* |
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| 52 | * Define the name of the CPU family. |
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| 53 | */ |
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| 54 | |
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| 55 | #define CPU_NAME "PowerPC" |
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| 56 | |
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| 57 | /* |
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| 58 | * This file contains the information required to build |
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| 59 | * RTEMS for a particular member of the PowerPC family. It does |
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| 60 | * this by setting variables to indicate which implementation |
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| 61 | * dependent features are present in a particular member |
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| 62 | * of the family. |
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| 63 | * |
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| 64 | * The following architectural feature definitions are defaulted |
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| 65 | * unless specifically set by the model definition: |
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| 66 | * |
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| 67 | * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD |
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| 68 | * + PPC_INTERRUPT_MAX - 16 |
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| 69 | * + PPC_CACHE_ALIGNMENT - 32 |
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| 70 | * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE |
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| 71 | * + PPC_HAS_EXCEPTION_PREFIX - 1 |
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| 72 | * + PPC_HAS_FPU - 1 |
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| 73 | * + PPC_HAS_DOUBLE - 1 if PPC_HAS_FPU, |
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| 74 | * - 0 otherwise |
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| 75 | * + PPC_USE_MULTIPLE - 0 |
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| 76 | */ |
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| 77 | |
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| 78 | /* |
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| 79 | * Define the debugging assistance models found in the PPC family. |
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| 80 | * |
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| 81 | * Standard: single step and branch trace |
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| 82 | * Single Step Only: single step only |
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| 83 | * IBM 4xx: debug exception |
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| 84 | */ |
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| 85 | |
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| 86 | #define PPC_DEBUG_MODEL_STANDARD 1 |
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| 87 | #define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2 |
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| 88 | #define PPC_DEBUG_MODEL_IBM4xx 3 |
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| 89 | |
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| 90 | /* |
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| 91 | * Define the low power mode models |
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| 92 | * |
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| 93 | * Standard: as defined for 603e |
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| 94 | * Nap Mode: nap mode only (604) |
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| 95 | * XXX 403GB, 603, 603e, 604, 821 |
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| 96 | */ |
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| 97 | |
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| 98 | #define PPC_LOW_POWER_MODE_NONE 0 |
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| 99 | #define PPC_LOW_POWER_MODE_STANDARD 1 |
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| 100 | |
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| 101 | /* |
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| 102 | * Figure out all CPU Model Feature Flags based upon compiler |
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| 103 | * predefines. |
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| 104 | */ |
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| 105 | |
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| 106 | #if defined(ppc403) || defined(ppc405) |
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| 107 | /* |
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| 108 | * IBM 403 |
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| 109 | * |
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| 110 | * Developed for 403GA. Book checked for 403GB. |
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| 111 | * |
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| 112 | * Does not have user mode. |
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| 113 | */ |
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| 114 | |
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| 115 | #if defined(ppc403) |
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| 116 | #define CPU_MODEL_NAME "PowerPC 403" |
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| 117 | #elif defined (ppc405) |
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| 118 | #define CPU_MODEL_NAME "PowerPC 405" |
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| 119 | #endif |
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| 120 | #define PPC_ALIGNMENT 4 |
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| 121 | #define PPC_CACHE_ALIGNMENT 16 |
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| 122 | #define PPC_HAS_RFCI 1 |
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| 123 | #define PPC_HAS_FPU 0 |
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| 124 | #define PPC_USE_MULTIPLE 1 |
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| 125 | #define PPC_I_CACHE 2048 |
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| 126 | #define PPC_D_CACHE 1024 |
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| 127 | |
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| 128 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx |
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| 129 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
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| 130 | #define PPC_HAS_EVPR 1 |
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| 131 | |
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| 132 | #elif defined(mpc555) |
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| 133 | |
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| 134 | #define CPU_MODEL_NAME "PowerPC 555" |
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| 135 | |
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| 136 | /* Copied from mpc505 */ |
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| 137 | #define PPC_ALIGNMENT 4 |
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| 138 | #define PPC_CACHE_ALIGNMENT 16 |
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| 139 | |
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| 140 | /* Based on comments by Sergei Organov <osv@Javad.RU> */ |
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| 141 | #define PPC_I_CACHE 0 |
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| 142 | #define PPC_D_CACHE 0 |
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| 143 | |
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| 144 | #elif defined(mpc505) || defined(mpc509) |
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| 145 | /* |
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| 146 | * Submitted by Sergei Organov <osv@Javad.RU> as a patch against |
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| 147 | * 3.6.0 long after 4.0 was released. This is just an attempt |
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| 148 | * to get the setting correct. |
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| 149 | */ |
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| 150 | |
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| 151 | #define CPU_MODEL_NAME "PowerPC 505/509" |
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| 152 | |
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| 153 | #define PPC_ALIGNMENT 4 |
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| 154 | #define PPC_CACHE_ALIGNMENT 16 |
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| 155 | #define PPC_I_CACHE 4096 |
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| 156 | #define PPC_D_CACHE 0 |
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| 157 | |
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| 158 | |
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| 159 | #elif defined(ppc601) |
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| 160 | |
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| 161 | /* |
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| 162 | * Submitted with original port -- book checked only. |
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| 163 | */ |
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| 164 | |
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| 165 | #define CPU_MODEL_NAME "PowerPC 601" |
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| 166 | |
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| 167 | #define PPC_ALIGNMENT 8 |
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| 168 | #define PPC_USE_MULTIPLE 1 |
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| 169 | #define PPC_I_CACHE 0 |
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| 170 | #define PPC_D_CACHE 32768 |
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| 171 | |
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| 172 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY |
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| 173 | |
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| 174 | #elif defined(ppc602) |
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| 175 | /* |
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| 176 | * Submitted with original port -- book checked only. |
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| 177 | */ |
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| 178 | |
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| 179 | #define CPU_MODEL_NAME "PowerPC 602" |
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| 180 | |
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| 181 | #define PPC_ALIGNMENT 4 |
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| 182 | #define PPC_HAS_DOUBLE 0 |
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| 183 | #define PPC_I_CACHE 4096 |
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| 184 | #define PPC_D_CACHE 4096 |
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| 185 | |
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| 186 | #elif defined(ppc603) |
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| 187 | /* |
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| 188 | * Submitted with original port -- book checked only. |
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| 189 | */ |
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| 190 | |
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| 191 | #define CPU_MODEL_NAME "PowerPC 603" |
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| 192 | |
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| 193 | #define PPC_ALIGNMENT 8 |
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| 194 | #define PPC_I_CACHE 8192 |
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| 195 | #define PPC_D_CACHE 8192 |
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| 196 | |
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| 197 | #elif defined(ppc603e) |
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| 198 | |
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| 199 | #define CPU_MODEL_NAME "PowerPC 603e" |
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| 200 | /* |
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| 201 | * Submitted with original port. |
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| 202 | * |
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| 203 | * Known to work on real hardware. |
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| 204 | */ |
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| 205 | |
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| 206 | #define PPC_ALIGNMENT 8 |
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| 207 | #define PPC_I_CACHE 16384 |
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| 208 | #define PPC_D_CACHE 16384 |
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| 209 | |
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| 210 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
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| 211 | |
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| 212 | #elif defined(mpc604) |
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| 213 | /* |
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| 214 | * Submitted with original port -- book checked only. |
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| 215 | */ |
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| 216 | |
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| 217 | #define CPU_MODEL_NAME "PowerPC 604" |
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| 218 | |
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| 219 | #define PPC_ALIGNMENT 8 |
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| 220 | #define PPC_I_CACHE 16384 |
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| 221 | #define PPC_D_CACHE 16384 |
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| 222 | |
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| 223 | #elif defined(mpc860) |
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| 224 | /* |
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| 225 | * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 |
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| 226 | * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) |
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| 227 | */ |
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| 228 | #define CPU_MODEL_NAME "PowerPC MPC860" |
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| 229 | |
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| 230 | #define PPC_ALIGNMENT 4 |
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| 231 | #define PPC_I_CACHE 4096 |
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| 232 | #define PPC_D_CACHE 4096 |
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| 233 | #define PPC_CACHE_ALIGNMENT 16 |
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| 234 | #define PPC_INTERRUPT_MAX 71 |
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| 235 | #define PPC_HAS_FPU 0 |
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| 236 | #define PPC_HAS_DOUBLE 0 |
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| 237 | #define PPC_USE_MULTIPLE 1 |
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| 238 | |
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| 239 | #define PPC_MSR_0 0x00009000 |
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| 240 | #define PPC_MSR_1 0x00001000 |
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| 241 | #define PPC_MSR_2 0x00001000 |
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| 242 | #define PPC_MSR_3 0x00000000 |
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| 243 | |
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| 244 | #elif defined(mpc821) |
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| 245 | /* |
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| 246 | * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 |
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| 247 | */ |
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| 248 | #define CPU_MODEL_NAME "PowerPC MPC821" |
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| 249 | |
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| 250 | #define PPC_ALIGNMENT 4 |
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| 251 | #define PPC_I_CACHE 4096 |
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| 252 | #define PPC_D_CACHE 4096 |
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| 253 | #define PPC_CACHE_ALIGNMENT 16 |
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| 254 | #define PPC_INTERRUPT_MAX 71 |
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| 255 | #define PPC_HAS_FPU 0 |
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| 256 | #define PPC_HAS_DOUBLE 0 |
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| 257 | |
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| 258 | #define PPC_MSR_0 0x00009000 |
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| 259 | #define PPC_MSR_1 0x00001000 |
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| 260 | #define PPC_MSR_2 0x00001000 |
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| 261 | #define PPC_MSR_3 0x00000000 |
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| 262 | |
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| 263 | #elif defined(mpc750) |
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| 264 | |
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| 265 | #define CPU_MODEL_NAME "PowerPC 750" |
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| 266 | |
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| 267 | #define PPC_ALIGNMENT 8 |
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| 268 | #define PPC_I_CACHE 16384 |
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| 269 | #define PPC_D_CACHE 16384 |
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| 270 | |
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| 271 | #elif defined(mpc8260) |
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| 272 | /* |
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| 273 | * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000 |
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| 274 | */ |
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| 275 | #define CPU_MODEL_NAME "PowerPC MPC8260" |
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| 276 | |
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| 277 | #define PPC_ALIGNMENT 4 |
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| 278 | #define PPC_I_CACHE 16384 |
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| 279 | #define PPC_D_CACHE 16384 |
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| 280 | #define PPC_CACHE_ALIGNMENT 32 |
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| 281 | #define PPC_INTERRUPT_MAX 125 |
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| 282 | /*#define PPC_HAS_FPU 0 */ /* my 8260 is one the few with no FPU */ |
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| 283 | #define PPC_HAS_FPU 1 /* the rest do have one */ |
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| 284 | #define PPC_HAS_DOUBLE 1 |
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| 285 | #define PPC_USE_MULTIPLE 1 |
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| 286 | #else |
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| 287 | |
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| 288 | #error "Unsupported CPU Model" |
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| 289 | |
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| 290 | #endif |
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| 291 | |
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| 292 | /* |
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| 293 | * Application binary interfaces. |
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| 294 | * |
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| 295 | * PPC_ABI MUST be defined as one of these. |
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| 296 | * Only PPC_ABI_POWEROPEN is currently fully supported. |
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| 297 | * Only EABI will be supported in the end when |
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| 298 | * the tools are there. |
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| 299 | * Only big endian is currently supported. |
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| 300 | */ |
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| 301 | /* |
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| 302 | * PowerOpen ABI. This is Andy's hack of the |
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| 303 | * PowerOpen ABI to ELF. ELF rather than a |
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| 304 | * XCOFF assembler is used. This may work |
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| 305 | * if PPC_ASM == PPC_ASM_XCOFF is defined. |
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| 306 | */ |
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| 307 | #define PPC_ABI_POWEROPEN 0 |
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| 308 | /* |
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| 309 | * GCC 2.7.0 munched version of EABI, with |
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| 310 | * PowerOpen calling convention and stack frames, |
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| 311 | * but EABI style indirect function calls. |
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| 312 | */ |
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| 313 | #define PPC_ABI_GCC27 1 |
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| 314 | /* |
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| 315 | * SVR4 ABI |
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| 316 | */ |
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| 317 | #define PPC_ABI_SVR4 2 |
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| 318 | /* |
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| 319 | * Embedded ABI |
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| 320 | */ |
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| 321 | #define PPC_ABI_EABI 3 |
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| 322 | |
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| 323 | /* |
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| 324 | * Default to the EABI used by current GNU tools |
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| 325 | */ |
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| 326 | |
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| 327 | #ifndef PPC_ABI |
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| 328 | #define PPC_ABI PPC_ABI_EABI |
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| 329 | #endif |
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| 330 | |
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| 331 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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| 332 | #define PPC_STACK_ALIGNMENT 8 |
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| 333 | #elif (PPC_ABI == PPC_ABI_GCC27) |
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| 334 | #define PPC_STACK_ALIGNMENT 8 |
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| 335 | #elif (PPC_ABI == PPC_ABI_SVR4) |
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| 336 | #define PPC_STACK_ALIGNMENT 16 |
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| 337 | #elif (PPC_ABI == PPC_ABI_EABI) |
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| 338 | #define PPC_STACK_ALIGNMENT 8 |
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| 339 | #else |
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| 340 | #error "PPC_ABI is not properly defined" |
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| 341 | #endif |
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| 342 | #ifndef PPC_ABI |
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| 343 | #error "PPC_ABI is not properly defined" |
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| 344 | #endif |
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| 345 | |
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| 346 | /* |
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| 347 | * Assemblers. |
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| 348 | * PPC_ASM MUST be defined as one of these. |
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| 349 | * |
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| 350 | * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. |
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| 351 | * PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI. |
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| 352 | * |
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| 353 | * NOTE: Only PPC_ABI_ELF is currently fully supported. |
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| 354 | */ |
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| 355 | |
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| 356 | #define PPC_ASM_ELF 0 |
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| 357 | #define PPC_ASM_XCOFF 1 |
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| 358 | |
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| 359 | /* |
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| 360 | * Default to the assembler format used by the current GNU tools. |
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| 361 | */ |
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| 362 | |
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| 363 | #ifndef PPC_ASM |
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| 364 | #define PPC_ASM PPC_ASM_ELF |
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| 365 | #endif |
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| 366 | |
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| 367 | /* |
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| 368 | * Use the default debug scheme defined in the architectural specification |
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| 369 | * if another model has not been specified. |
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| 370 | */ |
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| 371 | |
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| 372 | #ifndef PPC_DEBUG_MODEL |
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| 373 | #define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD |
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| 374 | #endif |
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| 375 | |
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| 376 | /* |
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| 377 | * If the maximum number of exception sources has not been defined, |
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| 378 | * then default it to 16. |
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| 379 | */ |
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| 380 | |
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| 381 | #ifndef PPC_INTERRUPT_MAX |
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| 382 | #define PPC_INTERRUPT_MAX 16 |
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| 383 | #endif |
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| 384 | |
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| 385 | /* |
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| 386 | * Unless specified otherwise, the cache line size is defaulted to 32. |
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| 387 | * |
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| 388 | * The derive the power of 2 the cache line is. |
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| 389 | */ |
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| 390 | |
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| 391 | #ifndef PPC_CACHE_ALIGNMENT |
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| 392 | #define PPC_CACHE_ALIGNMENT 32 |
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| 393 | #endif |
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| 394 | |
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| 395 | #if (PPC_CACHE_ALIGNMENT == 16) |
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| 396 | #define PPC_CACHE_ALIGN_POWER 4 |
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| 397 | #elif (PPC_CACHE_ALIGNMENT == 32) |
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| 398 | #define PPC_CACHE_ALIGN_POWER 5 |
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| 399 | #else |
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| 400 | #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" |
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| 401 | #endif |
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| 402 | |
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| 403 | /* |
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| 404 | * Unless otherwise specified, assume the model has an IP/EP bit to |
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| 405 | * set the exception address prefix. |
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| 406 | */ |
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| 407 | |
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| 408 | #ifndef PPC_HAS_EXCEPTION_PREFIX |
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| 409 | #define PPC_HAS_EXCEPTION_PREFIX 1 |
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| 410 | #endif |
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| 411 | |
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| 412 | /* |
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| 413 | * Unless otherwise specified, assume the model does NOT have |
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| 414 | * 403 style EVPR register to set the exception address prefix. |
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| 415 | */ |
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| 416 | |
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| 417 | #ifndef PPC_HAS_EVPR |
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| 418 | #define PPC_HAS_EVPR 0 |
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| 419 | #endif |
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| 420 | |
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| 421 | /* |
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| 422 | * If no low power mode model was specified, then assume there is none. |
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| 423 | */ |
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| 424 | |
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| 425 | #ifndef PPC_LOW_POWER_MODE |
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| 426 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE |
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| 427 | #endif |
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| 428 | |
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| 429 | /* |
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| 430 | * Unless specified above, then assume the model has FP support. |
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| 431 | */ |
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| 432 | |
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| 433 | #ifndef PPC_HAS_FPU |
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| 434 | #define PPC_HAS_FPU 1 |
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| 435 | #endif |
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| 436 | |
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| 437 | /* |
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| 438 | * Unless specified above, If the model has FP support, it is assumed to |
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| 439 | * support doubles (8-byte floating point numbers). |
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| 440 | * |
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| 441 | * If the model does NOT have FP support, then the model does |
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| 442 | * NOT have double length FP registers. |
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| 443 | */ |
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| 444 | |
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| 445 | #ifndef PPC_HAS_DOUBLE |
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| 446 | #if (PPC_HAS_FPU) |
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| 447 | #define PPC_HAS_DOUBLE 1 |
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| 448 | #else |
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| 449 | #define PPC_HAS_DOUBLE 0 |
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| 450 | #endif |
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| 451 | #endif |
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| 452 | |
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| 453 | /* |
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| 454 | * Unless specified above, then assume the model does NOT have critical |
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| 455 | * interrupt support. |
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| 456 | */ |
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| 457 | |
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| 458 | #ifndef PPC_HAS_RFCI |
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| 459 | #define PPC_HAS_RFCI 0 |
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| 460 | #endif |
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| 461 | |
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| 462 | /* |
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| 463 | * Unless specified above, do not use the load/store multiple instructions |
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| 464 | * in a context switch. |
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| 465 | */ |
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| 466 | |
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| 467 | #ifndef PPC_USE_MULTIPLE |
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| 468 | #define PPC_USE_MULTIPLE 0 |
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| 469 | #endif |
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| 470 | |
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| 471 | /* |
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| 472 | * The following exceptions are not maskable, and are not |
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| 473 | * necessarily predictable, so cannot be offered to RTEMS: |
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| 474 | * Alignment exception - handled by the CPU module |
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| 475 | * Data exceptions. |
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| 476 | * Instruction exceptions. |
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| 477 | */ |
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| 478 | |
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| 479 | /* |
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| 480 | * Base Interrupt vectors supported on all models. |
|---|
| 481 | */ |
|---|
| 482 | #define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ |
|---|
| 483 | #define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ |
|---|
| 484 | #define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ |
|---|
| 485 | #define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ |
|---|
| 486 | #define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ |
|---|
| 487 | #define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ |
|---|
| 488 | #define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ |
|---|
| 489 | #define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ |
|---|
| 490 | #define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ |
|---|
| 491 | #define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ |
|---|
| 492 | #define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ |
|---|
| 493 | #define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ |
|---|
| 494 | #define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ |
|---|
| 495 | #define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ |
|---|
| 496 | #define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST |
|---|
| 497 | |
|---|
| 498 | #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET |
|---|
| 499 | |
|---|
| 500 | #if defined(ppc403) || defined(ppc405) |
|---|
| 501 | |
|---|
| 502 | #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ |
|---|
| 503 | #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ |
|---|
| 504 | #define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ |
|---|
| 505 | #define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ |
|---|
| 506 | #define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ |
|---|
| 507 | #define PPC_IRQ_LAST PPC_IRQ_DEBUG |
|---|
| 508 | |
|---|
| 509 | #elif defined(mpc505) || defined(mpc509) |
|---|
| 510 | #define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ |
|---|
| 511 | #define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) |
|---|
| 512 | #define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) |
|---|
| 513 | #define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) |
|---|
| 514 | #define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) |
|---|
| 515 | |
|---|
| 516 | #elif defined(ppc601) |
|---|
| 517 | #define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ |
|---|
| 518 | #define PPC_IRQ_LAST PPC_IRQ_TRACE |
|---|
| 519 | |
|---|
| 520 | #elif defined(ppc602) |
|---|
| 521 | #define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) |
|---|
| 522 | |
|---|
| 523 | #elif defined(ppc603) |
|---|
| 524 | #define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ |
|---|
| 525 | #define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ |
|---|
| 526 | #define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ |
|---|
| 527 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ |
|---|
| 528 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
|---|
| 529 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
|---|
| 530 | |
|---|
| 531 | #elif defined(ppc603e) |
|---|
| 532 | #define PPC_TLB_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/ |
|---|
| 533 | #define PPC_TLB_LOAD_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load */ |
|---|
| 534 | #define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */ |
|---|
| 535 | #define PPC_IRQ_ADDRBRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */ |
|---|
| 536 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
|---|
| 537 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
|---|
| 538 | |
|---|
| 539 | |
|---|
| 540 | #elif defined(mpc604) |
|---|
| 541 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ |
|---|
| 542 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ |
|---|
| 543 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
|---|
| 544 | |
|---|
| 545 | #elif defined(mpc860) || defined(mpc821) |
|---|
| 546 | #define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ |
|---|
| 547 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ |
|---|
| 548 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ |
|---|
| 549 | #define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ |
|---|
| 550 | #define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ |
|---|
| 551 | #define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ |
|---|
| 552 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ |
|---|
| 553 | #define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ |
|---|
| 554 | #define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ |
|---|
| 555 | #define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) |
|---|
| 556 | #define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) |
|---|
| 557 | #define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) |
|---|
| 558 | #define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) |
|---|
| 559 | #define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) |
|---|
| 560 | #define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) |
|---|
| 561 | #define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) |
|---|
| 562 | #define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) |
|---|
| 563 | #define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) |
|---|
| 564 | #define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) |
|---|
| 565 | #define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) |
|---|
| 566 | #define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) |
|---|
| 567 | #define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) |
|---|
| 568 | #define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) |
|---|
| 569 | #define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) |
|---|
| 570 | #define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) |
|---|
| 571 | #define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) |
|---|
| 572 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) |
|---|
| 573 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) |
|---|
| 574 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) |
|---|
| 575 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) |
|---|
| 576 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) |
|---|
| 577 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) |
|---|
| 578 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) |
|---|
| 579 | #define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) |
|---|
| 580 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) |
|---|
| 581 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) |
|---|
| 582 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) |
|---|
| 583 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) |
|---|
| 584 | #define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) |
|---|
| 585 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) |
|---|
| 586 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) |
|---|
| 587 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) |
|---|
| 588 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) |
|---|
| 589 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) |
|---|
| 590 | #define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) |
|---|
| 591 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) |
|---|
| 592 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) |
|---|
| 593 | #define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) |
|---|
| 594 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) |
|---|
| 595 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) |
|---|
| 596 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) |
|---|
| 597 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) |
|---|
| 598 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) |
|---|
| 599 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) |
|---|
| 600 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) |
|---|
| 601 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) |
|---|
| 602 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) |
|---|
| 603 | |
|---|
| 604 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 |
|---|
| 605 | |
|---|
| 606 | #elif defined(mpc8260) |
|---|
| 607 | |
|---|
| 608 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ |
|---|
| 609 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ |
|---|
| 610 | #define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ |
|---|
| 611 | #define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ |
|---|
| 612 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ |
|---|
| 613 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ |
|---|
| 614 | /* 0x1600 - 0x2F00 reserved */ |
|---|
| 615 | #define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) |
|---|
| 616 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) |
|---|
| 617 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) |
|---|
| 618 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) |
|---|
| 619 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) |
|---|
| 620 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) |
|---|
| 621 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) |
|---|
| 622 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) |
|---|
| 623 | #define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) |
|---|
| 624 | #define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) |
|---|
| 625 | #define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) |
|---|
| 626 | #define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) |
|---|
| 627 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) |
|---|
| 628 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) |
|---|
| 629 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) |
|---|
| 630 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) |
|---|
| 631 | #define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) |
|---|
| 632 | #define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) |
|---|
| 633 | #define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) |
|---|
| 634 | #define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) |
|---|
| 635 | #define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) |
|---|
| 636 | #define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) |
|---|
| 637 | #define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) |
|---|
| 638 | #define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) |
|---|
| 639 | #define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) |
|---|
| 640 | #define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) |
|---|
| 641 | #define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) |
|---|
| 642 | #define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) |
|---|
| 643 | #define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) |
|---|
| 644 | #define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) |
|---|
| 645 | #define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) |
|---|
| 646 | #define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) |
|---|
| 647 | #define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) |
|---|
| 648 | #define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) |
|---|
| 649 | #define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) |
|---|
| 650 | #define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) |
|---|
| 651 | #define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) |
|---|
| 652 | #define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) |
|---|
| 653 | #define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) |
|---|
| 654 | #define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) |
|---|
| 655 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) |
|---|
| 656 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) |
|---|
| 657 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) |
|---|
| 658 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) |
|---|
| 659 | #define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) |
|---|
| 660 | #define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) |
|---|
| 661 | #define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) |
|---|
| 662 | #define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) |
|---|
| 663 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) |
|---|
| 664 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) |
|---|
| 665 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) |
|---|
| 666 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) |
|---|
| 667 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) |
|---|
| 668 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) |
|---|
| 669 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) |
|---|
| 670 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) |
|---|
| 671 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) |
|---|
| 672 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) |
|---|
| 673 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) |
|---|
| 674 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) |
|---|
| 675 | #define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) |
|---|
| 676 | #define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) |
|---|
| 677 | #define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) |
|---|
| 678 | #define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) |
|---|
| 679 | |
|---|
| 680 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 |
|---|
| 681 | |
|---|
| 682 | #endif |
|---|
| 683 | |
|---|
| 684 | |
|---|
| 685 | /* |
|---|
| 686 | * If the maximum number of exception sources is too low, |
|---|
| 687 | * then fix it |
|---|
| 688 | */ |
|---|
| 689 | |
|---|
| 690 | #if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST |
|---|
| 691 | #undef PPC_INTERRUPT_MAX |
|---|
| 692 | #define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) |
|---|
| 693 | #endif |
|---|
| 694 | |
|---|
| 695 | /* |
|---|
| 696 | * Machine Status Register (MSR) Constants Used by RTEMS |
|---|
| 697 | */ |
|---|
| 698 | |
|---|
| 699 | /* |
|---|
| 700 | * Some PPC model manuals refer to the Exception Prefix (EP) bit as |
|---|
| 701 | * IP for no apparent reason. |
|---|
| 702 | */ |
|---|
| 703 | |
|---|
| 704 | #define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ |
|---|
| 705 | #define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ |
|---|
| 706 | #define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ |
|---|
| 707 | |
|---|
| 708 | #if (PPC_HAS_EXCEPTION_PREFIX) |
|---|
| 709 | #define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ |
|---|
| 710 | #else |
|---|
| 711 | #define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ |
|---|
| 712 | #endif |
|---|
| 713 | |
|---|
| 714 | #if (PPC_HAS_FPU) |
|---|
| 715 | #define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ |
|---|
| 716 | #else |
|---|
| 717 | #define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ |
|---|
| 718 | #endif |
|---|
| 719 | |
|---|
| 720 | #if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) |
|---|
| 721 | #define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ |
|---|
| 722 | #else |
|---|
| 723 | #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ |
|---|
| 724 | #endif |
|---|
| 725 | |
|---|
| 726 | /* |
|---|
| 727 | * Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming |
|---|
| 728 | * Environments" and the manuals for various PPC models. |
|---|
| 729 | */ |
|---|
| 730 | |
|---|
| 731 | #if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD) |
|---|
| 732 | #define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ |
|---|
| 733 | #define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ |
|---|
| 734 | #define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */ |
|---|
| 735 | #elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY) |
|---|
| 736 | #define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ |
|---|
| 737 | #define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ |
|---|
| 738 | #define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ |
|---|
| 739 | #elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx) |
|---|
| 740 | #define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */ |
|---|
| 741 | #define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */ |
|---|
| 742 | #define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ |
|---|
| 743 | #else |
|---|
| 744 | #error "MSR constants -- unknown PPC_DEBUG_MODEL!!" |
|---|
| 745 | #endif |
|---|
| 746 | |
|---|
| 747 | #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ |
|---|
| 748 | #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ |
|---|
| 749 | |
|---|
| 750 | #if (PPC_HAS_RFCI) |
|---|
| 751 | #define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ |
|---|
| 752 | #else |
|---|
| 753 | #define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ |
|---|
| 754 | #endif |
|---|
| 755 | |
|---|
| 756 | #define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) |
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| 757 | |
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| 758 | /* |
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| 759 | * Initial value for the FPSCR register |
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| 760 | */ |
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| 761 | |
|---|
| 762 | #define PPC_INIT_FPSCR 0x000000f8 |
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| 763 | |
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| 764 | #ifdef __cplusplus |
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| 765 | } |
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| 766 | #endif |
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| 767 | |
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| 768 | #endif /* ! _INCLUDE_PPC_h */ |
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| 769 | /* end of include file */ |
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| 770 | |
|---|
| 771 | |
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