source: rtems/cpukit/score/cpu/powerpc/rtems/score/powerpc.h @ c1f4761

4.104.114.84.95
Last change on this file since c1f4761 was c1f4761, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 13, 2005 at 10:41:01 AM

2005-02-13 Ralf Corsepius <ralf.corsepius@…>

  • rtems/score/powerp.c: Remove PPC_HAS_EXCEPTION_PREFIX (Unused).
  • Property mode set to 100644
File size: 18.3 KB
Line 
1/**
2 * @file rtems/score/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_SCORE_POWERPC_H
46#define _RTEMS_SCORE_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#include <rtems/score/types.h>
53
54/*
55 *  Define the name of the CPU family.
56 */
57
58#define CPU_NAME "PowerPC"
59
60/*
61 *  This file contains the information required to build
62 *  RTEMS for a particular member of the PowerPC family.  It does
63 *  this by setting variables to indicate which implementation
64 *  dependent features are present in a particular member
65 *  of the family.
66 *
67 *  The following architectural feature definitions are defaulted
68 *  unless specifically set by the model definition:
69 *
70 *    + PPC_INTERRUPT_MAX        - 16
71 *    + PPC_CACHE_ALIGNMENT      - 32
72 *    + PPC_HAS_FPU              - 1
73 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
74 *                               - 0 otherwise
75 */
76 
77/*
78 *  Figure out all CPU Model Feature Flags based upon compiler
79 *  predefines.
80 */
81
82#if defined(ppc403) || defined(ppc405)
83/*
84 *  IBM 403
85 *
86 *  Developed for 403GA.  Book checked for 403GB.
87 *
88 *  Does not have user mode.
89 */
90 
91#if defined(ppc403)
92#define CPU_MODEL_NAME "PowerPC 403"
93#elif defined (ppc405)
94#define CPU_MODEL_NAME "PowerPC 405"
95#endif
96#define PPC_ALIGNMENT           4 
97#define PPC_CACHE_ALIGNMENT     16
98#define PPC_HAS_RFCI            1
99
100#elif defined(mpc555)
101
102#define CPU_MODEL_NAME  "PowerPC 555"
103
104/* Copied from mpc505 */
105#define PPC_ALIGNMENT           4
106#define PPC_CACHE_ALIGNMENT     16
107
108#elif defined(mpc505) || defined(mpc509)
109/*
110 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
111 *  3.6.0 long after 4.0 was released.   This is just an attempt
112 *  to get the setting correct.
113 */
114
115#define CPU_MODEL_NAME  "PowerPC 505/509"
116
117#define PPC_ALIGNMENT           4
118#define PPC_CACHE_ALIGNMENT     16
119
120#elif defined(ppc601)
121
122/*
123 *  Submitted with original port -- book checked only.
124 */
125 
126#define CPU_MODEL_NAME  "PowerPC 601"
127
128#define PPC_ALIGNMENT           8
129
130#elif defined(ppc602)
131/*
132 *  Submitted with original port -- book checked only.
133 */
134 
135#define CPU_MODEL_NAME  "PowerPC 602"
136
137#define PPC_ALIGNMENT           4
138#define PPC_HAS_DOUBLE          0
139
140#elif defined(ppc603)
141/*
142 *  Submitted with original port -- book checked only.
143 */
144 
145#define CPU_MODEL_NAME  "PowerPC 603"
146
147#define PPC_ALIGNMENT           8
148
149#elif defined(ppc603e)
150 
151#define CPU_MODEL_NAME  "PowerPC 603e"
152/*
153 *  Submitted with original port.
154 *
155 *  Known to work on real hardware.
156 */
157
158#define PPC_ALIGNMENT           8
159
160#elif defined(mpc604)
161/*
162 *  Submitted with original port -- book checked only.
163 */
164 
165#define CPU_MODEL_NAME  "PowerPC 604"
166
167#define PPC_ALIGNMENT           8
168 
169#elif defined(mpc860)
170/*
171 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
172 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
173 */ 
174#define CPU_MODEL_NAME  "PowerPC MPC860"
175
176#define PPC_ALIGNMENT           4
177#define PPC_CACHE_ALIGNMENT     16
178#define PPC_INTERRUPT_MAX       71
179
180#elif defined(mpc821)
181/*
182 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
183 */ 
184#define CPU_MODEL_NAME  "PowerPC MPC821"
185
186#define PPC_ALIGNMENT           4
187#define PPC_CACHE_ALIGNMENT     16
188#define PPC_INTERRUPT_MAX       71
189
190#elif defined(mpc750)
191
192#define CPU_MODEL_NAME  "PowerPC 750"
193
194#define PPC_ALIGNMENT           8
195
196#elif defined(mpc7400)
197
198#define CPU_MODEL_NAME  "PowerPC 7400"
199
200#define PPC_ALIGNMENT           8
201
202#elif defined(mpc7455)
203/*
204 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
205 */
206
207#define CPU_MODEL_NAME  "PowerPC 7455"
208
209#define PPC_ALIGNMENT           8
210#define PPC_CACHE_ALIGNMENT     32
211
212#elif defined(mpc8260)
213/*
214 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
215 */
216#define CPU_MODEL_NAME  "PowerPC MPC8260"
217
218#define PPC_ALIGNMENT           4
219#define PPC_CACHE_ALIGNMENT     32
220#define PPC_INTERRUPT_MAX       125
221#else
222 
223#error "Unsupported CPU Model"
224 
225#endif
226
227/*
228 *  Application binary interfaces.
229 *
230 *  PPC_ABI MUST be defined as one of these.
231 *  Only big endian is currently supported.
232 */
233/*
234 *  SVR4 ABI
235 */
236#define PPC_ABI_SVR4            2
237/*
238 *  Embedded ABI
239 */
240#define PPC_ABI_EABI            3
241
242/*
243 *  Default to the EABI used by current GNU tools
244 */
245
246#ifndef PPC_ABI
247#define PPC_ABI PPC_ABI_EABI
248#endif
249
250#if (PPC_ABI == PPC_ABI_SVR4)
251#define PPC_STACK_ALIGNMENT     16
252#elif (PPC_ABI == PPC_ABI_EABI)
253#define PPC_STACK_ALIGNMENT     8
254#else
255#error  "PPC_ABI is not properly defined"
256#endif
257
258/*
259 *  Assemblers.
260 *  PPC_ASM MUST be defined as one of these.
261 *
262 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
263 *
264 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
265 */
266
267#define PPC_ASM_ELF   0
268
269/*
270 *  Default to the assembler format used by the current GNU tools.
271 */
272
273#ifndef PPC_ASM
274#define PPC_ASM PPC_ASM_ELF
275#endif
276
277/*
278 *  If the maximum number of exception sources has not been defined,
279 *  then default it to 16.
280 */
281
282#ifndef PPC_INTERRUPT_MAX
283#define PPC_INTERRUPT_MAX       16
284#endif
285
286/*
287 *  Unless specified otherwise, the cache line size is defaulted to 32.
288 *
289 *  The derive the power of 2 the cache line is.
290 */
291
292#ifndef PPC_CACHE_ALIGNMENT
293#define PPC_CACHE_ALIGNMENT 32
294#endif
295
296/*
297 *  Unless specified above, assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT.
298 *  FIXME: Should we tie PPC_HAS_FPU to _SOFT_FLOAT, directly
299 *     and disallow explicitly setting PPC_HAS_FPU?
300 */
301
302#ifndef PPC_HAS_FPU
303#ifdef _SOFT_FLOAT
304#define PPC_HAS_FPU 0
305#else
306#define PPC_HAS_FPU 1
307#endif
308#endif
309
310/*
311 *  Unless specified above, If the model has FP support, it is assumed to
312 *  support doubles (8-byte floating point numbers).
313 *
314 *  If the model does NOT have FP support, then the model does
315 *  NOT have double length FP registers.
316 */
317
318#ifndef PPC_HAS_DOUBLE
319#if (PPC_HAS_FPU)
320#define PPC_HAS_DOUBLE 1
321#else
322#define PPC_HAS_DOUBLE 0
323#endif
324#endif
325
326/*
327 *  Unless specified above, then assume the model does NOT have critical
328 *  interrupt support.
329 */
330
331#ifndef PPC_HAS_RFCI
332#define PPC_HAS_RFCI 0
333#endif
334
335/*
336 *  The following exceptions are not maskable, and are not
337 *  necessarily predictable, so cannot be offered to RTEMS:
338 *    Alignment exception - handled by the CPU module
339 *    Data exceptions.
340 *    Instruction exceptions.
341 */
342
343/*
344 *  Base Interrupt vectors supported on all models.
345 */
346#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
347#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
348#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
349#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
350#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
351#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
352#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
353#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
354#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
355#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
356#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
357#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
358#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
359#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
360#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
361
362#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
363
364#if defined(ppc403) || defined(ppc405)
365                                 
366#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
367#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
368#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
369#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
370#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
371#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
372
373#elif defined(mpc505) || defined(mpc509)
374#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
375#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
376#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
377#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
378#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
379
380#elif defined(mpc555)
381#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
382#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
383#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
384#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
385#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
386#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
387#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
388#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
389
390#elif defined(ppc601)
391#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
392#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
393
394#elif defined(ppc602)
395#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
396
397#elif defined(ppc603)
398#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
399#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
400#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
401#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
402#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
403#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
404
405#elif defined(ppc603e)
406#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
407#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
408#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
409#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
410#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
411#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
412
413
414#elif defined(mpc604)
415#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
416#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
417#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
418
419#elif defined(mpc860) || defined(mpc821)
420#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
421#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
422#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
423#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
424#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
425#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
426#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
427#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
428#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
429#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
430#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
431#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
432#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
433#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
434#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
435#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
436#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
437#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
438#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
439#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
440#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
441#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
442#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
443#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
444#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
445#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
446#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
447#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
448#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
449#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
450#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
451#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
452#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
453#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
454#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
455#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
456#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
457#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
458#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
459#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
460#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
461#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
462#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
463#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
464#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
465#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
466#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
467#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
468#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
469#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
470#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
471#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
472#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
473#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
474#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
475#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
476#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
477
478#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
479
480#elif defined(mpc8260)
481
482#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
483#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
484#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
485#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
486#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
487#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
488/* 0x1600 - 0x2F00 reserved */
489#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
490#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
491#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
492#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
493#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
494#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
495#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
496#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
497#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
498#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
499#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
500#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
501#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
502#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
503#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
504#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
505#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
506#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
507#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
508#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
509#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
510#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
511#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
512#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
513#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
514#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
515#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
516#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
517#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
518#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
519#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
520#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
521#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
522#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
523#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
524#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
525#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
526#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
527#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
528#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
529#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
530#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
531#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
532#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
533#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
534#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
535#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
536#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
537#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
538#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
539#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
540#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
541#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
542#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
543#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
544#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
545#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
546#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
547#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
548#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
549#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
550#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
551#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
552#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
553
554#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
555
556#endif
557
558
559/*
560 *  If the maximum number of exception sources is too low,
561 *  then fix it
562 */
563
564#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
565#undef PPC_INTERRUPT_MAX
566#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
567#endif
568
569/*
570 *  Initial value for the FPSCR register
571 */
572
573#define PPC_INIT_FPSCR          0x000000f8
574
575#ifdef __cplusplus
576}
577#endif
578
579#endif /* _RTEMS_SCORE_POWERPC_H */
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