source: rtems/cpukit/score/cpu/powerpc/rtems/score/powerpc.h @ 5022a49

4.104.114.84.95
Last change on this file since 5022a49 was 5022a49, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 13, 2005 at 7:48:16 AM

2005-02-13 Ralf Corsepius <ralf.corsepius@…>

  • rtems/score/powerpc.h: Remove PPC_D_CACHE, PPC_I_CACHE defines.
  • Property mode set to 100644
File size: 19.8 KB
Line 
1/**
2 * @file rtems/score/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_SCORE_POWERPC_H
46#define _RTEMS_SCORE_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#include <rtems/score/types.h>
53
54/*
55 *  Define the name of the CPU family.
56 */
57
58#define CPU_NAME "PowerPC"
59
60/*
61 *  This file contains the information required to build
62 *  RTEMS for a particular member of the PowerPC family.  It does
63 *  this by setting variables to indicate which implementation
64 *  dependent features are present in a particular member
65 *  of the family.
66 *
67 *  The following architectural feature definitions are defaulted
68 *  unless specifically set by the model definition:
69 *
70 *    + PPC_INTERRUPT_MAX        - 16
71 *    + PPC_CACHE_ALIGNMENT      - 32
72 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
73 *    + PPC_HAS_EXCEPTION_PREFIX - 1
74 *    + PPC_HAS_FPU              - 1
75 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
76 *                               - 0 otherwise
77 *    + PPC_USE_MULTIPLE         - 0
78 */
79 
80/*
81 *  Define the low power mode models
82 *
83 *  Standard:   as defined for 603e
84 *  Nap Mode:   nap mode only (604)
85 *  XXX 403GB, 603, 603e, 604, 821
86 */
87
88#define PPC_LOW_POWER_MODE_NONE      0
89#define PPC_LOW_POWER_MODE_STANDARD  1
90
91/*
92 *  Figure out all CPU Model Feature Flags based upon compiler
93 *  predefines.
94 */
95
96#if defined(ppc403) || defined(ppc405)
97/*
98 *  IBM 403
99 *
100 *  Developed for 403GA.  Book checked for 403GB.
101 *
102 *  Does not have user mode.
103 */
104 
105#if defined(ppc403)
106#define CPU_MODEL_NAME "PowerPC 403"
107#elif defined (ppc405)
108#define CPU_MODEL_NAME "PowerPC 405"
109#endif
110#define PPC_ALIGNMENT           4 
111#define PPC_CACHE_ALIGNMENT     16
112#define PPC_HAS_RFCI            1
113#define PPC_USE_MULTIPLE        1
114
115#define PPC_HAS_EXCEPTION_PREFIX 0
116#define PPC_HAS_EVPR             1
117
118#elif defined(mpc555)
119
120#define CPU_MODEL_NAME  "PowerPC 555"
121
122/* Copied from mpc505 */
123#define PPC_ALIGNMENT           4
124#define PPC_CACHE_ALIGNMENT     16
125
126/* Added by querbach@realtime.bc.ca */
127#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
128
129#elif defined(mpc505) || defined(mpc509)
130/*
131 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
132 *  3.6.0 long after 4.0 was released.   This is just an attempt
133 *  to get the setting correct.
134 */
135
136#define CPU_MODEL_NAME  "PowerPC 505/509"
137
138#define PPC_ALIGNMENT           4
139#define PPC_CACHE_ALIGNMENT     16
140
141#elif defined(ppc601)
142
143/*
144 *  Submitted with original port -- book checked only.
145 */
146 
147#define CPU_MODEL_NAME  "PowerPC 601"
148
149#define PPC_ALIGNMENT           8
150#define PPC_USE_MULTIPLE        1
151
152#elif defined(ppc602)
153/*
154 *  Submitted with original port -- book checked only.
155 */
156 
157#define CPU_MODEL_NAME  "PowerPC 602"
158
159#define PPC_ALIGNMENT           4
160#define PPC_HAS_DOUBLE          0
161
162#elif defined(ppc603)
163/*
164 *  Submitted with original port -- book checked only.
165 */
166 
167#define CPU_MODEL_NAME  "PowerPC 603"
168
169#define PPC_ALIGNMENT           8
170
171#elif defined(ppc603e)
172 
173#define CPU_MODEL_NAME  "PowerPC 603e"
174/*
175 *  Submitted with original port.
176 *
177 *  Known to work on real hardware.
178 */
179
180#define PPC_ALIGNMENT           8
181
182#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
183
184#elif defined(mpc604)
185/*
186 *  Submitted with original port -- book checked only.
187 */
188 
189#define CPU_MODEL_NAME  "PowerPC 604"
190
191#define PPC_ALIGNMENT           8
192 
193#elif defined(mpc860)
194/*
195 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
196 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
197 */ 
198#define CPU_MODEL_NAME  "PowerPC MPC860"
199
200#define PPC_ALIGNMENT           4
201#define PPC_CACHE_ALIGNMENT     16
202#define PPC_INTERRUPT_MAX       71
203#define PPC_USE_MULTIPLE        1
204
205#elif defined(mpc821)
206/*
207 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
208 */ 
209#define CPU_MODEL_NAME  "PowerPC MPC821"
210
211#define PPC_ALIGNMENT           4
212#define PPC_CACHE_ALIGNMENT     16
213#define PPC_INTERRUPT_MAX       71
214
215#elif defined(mpc750)
216
217#define CPU_MODEL_NAME  "PowerPC 750"
218
219#define PPC_ALIGNMENT           8
220
221#elif defined(mpc7400)
222
223#define CPU_MODEL_NAME  "PowerPC 7400"
224
225#define PPC_ALIGNMENT           8
226
227#elif defined(mpc7455)
228/*
229 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
230 */
231
232#define CPU_MODEL_NAME  "PowerPC 7455"
233
234#define PPC_ALIGNMENT           8
235#define PPC_CACHE_ALIGNMENT     32
236
237#elif defined(mpc8260)
238/*
239 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
240 */
241#define CPU_MODEL_NAME  "PowerPC MPC8260"
242
243#define PPC_ALIGNMENT           4
244#define PPC_CACHE_ALIGNMENT     32
245#define PPC_INTERRUPT_MAX       125
246#define PPC_USE_MULTIPLE        1
247#else
248 
249#error "Unsupported CPU Model"
250 
251#endif
252
253/*
254 *  Application binary interfaces.
255 *
256 *  PPC_ABI MUST be defined as one of these.
257 *  Only big endian is currently supported.
258 */
259/*
260 *  SVR4 ABI
261 */
262#define PPC_ABI_SVR4            2
263/*
264 *  Embedded ABI
265 */
266#define PPC_ABI_EABI            3
267
268/*
269 *  Default to the EABI used by current GNU tools
270 */
271
272#ifndef PPC_ABI
273#define PPC_ABI PPC_ABI_EABI
274#endif
275
276#if (PPC_ABI == PPC_ABI_SVR4)
277#define PPC_STACK_ALIGNMENT     16
278#elif (PPC_ABI == PPC_ABI_EABI)
279#define PPC_STACK_ALIGNMENT     8
280#else
281#error  "PPC_ABI is not properly defined"
282#endif
283
284/*
285 *  Assemblers.
286 *  PPC_ASM MUST be defined as one of these.
287 *
288 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
289 *
290 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
291 */
292
293#define PPC_ASM_ELF   0
294
295/*
296 *  Default to the assembler format used by the current GNU tools.
297 */
298
299#ifndef PPC_ASM
300#define PPC_ASM PPC_ASM_ELF
301#endif
302
303/*
304 *  If the maximum number of exception sources has not been defined,
305 *  then default it to 16.
306 */
307
308#ifndef PPC_INTERRUPT_MAX
309#define PPC_INTERRUPT_MAX       16
310#endif
311
312/*
313 *  Unless specified otherwise, the cache line size is defaulted to 32.
314 *
315 *  The derive the power of 2 the cache line is.
316 */
317
318#ifndef PPC_CACHE_ALIGNMENT
319#define PPC_CACHE_ALIGNMENT 32
320#endif
321
322#if (PPC_CACHE_ALIGNMENT == 16)
323#define PPC_CACHE_ALIGN_POWER 4
324#elif (PPC_CACHE_ALIGNMENT == 32)
325#define PPC_CACHE_ALIGN_POWER 5
326#else
327#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
328#endif
329
330/*
331 *  Unless otherwise specified, assume the model has an IP/EP bit to
332 *  set the exception address prefix.
333 */
334
335#ifndef PPC_HAS_EXCEPTION_PREFIX
336#define PPC_HAS_EXCEPTION_PREFIX 1
337#endif
338
339/*
340 *  Unless otherwise specified, assume the model does NOT have
341 *  403 style EVPR register to set the exception address prefix.
342 */
343
344#ifndef PPC_HAS_EVPR
345#define PPC_HAS_EVPR 0
346#endif
347
348/*
349 *  If no low power mode model was specified, then assume there is none.
350 */
351
352#ifndef PPC_LOW_POWER_MODE
353#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
354#endif
355
356/*
357 *  Unless specified above, assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT.
358 *  FIXME: Should we tie PPC_HAS_FPU to _SOFT_FLOAT, directly
359 *     and disallow explicitly setting PPC_HAS_FPU?
360 */
361
362#ifndef PPC_HAS_FPU
363#ifdef _SOFT_FLOAT
364#define PPC_HAS_FPU 0
365#else
366#define PPC_HAS_FPU 1
367#endif
368#endif
369
370/*
371 *  Unless specified above, If the model has FP support, it is assumed to
372 *  support doubles (8-byte floating point numbers).
373 *
374 *  If the model does NOT have FP support, then the model does
375 *  NOT have double length FP registers.
376 */
377
378#ifndef PPC_HAS_DOUBLE
379#if (PPC_HAS_FPU)
380#define PPC_HAS_DOUBLE 1
381#else
382#define PPC_HAS_DOUBLE 0
383#endif
384#endif
385
386/*
387 *  Unless specified above, then assume the model does NOT have critical
388 *  interrupt support.
389 */
390
391#ifndef PPC_HAS_RFCI
392#define PPC_HAS_RFCI 0
393#endif
394
395/*
396 *  Unless specified above, do not use the load/store multiple instructions
397 *  in a context switch.
398 */
399
400#ifndef PPC_USE_MULTIPLE
401#define PPC_USE_MULTIPLE 0
402#endif
403
404/*
405 *  The following exceptions are not maskable, and are not
406 *  necessarily predictable, so cannot be offered to RTEMS:
407 *    Alignment exception - handled by the CPU module
408 *    Data exceptions.
409 *    Instruction exceptions.
410 */
411
412/*
413 *  Base Interrupt vectors supported on all models.
414 */
415#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
416#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
417#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
418#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
419#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
420#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
421#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
422#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
423#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
424#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
425#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
426#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
427#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
428#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
429#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
430
431#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
432
433#if defined(ppc403) || defined(ppc405)
434                                 
435#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
436#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
437#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
438#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
439#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
440#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
441
442#elif defined(mpc505) || defined(mpc509)
443#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
444#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
445#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
446#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
447#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
448
449#elif defined(mpc555)
450#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
451#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
452#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
453#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
454#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
455#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
456#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
457#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
458
459#elif defined(ppc601)
460#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
461#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
462
463#elif defined(ppc602)
464#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
465
466#elif defined(ppc603)
467#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
468#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
469#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
470#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
471#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
472#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
473
474#elif defined(ppc603e)
475#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
476#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
477#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
478#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
479#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
480#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
481
482
483#elif defined(mpc604)
484#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
485#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
486#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
487
488#elif defined(mpc860) || defined(mpc821)
489#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
490#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
491#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
492#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
493#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
494#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
495#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
496#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
497#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
498#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
499#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
500#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
501#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
502#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
503#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
504#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
505#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
506#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
507#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
508#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
509#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
510#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
511#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
512#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
513#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
514#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
515#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
516#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
517#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
518#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
519#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
520#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
521#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
522#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
523#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
524#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
525#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
526#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
527#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
528#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
529#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
530#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
531#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
532#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
533#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
534#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
535#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
536#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
537#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
538#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
539#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
540#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
541#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
542#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
543#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
544#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
545#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
546
547#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
548
549#elif defined(mpc8260)
550
551#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
552#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
553#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
554#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
555#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
556#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
557/* 0x1600 - 0x2F00 reserved */
558#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
559#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
560#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
561#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
562#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
563#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
564#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
565#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
566#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
567#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
568#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
569#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
570#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
571#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
572#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
573#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
574#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
575#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
576#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
577#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
578#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
579#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
580#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
581#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
582#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
583#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
584#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
585#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
586#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
587#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
588#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
589#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
590#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
591#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
592#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
593#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
594#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
595#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
596#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
597#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
598#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
599#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
600#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
601#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
602#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
603#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
604#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
605#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
606#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
607#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
608#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
609#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
610#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
611#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
612#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
613#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
614#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
615#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
616#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
617#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
618#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
619#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
620#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
621#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
622
623#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
624
625#endif
626
627
628/*
629 *  If the maximum number of exception sources is too low,
630 *  then fix it
631 */
632
633#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
634#undef PPC_INTERRUPT_MAX
635#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
636#endif
637
638/*
639 *  Initial value for the FPSCR register
640 */
641
642#define PPC_INIT_FPSCR          0x000000f8
643
644#ifdef __cplusplus
645}
646#endif
647
648#endif /* _RTEMS_SCORE_POWERPC_H */
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