source: rtems/cpukit/score/cpu/powerpc/rtems/score/powerpc.h @ 3d852ab

4.104.114.84.95
Last change on this file since 3d852ab was 3d852ab, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 10, 2005 at 3:22:07 PM

2005-02-10 Ralf Corsepius <ralf.corsepius@…>

  • rtems/asm.h, rtems/old-exceptions/cpu.h, rtems/score/powerpc.h: Remove PPC_ABI_POWEROPEN.
  • Property mode set to 100644
File size: 22.3 KB
Line 
1/**
2 * @file rtems/score/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_SCORE_POWERPC_H
46#define _RTEMS_SCORE_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#include <rtems/score/types.h>
53
54/*
55 *  Define the name of the CPU family.
56 */
57
58#define CPU_NAME "PowerPC"
59
60/*
61 *  This file contains the information required to build
62 *  RTEMS for a particular member of the PowerPC family.  It does
63 *  this by setting variables to indicate which implementation
64 *  dependent features are present in a particular member
65 *  of the family.
66 *
67 *  The following architectural feature definitions are defaulted
68 *  unless specifically set by the model definition:
69 *
70 *    + PPC_INTERRUPT_MAX        - 16
71 *    + PPC_CACHE_ALIGNMENT      - 32
72 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
73 *    + PPC_HAS_EXCEPTION_PREFIX - 1
74 *    + PPC_HAS_FPU              - 1
75 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
76 *                               - 0 otherwise
77 *    + PPC_USE_MULTIPLE         - 0
78 */
79 
80/*
81 *  Define the low power mode models
82 *
83 *  Standard:   as defined for 603e
84 *  Nap Mode:   nap mode only (604)
85 *  XXX 403GB, 603, 603e, 604, 821
86 */
87
88#define PPC_LOW_POWER_MODE_NONE      0
89#define PPC_LOW_POWER_MODE_STANDARD  1
90
91/*
92 *  Figure out all CPU Model Feature Flags based upon compiler
93 *  predefines.
94 */
95
96#if defined(ppc403) || defined(ppc405)
97/*
98 *  IBM 403
99 *
100 *  Developed for 403GA.  Book checked for 403GB.
101 *
102 *  Does not have user mode.
103 */
104 
105#if defined(ppc403)
106#define CPU_MODEL_NAME "PowerPC 403"
107#elif defined (ppc405)
108#define CPU_MODEL_NAME "PowerPC 405"
109#endif
110#define PPC_ALIGNMENT           4 
111#define PPC_CACHE_ALIGNMENT     16
112#define PPC_HAS_RFCI            1
113#define PPC_USE_MULTIPLE        1
114#define PPC_I_CACHE             2048
115#define PPC_D_CACHE             1024
116
117#define PPC_HAS_EXCEPTION_PREFIX 0
118#define PPC_HAS_EVPR             1
119
120#elif defined(mpc555)
121
122#define CPU_MODEL_NAME  "PowerPC 555"
123
124/* Copied from mpc505 */
125#define PPC_ALIGNMENT           4
126#define PPC_CACHE_ALIGNMENT     16
127
128/* Added by querbach@realtime.bc.ca */
129#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
130
131/* Based on comments by Sergei Organov <osv@Javad.RU> */
132#define PPC_I_CACHE             0
133#define PPC_D_CACHE             0
134
135#elif defined(mpc505) || defined(mpc509)
136/*
137 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
138 *  3.6.0 long after 4.0 was released.   This is just an attempt
139 *  to get the setting correct.
140 */
141
142#define CPU_MODEL_NAME  "PowerPC 505/509"
143
144#define PPC_ALIGNMENT           4
145#define PPC_CACHE_ALIGNMENT     16
146#define PPC_I_CACHE             4096
147#define PPC_D_CACHE             0
148
149
150#elif defined(ppc601)
151
152/*
153 *  Submitted with original port -- book checked only.
154 */
155 
156#define CPU_MODEL_NAME  "PowerPC 601"
157
158#define PPC_ALIGNMENT           8
159#define PPC_USE_MULTIPLE        1
160#define PPC_I_CACHE             0
161#define PPC_D_CACHE             32768
162
163#elif defined(ppc602)
164/*
165 *  Submitted with original port -- book checked only.
166 */
167 
168#define CPU_MODEL_NAME  "PowerPC 602"
169
170#define PPC_ALIGNMENT           4
171#define PPC_HAS_DOUBLE          0
172#define PPC_I_CACHE             4096
173#define PPC_D_CACHE             4096
174
175#elif defined(ppc603)
176/*
177 *  Submitted with original port -- book checked only.
178 */
179 
180#define CPU_MODEL_NAME  "PowerPC 603"
181
182#define PPC_ALIGNMENT           8
183#define PPC_I_CACHE             8192
184#define PPC_D_CACHE             8192
185
186#elif defined(ppc603e)
187 
188#define CPU_MODEL_NAME  "PowerPC 603e"
189/*
190 *  Submitted with original port.
191 *
192 *  Known to work on real hardware.
193 */
194
195#define PPC_ALIGNMENT           8
196#define PPC_I_CACHE             16384
197#define PPC_D_CACHE             16384
198
199#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
200
201#elif defined(mpc604)
202/*
203 *  Submitted with original port -- book checked only.
204 */
205 
206#define CPU_MODEL_NAME  "PowerPC 604"
207
208#define PPC_ALIGNMENT           8
209#define PPC_I_CACHE             16384
210#define PPC_D_CACHE             16384
211 
212#elif defined(mpc860)
213/*
214 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
215 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
216 */ 
217#define CPU_MODEL_NAME  "PowerPC MPC860"
218
219#define PPC_ALIGNMENT           4
220#define PPC_I_CACHE             4096
221#define PPC_D_CACHE             4096
222#define PPC_CACHE_ALIGNMENT     16
223#define PPC_INTERRUPT_MAX       71
224#define PPC_USE_MULTIPLE        1
225
226#define PPC_MSR_0               0x00009000
227#define PPC_MSR_1               0x00001000
228#define PPC_MSR_2               0x00001000
229#define PPC_MSR_3               0x00000000
230
231#elif defined(mpc821)
232/*
233 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
234 */ 
235#define CPU_MODEL_NAME  "PowerPC MPC821"
236
237#define PPC_ALIGNMENT           4
238#define PPC_I_CACHE             4096
239#define PPC_D_CACHE             4096
240#define PPC_CACHE_ALIGNMENT     16
241#define PPC_INTERRUPT_MAX       71
242
243#define PPC_MSR_0               0x00009000
244#define PPC_MSR_1               0x00001000
245#define PPC_MSR_2               0x00001000
246#define PPC_MSR_3               0x00000000
247
248#elif defined(mpc750)
249
250#define CPU_MODEL_NAME  "PowerPC 750"
251
252#define PPC_ALIGNMENT           8
253#define PPC_I_CACHE             16384
254#define PPC_D_CACHE             16384
255
256#elif defined(mpc7400)
257
258#define CPU_MODEL_NAME  "PowerPC 7400"
259
260#define PPC_ALIGNMENT           8
261#define PPC_I_CACHE             32768
262#define PPC_D_CACHE             32768
263
264#elif defined(mpc7455)
265/*
266 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
267 */
268
269#define CPU_MODEL_NAME  "PowerPC 7455"
270
271#define PPC_ALIGNMENT           8
272#define PPC_CACHE_ALIGNMENT     32
273#define PPC_I_CACHE             32768
274#define PPC_D_CACHE             32768
275
276#elif defined(mpc8260)
277/*
278 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
279 */
280#define CPU_MODEL_NAME  "PowerPC MPC8260"
281
282#define PPC_ALIGNMENT           4
283#define PPC_I_CACHE             16384
284#define PPC_D_CACHE             16384
285#define PPC_CACHE_ALIGNMENT     32
286#define PPC_INTERRUPT_MAX       125
287#define PPC_USE_MULTIPLE        1
288#else
289 
290#error "Unsupported CPU Model"
291 
292#endif
293
294/*
295 *  Application binary interfaces.
296 *
297 *  PPC_ABI MUST be defined as one of these.
298 *  Only big endian is currently supported.
299 */
300/*
301 *  SVR4 ABI
302 */
303#define PPC_ABI_SVR4            2
304/*
305 *  Embedded ABI
306 */
307#define PPC_ABI_EABI            3
308
309/*
310 *  Default to the EABI used by current GNU tools
311 */
312
313#ifndef PPC_ABI
314#define PPC_ABI PPC_ABI_EABI
315#endif
316
317#if (PPC_ABI == PPC_ABI_SVR4)
318#define PPC_STACK_ALIGNMENT     16
319#elif (PPC_ABI == PPC_ABI_EABI)
320#define PPC_STACK_ALIGNMENT     8
321#else
322#error  "PPC_ABI is not properly defined"
323#endif
324
325/*
326 *  Assemblers.
327 *  PPC_ASM MUST be defined as one of these.
328 *
329 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
330 *
331 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
332 */
333
334#define PPC_ASM_ELF   0
335
336/*
337 *  Default to the assembler format used by the current GNU tools.
338 */
339
340#ifndef PPC_ASM
341#define PPC_ASM PPC_ASM_ELF
342#endif
343
344/*
345 *  If the maximum number of exception sources has not been defined,
346 *  then default it to 16.
347 */
348
349#ifndef PPC_INTERRUPT_MAX
350#define PPC_INTERRUPT_MAX       16
351#endif
352
353/*
354 *  Unless specified otherwise, the cache line size is defaulted to 32.
355 *
356 *  The derive the power of 2 the cache line is.
357 */
358
359#ifndef PPC_CACHE_ALIGNMENT
360#define PPC_CACHE_ALIGNMENT 32
361#endif
362
363#if (PPC_CACHE_ALIGNMENT == 16)
364#define PPC_CACHE_ALIGN_POWER 4
365#elif (PPC_CACHE_ALIGNMENT == 32)
366#define PPC_CACHE_ALIGN_POWER 5
367#else
368#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
369#endif
370
371/*
372 *  Unless otherwise specified, assume the model has an IP/EP bit to
373 *  set the exception address prefix.
374 */
375
376#ifndef PPC_HAS_EXCEPTION_PREFIX
377#define PPC_HAS_EXCEPTION_PREFIX 1
378#endif
379
380/*
381 *  Unless otherwise specified, assume the model does NOT have
382 *  403 style EVPR register to set the exception address prefix.
383 */
384
385#ifndef PPC_HAS_EVPR
386#define PPC_HAS_EVPR 0
387#endif
388
389/*
390 *  If no low power mode model was specified, then assume there is none.
391 */
392
393#ifndef PPC_LOW_POWER_MODE
394#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
395#endif
396
397/*
398 *  Unless specified above, assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT.
399 *  FIXME: Should we tie PPC_HAS_FPU to _SOFT_FLOAT, directly
400 *     and disallow explicitly setting PPC_HAS_FPU?
401 */
402
403#ifndef PPC_HAS_FPU
404#ifdef _SOFT_FLOAT
405#define PPC_HAS_FPU 0
406#else
407#define PPC_HAS_FPU 1
408#endif
409#endif
410
411/*
412 *  Unless specified above, If the model has FP support, it is assumed to
413 *  support doubles (8-byte floating point numbers).
414 *
415 *  If the model does NOT have FP support, then the model does
416 *  NOT have double length FP registers.
417 */
418
419#ifndef PPC_HAS_DOUBLE
420#if (PPC_HAS_FPU)
421#define PPC_HAS_DOUBLE 1
422#else
423#define PPC_HAS_DOUBLE 0
424#endif
425#endif
426
427/*
428 *  Unless specified above, then assume the model does NOT have critical
429 *  interrupt support.
430 */
431
432#ifndef PPC_HAS_RFCI
433#define PPC_HAS_RFCI 0
434#endif
435
436/*
437 *  Unless specified above, do not use the load/store multiple instructions
438 *  in a context switch.
439 */
440
441#ifndef PPC_USE_MULTIPLE
442#define PPC_USE_MULTIPLE 0
443#endif
444
445/*
446 *  The following exceptions are not maskable, and are not
447 *  necessarily predictable, so cannot be offered to RTEMS:
448 *    Alignment exception - handled by the CPU module
449 *    Data exceptions.
450 *    Instruction exceptions.
451 */
452
453/*
454 *  Base Interrupt vectors supported on all models.
455 */
456#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
457#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
458#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
459#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
460#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
461#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
462#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
463#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
464#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
465#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
466#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
467#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
468#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
469#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
470#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
471
472#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
473
474#if defined(ppc403) || defined(ppc405)
475                                 
476#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
477#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
478#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
479#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
480#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
481#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
482
483#elif defined(mpc505) || defined(mpc509)
484#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
485#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
486#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
487#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
488#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
489
490#elif defined(mpc555)
491#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
492#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
493#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
494#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
495#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
496#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
497#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
498#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
499
500#elif defined(ppc601)
501#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
502#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
503
504#elif defined(ppc602)
505#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
506
507#elif defined(ppc603)
508#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
509#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
510#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
511#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
512#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
513#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
514
515#elif defined(ppc603e)
516#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
517#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
518#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
519#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
520#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
521#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
522
523
524#elif defined(mpc604)
525#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
526#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
527#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
528
529#elif defined(mpc860) || defined(mpc821)
530#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
531#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
532#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
533#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
534#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
535#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
536#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
537#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
538#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
539#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
540#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
541#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
542#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
543#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
544#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
545#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
546#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
547#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
548#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
549#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
550#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
551#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
552#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
553#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
554#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
555#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
556#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
557#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
558#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
559#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
560#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
561#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
562#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
563#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
564#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
565#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
566#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
567#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
568#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
569#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
570#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
571#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
572#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
573#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
574#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
575#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
576#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
577#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
578#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
579#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
580#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
581#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
582#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
583#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
584#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
585#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
586#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
587
588#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
589
590#elif defined(mpc8260)
591
592#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
593#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
594#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
595#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
596#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
597#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
598/* 0x1600 - 0x2F00 reserved */
599#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
600#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
601#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
602#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
603#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
604#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
605#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
606#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
607#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
608#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
609#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
610#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
611#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
612#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
613#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
614#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
615#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
616#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
617#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
618#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
619#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
620#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
621#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
622#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
623#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
624#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
625#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
626#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
627#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
628#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
629#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
630#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
631#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
632#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
633#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
634#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
635#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
636#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
637#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
638#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
639#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
640#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
641#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
642#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
643#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
644#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
645#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
646#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
647#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
648#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
649#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
650#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
651#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
652#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
653#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
654#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
655#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
656#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
657#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
658#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
659#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
660#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
661#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
662#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
663
664#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
665
666#endif
667
668
669/*
670 *  If the maximum number of exception sources is too low,
671 *  then fix it
672 */
673
674#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
675#undef PPC_INTERRUPT_MAX
676#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
677#endif
678
679/*
680 *  Machine Status Register (MSR) Constants Used by RTEMS
681 */
682
683/*
684 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
685 *  IP for no apparent reason.
686 */
687
688#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
689#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
690#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
691
692#if (PPC_HAS_EXCEPTION_PREFIX)
693#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
694#else
695#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
696#endif
697
698#if (PPC_HAS_FPU)
699#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
700#else
701#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
702#endif
703
704#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
705#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
706#else
707#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
708#endif
709
710#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
711#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
712
713#if (PPC_HAS_RFCI)
714#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
715#else
716#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
717#endif
718
719#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
720
721/*
722 *  Initial value for the FPSCR register
723 */
724
725#define PPC_INIT_FPSCR          0x000000f8
726
727#ifdef __cplusplus
728}
729#endif
730
731#endif /* _RTEMS_SCORE_POWERPC_H */
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