source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpusmplock.h @ ffbeb6f

4.115
Last change on this file since ffbeb6f was ffbeb6f, checked in by Sebastian Huber <sebastian.huber@…>, on 01/18/13 at 08:42:49

smp: Add PowerPC support

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreSMPLockPowerPC
5 *
6 * @brief PowerPC SMP Lock Implementation
7 */
8
9/*
10 * Copyright (c) 2013 embedded brains GmbH
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef _RTEMS_SCORE_POWERPC_SMPLOCK_H
18#define _RTEMS_SCORE_POWERPC_SMPLOCK_H
19
20#include <rtems/score/cpu.h>
21
22#ifdef __cplusplus
23extern "C" {
24#endif /* __cplusplus */
25
26/**
27 * @defgroup ScoreSMPLockPowerPC PowerPC SMP Locks
28 *
29 * @ingroup ScoreSMPLock
30 *
31 * A ticket lock implementation is used.
32 *
33 * @{
34 */
35
36typedef struct {
37  uint32_t next_ticket;
38  uint32_t now_serving;
39} CPU_SMP_lock_Control;
40
41#define CPU_SMP_LOCK_INITIALIZER { 0, 0 }
42
43static inline void _CPU_SMP_lock_Initialize( CPU_SMP_lock_Control *lock )
44{
45  lock->next_ticket = 0;
46  lock->now_serving = 0;
47}
48
49static inline void _CPU_SMP_lock_Acquire( CPU_SMP_lock_Control *lock )
50{
51  uint32_t my_ticket;
52  uint32_t next_ticket;
53
54  __asm__ volatile (
55    "1: lwarx %[my_ticket], 0, %[next_ticket_addr]\n"
56    "addi %[next_ticket], %[my_ticket], 1\n"
57    "stwcx. %[next_ticket], 0, [%[next_ticket_addr]]\n"
58    "bne 1b\n"
59    "isync"
60    : [my_ticket] "=&r" (my_ticket),
61      [next_ticket] "=&r" (next_ticket)
62    : [next_ticket_addr] "r" (&lock->next_ticket)
63    : "cc", "memory"
64  );
65
66  while ( my_ticket != lock->now_serving ) {
67    __asm__ volatile ( "" : : : "memory" );
68  }
69}
70
71static inline void _CPU_SMP_lock_Release( CPU_SMP_lock_Control *lock )
72{
73  __asm__ volatile ( "msync" : : : "memory" );
74  ++lock->now_serving;
75}
76
77#define _CPU_SMP_lock_ISR_disable_and_acquire( lock, isr_cookie ) \
78  do { \
79    _CPU_ISR_Disable( isr_cookie ); \
80    _CPU_SMP_lock_Acquire( lock ); \
81  } while (0)
82
83#define _CPU_SMP_lock_Release_and_ISR_enable( lock, isr_cookie ) \
84  do { \
85    _CPU_SMP_lock_Release( lock ); \
86    _CPU_ISR_Enable( isr_cookie ); \
87  } while (0)
88
89/**@}*/
90
91#ifdef __cplusplus
92}
93#endif /* __cplusplus */
94
95#endif /* _RTEMS_SCORE_POWERPC_SMPLOCK_H */
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