[df63fbd1] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief CPU Port Implementation API |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[2599c8e] | 8 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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| 9 | * Canon Centre Recherche France. |
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| 10 | * |
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| 11 | * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> |
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| 12 | * |
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[a6f84b27] | 13 | * Copyright (c) 2009, 2017 embedded brains GmbH |
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[38a1449] | 14 | * |
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[df63fbd1] | 15 | * The license and distribution terms for this file may be |
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| 16 | * found in the file LICENSE in this distribution or at |
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| 17 | * http://www.rtems.org/license/LICENSE. |
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| 18 | */ |
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| 19 | |
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| 20 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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| 21 | #define _RTEMS_SCORE_CPUIMPL_H |
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| 22 | |
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| 23 | #include <rtems/score/cpu.h> |
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| 24 | |
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[a6f84b27] | 25 | /* Exception stack frame -> BSP_Exception_frame */ |
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| 26 | #ifdef __powerpc64__ |
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| 27 | #define FRAME_LINK_SPACE 32 |
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| 28 | #else |
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| 29 | #define FRAME_LINK_SPACE 8 |
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| 30 | #endif |
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| 31 | |
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| 32 | #define SRR0_FRAME_OFFSET FRAME_LINK_SPACE |
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| 33 | #define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE) |
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| 34 | #define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE) |
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| 35 | #define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4) |
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| 36 | #define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8) |
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| 37 | #define EXC_XER_OFFSET (EXC_CR_OFFSET + 4) |
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| 38 | #define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4) |
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| 39 | #define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE) |
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| 40 | #define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE) |
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| 41 | |
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| 42 | #ifndef __SPE__ |
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| 43 | #define PPC_EXC_GPR_OFFSET(gpr) \ |
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| 44 | ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) |
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[5018894e] | 45 | #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3) |
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[a6f84b27] | 46 | #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) |
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| 47 | #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) |
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| 48 | #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) |
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| 49 | #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) |
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| 50 | #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32)) |
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| 51 | #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) |
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| 52 | #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) |
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| 53 | #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) |
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| 54 | #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) |
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| 55 | #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20)) |
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| 56 | #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) |
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| 57 | #define CPU_INTERRUPT_FRAME_SIZE \ |
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| 58 | (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) |
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| 59 | #elif defined(PPC_MULTILIB_ALTIVEC) |
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| 60 | #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) |
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| 61 | #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) |
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| 62 | #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) |
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| 63 | #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32) |
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| 64 | #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) |
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| 65 | #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) |
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| 66 | #define CPU_INTERRUPT_FRAME_SIZE \ |
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| 67 | (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE) |
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| 68 | #elif defined(PPC_MULTILIB_FPU) |
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| 69 | #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33)) |
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| 70 | #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) |
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| 71 | #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) |
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| 72 | #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13)) |
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| 73 | #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) |
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| 74 | #define CPU_INTERRUPT_FRAME_SIZE \ |
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| 75 | (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) |
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| 76 | #else |
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| 77 | #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33) |
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| 78 | #define CPU_INTERRUPT_FRAME_SIZE \ |
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| 79 | (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE) |
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| 80 | #endif |
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| 81 | #else |
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| 82 | #define PPC_EXC_SPEFSCR_OFFSET 44 |
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| 83 | #define PPC_EXC_ACC_OFFSET 48 |
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| 84 | #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) |
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[5018894e] | 85 | #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4) |
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[a6f84b27] | 86 | #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) |
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| 87 | #define PPC_EXC_FRAME_SIZE 320 |
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| 88 | #endif |
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| 89 | |
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[2599c8e] | 90 | #define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0) |
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| 91 | #define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1) |
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| 92 | #define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2) |
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| 93 | #define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3) |
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| 94 | #define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4) |
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| 95 | #define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5) |
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| 96 | #define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6) |
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| 97 | #define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7) |
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| 98 | #define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8) |
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| 99 | #define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9) |
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| 100 | #define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10) |
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| 101 | #define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11) |
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| 102 | #define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12) |
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| 103 | #define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13) |
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| 104 | #define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14) |
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| 105 | #define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15) |
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| 106 | #define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16) |
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| 107 | #define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17) |
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| 108 | #define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18) |
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| 109 | #define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19) |
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| 110 | #define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20) |
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| 111 | #define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21) |
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| 112 | #define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22) |
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| 113 | #define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23) |
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| 114 | #define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24) |
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| 115 | #define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25) |
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| 116 | #define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26) |
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| 117 | #define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27) |
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| 118 | #define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28) |
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| 119 | #define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29) |
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| 120 | #define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30) |
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| 121 | #define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31) |
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| 122 | |
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[82d30a3] | 123 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 124 | |
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[38a1449] | 125 | #ifdef RTEMS_SMP |
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| 126 | |
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| 127 | /* Use SPRG0 for the per-CPU control of the current processor */ |
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| 128 | #define PPC_PER_CPU_CONTROL_REGISTER 272 |
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| 129 | |
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| 130 | #endif /* RTEMS_SMP */ |
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| 131 | |
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[df63fbd1] | 132 | #ifndef ASM |
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| 133 | |
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| 134 | #ifdef __cplusplus |
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| 135 | extern "C" { |
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| 136 | #endif |
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| 137 | |
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[2599c8e] | 138 | typedef struct { |
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[a6f84b27] | 139 | uintptr_t FRAME_SP; |
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| 140 | #ifdef __powerpc64__ |
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| 141 | uint32_t FRAME_CR; |
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| 142 | uint32_t FRAME_RESERVED; |
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| 143 | #endif |
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| 144 | uintptr_t FRAME_LR; |
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| 145 | #ifdef __powerpc64__ |
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| 146 | uintptr_t FRAME_TOC; |
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| 147 | #endif |
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| 148 | uintptr_t EXC_SRR0; |
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| 149 | uintptr_t EXC_SRR1; |
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| 150 | uint32_t RESERVED_FOR_ALIGNMENT_0; |
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| 151 | uint32_t EXC_INTERRUPT_ENTRY_INSTANT; |
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[2599c8e] | 152 | uint32_t EXC_CR; |
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| 153 | uint32_t EXC_XER; |
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[a6f84b27] | 154 | uintptr_t EXC_CTR; |
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| 155 | uintptr_t EXC_LR; |
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| 156 | uintptr_t EXC_INTERRUPT_FRAME; |
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[2599c8e] | 157 | #ifdef __SPE__ |
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| 158 | uint32_t EXC_SPEFSCR; |
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| 159 | uint64_t EXC_ACC; |
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| 160 | #endif |
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| 161 | PPC_GPR_TYPE GPR0; |
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| 162 | PPC_GPR_TYPE GPR1; |
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| 163 | PPC_GPR_TYPE GPR2; |
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| 164 | PPC_GPR_TYPE GPR3; |
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| 165 | PPC_GPR_TYPE GPR4; |
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| 166 | PPC_GPR_TYPE GPR5; |
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| 167 | PPC_GPR_TYPE GPR6; |
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| 168 | PPC_GPR_TYPE GPR7; |
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| 169 | PPC_GPR_TYPE GPR8; |
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| 170 | PPC_GPR_TYPE GPR9; |
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| 171 | PPC_GPR_TYPE GPR10; |
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| 172 | PPC_GPR_TYPE GPR11; |
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| 173 | PPC_GPR_TYPE GPR12; |
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| 174 | #ifdef PPC_MULTILIB_ALTIVEC |
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| 175 | /* This field must take stvewx/lvewx requirements into account */ |
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[a6f84b27] | 176 | uint32_t RESERVED_FOR_ALIGNMENT_3[3]; |
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[2599c8e] | 177 | uint32_t VSCR; |
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| 178 | |
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[a6f84b27] | 179 | uint8_t V0[16]; |
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[2599c8e] | 180 | uint8_t V1[16]; |
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| 181 | uint8_t V2[16]; |
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| 182 | uint8_t V3[16]; |
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| 183 | uint8_t V4[16]; |
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| 184 | uint8_t V5[16]; |
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| 185 | uint8_t V6[16]; |
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| 186 | uint8_t V7[16]; |
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| 187 | uint8_t V8[16]; |
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| 188 | uint8_t V9[16]; |
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| 189 | uint8_t V10[16]; |
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| 190 | uint8_t V11[16]; |
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| 191 | uint8_t V12[16]; |
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| 192 | uint8_t V13[16]; |
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| 193 | uint8_t V14[16]; |
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| 194 | uint8_t V15[16]; |
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| 195 | uint8_t V16[16]; |
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| 196 | uint8_t V17[16]; |
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| 197 | uint8_t V18[16]; |
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| 198 | uint8_t V19[16]; |
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| 199 | #endif |
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| 200 | #ifdef PPC_MULTILIB_FPU |
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| 201 | double F0; |
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| 202 | double F1; |
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| 203 | double F2; |
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| 204 | double F3; |
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| 205 | double F4; |
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| 206 | double F5; |
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| 207 | double F6; |
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| 208 | double F7; |
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| 209 | double F8; |
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| 210 | double F9; |
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| 211 | double F10; |
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| 212 | double F11; |
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| 213 | double F12; |
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| 214 | double F13; |
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| 215 | uint64_t FPSCR; |
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[a6f84b27] | 216 | uint64_t RESERVED_FOR_ALIGNMENT_4; |
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[2599c8e] | 217 | #endif |
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[a6f84b27] | 218 | #if PPC_STACK_RED_ZONE_SIZE > 0 |
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| 219 | uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ]; |
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[585706a4] | 220 | #endif |
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[2599c8e] | 221 | } CPU_Interrupt_frame; |
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| 222 | |
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[38a1449] | 223 | #ifdef RTEMS_SMP |
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| 224 | |
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| 225 | static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void ) |
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| 226 | { |
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| 227 | struct Per_CPU_Control *cpu_self; |
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| 228 | |
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| 229 | __asm__ volatile ( |
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| 230 | "mfspr %0, " RTEMS_XSTRING( PPC_PER_CPU_CONTROL_REGISTER ) |
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| 231 | : "=r" ( cpu_self ) |
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| 232 | ); |
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| 233 | |
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| 234 | return cpu_self; |
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| 235 | } |
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| 236 | |
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| 237 | #define _CPU_Get_current_per_CPU_control() _PPC_Get_current_per_CPU_control() |
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| 238 | |
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| 239 | #endif /* RTEMS_SMP */ |
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| 240 | |
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[df63fbd1] | 241 | #ifdef __cplusplus |
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| 242 | } |
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| 243 | #endif |
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| 244 | |
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| 245 | #endif /* ASM */ |
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| 246 | |
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| 247 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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