source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ ffbeb6f

4.115
Last change on this file since ffbeb6f was ffbeb6f, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 18, 2013 at 8:42:49 AM

smp: Add PowerPC support

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1/**
2 * @file
3 *
4 * @brief PowerPC CPU Department Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  COPYRIGHT (c) 1995 i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
25 *
26 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
27 *
28 *  Copyright (c) 2010-2012 embedded brains GmbH.
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.rtems.com/license/LICENSE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#include <rtems/score/types.h>
39#include <rtems/score/powerpc.h>
40#include <rtems/powerpc/registers.h>
41
42#ifndef ASM
43  #include <string.h> /* for memset() */
44#endif
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/* conditional compilation parameters */
51
52/*
53 *  Should the calls to _Thread_Enable_dispatch be inlined?
54 *
55 *  If TRUE, then they are inlined.
56 *  If FALSE, then a subroutine call is made.
57 *
58 *  Basically this is an example of the classic trade-off of size
59 *  versus speed.  Inlining the call (TRUE) typically increases the
60 *  size of RTEMS while speeding up the enabling of dispatching.
61 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
62 *  only be 0 or 1 unless you are in an interrupt handler and that
63 *  interrupt handler invokes the executive.]  When not inlined
64 *  something calls _Thread_Enable_dispatch which in turns calls
65 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
66 *  one subroutine call is avoided entirely.]
67 */
68
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/*
72 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
73 *  be unrolled one time?  In unrolled each iteration of the loop examines
74 *  two "nodes" on the chain being searched.  Otherwise, only one node
75 *  is examined per iteration.
76 *
77 *  If TRUE, then the loops are unrolled.
78 *  If FALSE, then the loops are not unrolled.
79 *
80 *  The primary factor in making this decision is the cost of disabling
81 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 *  body of the loop.  On some CPUs, the flash is more expensive than
83 *  one iteration of the loop body.  In this case, it might be desirable
84 *  to unroll the loop.  It is important to note that on some CPUs, this
85 *  code is the longest interrupt disable period in RTEMS.  So it is
86 *  necessary to strike a balance when setting this parameter.
87 */
88
89#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
90
91/*
92 *  Does this port provide a CPU dependent IDLE task implementation?
93 *
94 *  If TRUE, then the routine _CPU_Thread_Idle_body
95 *  must be provided and is the default IDLE thread body instead of
96 *  _CPU_Thread_Idle_body.
97 *
98 *  If FALSE, then use the generic IDLE thread body if the BSP does
99 *  not provide one.
100 *
101 *  This is intended to allow for supporting processors which have
102 *  a low power or idle mode.  When the IDLE thread is executed, then
103 *  the CPU can be powered down.
104 *
105 *  The order of precedence for selecting the IDLE thread body is:
106 *
107 *    1.  BSP provided
108 *    2.  CPU dependent (if provided)
109 *    3.  generic (if no BSP and no CPU dependent)
110 */
111
112#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
113
114/*
115 *  Does the stack grow up (toward higher addresses) or down
116 *  (toward lower addresses)?
117 *
118 *  If TRUE, then the grows upward.
119 *  If FALSE, then the grows toward smaller addresses.
120 */
121
122#define CPU_STACK_GROWS_UP               FALSE
123
124/*
125 *  The following is the variable attribute used to force alignment
126 *  of critical RTEMS structures.  On some processors it may make
127 *  sense to have these aligned on tighter boundaries than
128 *  the minimum requirements of the compiler in order to have as
129 *  much of the critical data area as possible in a cache line.
130 *
131 *  The placement of this macro in the declaration of the variables
132 *  is based on the syntactically requirements of the GNU C
133 *  "__attribute__" extension.  For example with GNU C, use
134 *  the following to force a structures to a 32 byte boundary.
135 *
136 *      __attribute__ ((aligned (32)))
137 *
138 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
139 *         To benefit from using this, the data must be heavily
140 *         used so it will stay in the cache and used frequently enough
141 *         in the executive to justify turning this on.
142 */
143
144#define CPU_STRUCTURE_ALIGNMENT \
145  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
146
147#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
148
149/*
150 *  Define what is required to specify how the network to host conversion
151 *  routines are handled.
152 */
153
154#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
155#define CPU_BIG_ENDIAN                           TRUE
156#define CPU_LITTLE_ENDIAN                        FALSE
157#else
158#define CPU_BIG_ENDIAN                           FALSE
159#define CPU_LITTLE_ENDIAN                        TRUE
160#endif
161
162/*
163 *  Does the CPU have hardware floating point?
164 *
165 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
166 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
167 *
168 *  If there is a FP coprocessor such as the i387 or mc68881, then
169 *  the answer is TRUE.
170 *
171 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
172 *  It indicates whether or not this CPU model has FP support.  For
173 *  example, it would be possible to have an i386_nofp CPU model
174 *  which set this to false to indicate that you have an i386 without
175 *  an i387 and wish to leave floating point support out of RTEMS.
176 */
177
178#if ( PPC_HAS_FPU == 1 )
179#define CPU_HARDWARE_FP     TRUE
180#define CPU_SOFTWARE_FP     FALSE
181#else
182#define CPU_HARDWARE_FP     FALSE
183#define CPU_SOFTWARE_FP     FALSE
184#endif
185
186/*
187 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
188 *
189 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
190 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
191 *
192 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
193 *
194 *  PowerPC Note: It appears the GCC can implicitly generate FPU
195 *  and Altivec instructions when you least expect them.  So make
196 *  all tasks floating point.
197 */
198
199#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
200
201/*
202 *  Should the IDLE task have a floating point context?
203 *
204 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
205 *  and it has a floating point context which is switched in and out.
206 *  If FALSE, then the IDLE task does not have a floating point context.
207 *
208 *  Setting this to TRUE negatively impacts the time required to preempt
209 *  the IDLE task from an interrupt because the floating point context
210 *  must be saved as part of the preemption.
211 */
212
213#define CPU_IDLE_TASK_IS_FP      FALSE
214
215/*
216 *  Processor defined structures required for cpukit/score.
217 */
218
219/*
220 * Contexts
221 *
222 *  Generally there are 2 types of context to save.
223 *     1. Interrupt registers to save
224 *     2. Task level registers to save
225 *
226 *  This means we have the following 3 context items:
227 *     1. task level context stuff::  Context_Control
228 *     2. floating point task stuff:: Context_Control_fp
229 *     3. special interrupt level context :: Context_Control_interrupt
230 *
231 *  On some processors, it is cost-effective to save only the callee
232 *  preserved registers during a task context switch.  This means
233 *  that the ISR code needs to save those registers which do not
234 *  persist across function calls.  It is not mandatory to make this
235 *  distinctions between the caller/callee saves registers for the
236 *  purpose of minimizing context saved during task switch and on interrupts.
237 *  If the cost of saving extra registers is minimal, simplicity is the
238 *  choice.  Save the same context on interrupt entry as for tasks in
239 *  this case.
240 *
241 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
242 *  care should be used in designing the context area.
243 *
244 *  On some CPUs with hardware floating point support, the Context_Control_fp
245 *  structure will not be used or it simply consist of an array of a
246 *  fixed number of bytes.   This is done when the floating point context
247 *  is dumped by a "FP save context" type instruction and the format
248 *  is not really defined by the CPU.  In this case, there is no need
249 *  to figure out the exact format -- only the size.  Of course, although
250 *  this is enough information for RTEMS, it is probably not enough for
251 *  a debugger such as gdb.  But that is another problem.
252 */
253
254#ifndef __SPE__
255  #define PPC_GPR_TYPE uint32_t
256  #define PPC_GPR_SIZE 4
257  #define PPC_GPR_LOAD lwz
258  #define PPC_GPR_STORE stw
259#else
260  #define PPC_GPR_TYPE uint64_t
261  #define PPC_GPR_SIZE 8
262  #define PPC_GPR_LOAD evldd
263  #define PPC_GPR_STORE evstdd
264#endif
265
266#define PPC_DEFAULT_CACHE_LINE_SIZE 32
267
268#ifndef ASM
269
270/* Non-volatile context according to E500ABIUG and EABI */
271typedef struct {
272  uint32_t gpr1;
273  uint32_t msr;
274  uint32_t lr;
275  uint32_t cr;
276  PPC_GPR_TYPE gpr14;
277  PPC_GPR_TYPE gpr15;
278  PPC_GPR_TYPE gpr16;
279  PPC_GPR_TYPE gpr17;
280  PPC_GPR_TYPE gpr18;
281  PPC_GPR_TYPE gpr19;
282  PPC_GPR_TYPE gpr20;
283  PPC_GPR_TYPE gpr21;
284  PPC_GPR_TYPE gpr22;
285  PPC_GPR_TYPE gpr23;
286  PPC_GPR_TYPE gpr24;
287  PPC_GPR_TYPE gpr25;
288  PPC_GPR_TYPE gpr26;
289  PPC_GPR_TYPE gpr27;
290  PPC_GPR_TYPE gpr28;
291  PPC_GPR_TYPE gpr29;
292  PPC_GPR_TYPE gpr30;
293  PPC_GPR_TYPE gpr31;
294  #ifdef __ALTIVEC__
295    /*
296     * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
297     * and padding to ensure cache-alignment.  Unfortunately, we can't verify
298     * the cache line size here in the cpukit but altivec support code will
299     * produce an error if this is ever different from 32 bytes.
300     *
301     * Note: it is the BSP/CPU-support's responsibility to save/restore
302     *       volatile vregs across interrupts and exceptions.
303     */
304    uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
305  #endif
306} ppc_context;
307
308typedef struct {
309  uint8_t context [
310    PPC_DEFAULT_CACHE_LINE_SIZE
311      + sizeof(ppc_context)
312      + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
313        ? 0
314          : PPC_DEFAULT_CACHE_LINE_SIZE
315            - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
316  ];
317} Context_Control;
318
319static inline ppc_context *ppc_get_context( Context_Control *context )
320{
321  uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
322  uintptr_t mask = clsz - 1;
323  uintptr_t addr = (uintptr_t) context;
324
325  return (ppc_context *) ((addr & ~mask) + clsz);
326}
327
328#define _CPU_Context_Get_SP( _context ) \
329  ppc_get_context(_context)->gpr1
330#endif /* ASM */
331
332#define PPC_CONTEXT_OFFSET_GPR1 32
333#define PPC_CONTEXT_OFFSET_MSR 36
334#define PPC_CONTEXT_OFFSET_LR 40
335#define PPC_CONTEXT_OFFSET_CR 44
336
337#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
338  (((gpr) - 14) * PPC_GPR_SIZE + 48)
339
340#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
341#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
342#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
343#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
344#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
345#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
346#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
347#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
348#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
349#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
350#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
351#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
352#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
353#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
354#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
355#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
356#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
357#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
358
359#ifndef ASM
360typedef struct {
361    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
362     * procedure calls.  However, this would mean that the interrupt
363     * frame had to hold f0-f13, and the fpscr.  And as the majority
364     * of tasks will not have an FP context, we will save the whole
365     * context here.
366     */
367#if (PPC_HAS_DOUBLE == 1)
368    double      f[32];
369    uint64_t    fpscr;
370#else
371    float       f[32];
372    uint32_t    fpscr;
373#endif
374} Context_Control_fp;
375
376typedef struct CPU_Interrupt_frame {
377    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
378    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
379
380    /* This is what is left out of the primary contexts */
381    uint32_t   gpr0;
382    uint32_t   gpr2;            /* play safe */
383    uint32_t   gpr3;
384    uint32_t   gpr4;
385    uint32_t   gpr5;
386    uint32_t   gpr6;
387    uint32_t   gpr7;
388    uint32_t   gpr8;
389    uint32_t   gpr9;
390    uint32_t   gpr10;
391    uint32_t   gpr11;
392    uint32_t   gpr12;
393    uint32_t   gpr13;   /* Play safe */
394    uint32_t   gpr28;   /* For internal use by the IRQ handler */
395    uint32_t   gpr29;   /* For internal use by the IRQ handler */
396    uint32_t   gpr30;   /* For internal use by the IRQ handler */
397    uint32_t   gpr31;   /* For internal use by the IRQ handler */
398    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
399    uint32_t   ctr;
400    uint32_t   xer;
401    uint32_t   lr;
402    uint32_t   pc;
403    uint32_t   msr;
404    uint32_t   pad[3];
405} CPU_Interrupt_frame;
406
407#endif /* ASM */
408
409/*
410 *  Does the CPU follow the simple vectored interrupt model?
411 *
412 *  If TRUE, then RTEMS allocates the vector table it internally manages.
413 *  If FALSE, then the BSP is assumed to allocate and manage the vector
414 *  table
415 *
416 *  PowerPC Specific Information:
417 *
418 *  The PowerPC and x86 were the first to use the PIC interrupt model.
419 *  They do not use the simple vectored interrupt model.
420 */
421#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
422
423/*
424 *  Does RTEMS manage a dedicated interrupt stack in software?
425 *
426 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
427 *  If FALSE, nothing is done.
428 *
429 *  If the CPU supports a dedicated interrupt stack in hardware,
430 *  then it is generally the responsibility of the BSP to allocate it
431 *  and set it up.
432 *
433 *  If the CPU does not support a dedicated interrupt stack, then
434 *  the porter has two options: (1) execute interrupts on the
435 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
436 *  interrupt stack.
437 *
438 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
439 *
440 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
441 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
442 *  possible that both are FALSE for a particular CPU.  Although it
443 *  is unclear what that would imply about the interrupt processing
444 *  procedure on that CPU.
445 */
446
447#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
448
449/*
450 *  Does this CPU have hardware support for a dedicated interrupt stack?
451 *
452 *  If TRUE, then it must be installed during initialization.
453 *  If FALSE, then no installation is performed.
454 *
455 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
456 *
457 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
458 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
459 *  possible that both are FALSE for a particular CPU.  Although it
460 *  is unclear what that would imply about the interrupt processing
461 *  procedure on that CPU.
462 */
463
464#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
465
466/*
467 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
468 *
469 *  If TRUE, then the memory is allocated during initialization.
470 *  If FALSE, then the memory is allocated during initialization.
471 *
472 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
473 */
474
475#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
476
477/*
478 *  Does the RTEMS invoke the user's ISR with the vector number and
479 *  a pointer to the saved interrupt frame (1) or just the vector
480 *  number (0)?
481 */
482
483#define CPU_ISR_PASSES_FRAME_POINTER 0
484
485/*
486 *  Should the saving of the floating point registers be deferred
487 *  until a context switch is made to another different floating point
488 *  task?
489 *
490 *  If TRUE, then the floating point context will not be stored until
491 *  necessary.  It will remain in the floating point registers and not
492 *  disturned until another floating point task is switched to.
493 *
494 *  If FALSE, then the floating point context is saved when a floating
495 *  point task is switched out and restored when the next floating point
496 *  task is restored.  The state of the floating point registers between
497 *  those two operations is not specified.
498 *
499 *  If the floating point context does NOT have to be saved as part of
500 *  interrupt dispatching, then it should be safe to set this to TRUE.
501 *
502 *  Setting this flag to TRUE results in using a different algorithm
503 *  for deciding when to save and restore the floating point context.
504 *  The deferred FP switch algorithm minimizes the number of times
505 *  the FP context is saved and restored.  The FP context is not saved
506 *  until a context switch is made to another, different FP task.
507 *  Thus in a system with only one FP task, the FP context will never
508 *  be saved or restored.
509 *
510 *  Note, however that compilers may use floating point registers/
511 *  instructions for optimization or they may save/restore FP registers
512 *  on the stack. You must not use deferred switching in these cases
513 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
514 *  exception.
515 */
516/*
517 *  ACB Note:  This could make debugging tricky..
518 */
519
520/* conservative setting (FALSE); probably doesn't affect performance too much */
521#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
522
523/*
524 *  Processor defined structures required for cpukit/score.
525 */
526
527#ifndef ASM
528
529/*
530 *  This variable is optional.  It is used on CPUs on which it is difficult
531 *  to generate an "uninitialized" FP context.  It is filled in by
532 *  _CPU_Initialize and copied into the task's FP context area during
533 *  _CPU_Context_Initialize.
534 */
535
536/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
537
538#endif /* ndef ASM */
539
540/*
541 *  This defines the number of levels and the mask used to pick those
542 *  bits out of a thread mode.
543 */
544
545#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
546#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
547
548/*
549 *  Nothing prevents the porter from declaring more CPU specific variables.
550 */
551
552#ifndef ASM
553
554SCORE_EXTERN struct {
555  uint32_t      *Disable_level;
556  void          *Stack;
557  volatile bool *Switch_necessary;
558  bool          *Signal;
559
560} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
561
562#endif /* ndef ASM */
563
564/*
565 *  The size of the floating point context area.  On some CPUs this
566 *  will not be a "sizeof" because the format of the floating point
567 *  area is not defined -- only the size is.  This is usually on
568 *  CPUs with a "floating point save context" instruction.
569 */
570
571#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
572
573/*
574 * (Optional) # of bytes for libmisc/stackchk to check
575 * If not specifed, then it defaults to something reasonable
576 * for most architectures.
577 */
578
579#define CPU_STACK_CHECK_SIZE    (128)
580
581/*
582 *  Amount of extra stack (above minimum stack size) required by
583 *  MPCI receive server thread.  Remember that in a multiprocessor
584 *  system this thread must exist and be able to process all directives.
585 */
586
587#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
588
589/*
590 *  This defines the number of entries in the ISR_Vector_table managed
591 *  by RTEMS.
592 *
593 *  NOTE: CPU_INTERRUPT_NUMBER_OF_VECTORS and
594 *        CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER are only used on
595 *        Simple Vectored Architectures and thus are not defined
596 *        for this architecture.
597 */
598
599/*
600 *  This is defined if the port has a special way to report the ISR nesting
601 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
602 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
603 *  being maintained (e.g. watchdog queues).
604 */
605
606#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
607
608/*
609 *  ISR handler macros
610 */
611
612/*
613 *  Disable all interrupts for an RTEMS critical section.  The previous
614 *  level is returned in _isr_cookie.
615 */
616
617#ifndef ASM
618
619static inline uint32_t   _CPU_ISR_Get_level( void )
620{
621  register unsigned int msr;
622  _CPU_MSR_GET(msr);
623  if (msr & MSR_EE) return 0;
624  else  return 1;
625}
626
627static inline void _CPU_ISR_Set_level( uint32_t   level )
628{
629  register unsigned int msr;
630  _CPU_MSR_GET(msr);
631  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
632    msr |= ppc_interrupt_get_disable_mask();
633  }
634  else {
635    msr &= ~ppc_interrupt_get_disable_mask();
636  }
637  _CPU_MSR_SET(msr);
638}
639
640void BSP_panic(char *);
641
642/* Fatal Error manager macros */
643
644/*
645 *  This routine copies _error into a known place -- typically a stack
646 *  location or a register, optionally disables interrupts, and
647 *  halts/stops the CPU.
648 */
649
650void _BSP_Fatal_error(unsigned int);
651
652#endif /* ASM */
653
654#define _CPU_Fatal_halt( _error ) \
655  _BSP_Fatal_error(_error)
656
657/* end of Fatal Error manager macros */
658
659/*
660 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
661 * Now SPRG0 is devoted to the interrupt disable mask.
662 */
663
664#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
665
666/*
667 *  Should be large enough to run all RTEMS tests.  This ensures
668 *  that a "reasonable" small application should not have any problems.
669 */
670
671#define CPU_STACK_MINIMUM_SIZE          (1024*8)
672
673#define CPU_SIZEOF_POINTER 4
674
675/*
676 *  CPU's worst alignment requirement for data types on a byte boundary.  This
677 *  alignment does not take into account the requirements for the stack.
678 */
679
680#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
681
682/*
683 *  This number corresponds to the byte alignment requirement for the
684 *  heap handler.  This alignment requirement may be stricter than that
685 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
686 *  common for the heap to follow the same alignment requirement as
687 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
688 *  then this should be set to CPU_ALIGNMENT.
689 *
690 *  NOTE:  This does not have to be a power of 2.  It does have to
691 *         be greater or equal to than CPU_ALIGNMENT.
692 */
693
694#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
695
696/*
697 *  This number corresponds to the byte alignment requirement for memory
698 *  buffers allocated by the partition manager.  This alignment requirement
699 *  may be stricter than that for the data types alignment specified by
700 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
701 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
702 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
703 *
704 *  NOTE:  This does not have to be a power of 2.  It does have to
705 *         be greater or equal to than CPU_ALIGNMENT.
706 */
707
708#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
709
710/*
711 *  This number corresponds to the byte alignment requirement for the
712 *  stack.  This alignment requirement may be stricter than that for the
713 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
714 *  is strict enough for the stack, then this should be set to 0.
715 *
716 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
717 */
718
719#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
720
721#ifndef ASM
722/*  The following routine swaps the endian format of an unsigned int.
723 *  It must be static because it is referenced indirectly.
724 *
725 *  This version will work on any processor, but if there is a better
726 *  way for your CPU PLEASE use it.  The most common way to do this is to:
727 *
728 *     swap least significant two bytes with 16-bit rotate
729 *     swap upper and lower 16-bits
730 *     swap most significant two bytes with 16-bit rotate
731 *
732 *  Some CPUs have special instructions which swap a 32-bit quantity in
733 *  a single instruction (e.g. i486).  It is probably best to avoid
734 *  an "endian swapping control bit" in the CPU.  One good reason is
735 *  that interrupts would probably have to be disabled to ensure that
736 *  an interrupt does not try to access the same "chunk" with the wrong
737 *  endian.  Another good reason is that on some CPUs, the endian bit
738 *  endianness for ALL fetches -- both code and data -- so the code
739 *  will be fetched incorrectly.
740 */
741
742static inline uint32_t CPU_swap_u32(
743  uint32_t value
744)
745{
746  uint32_t   swapped;
747
748  __asm__ volatile("rlwimi %0,%1,8,24,31;"
749               "rlwimi %0,%1,24,16,23;"
750               "rlwimi %0,%1,8,8,15;"
751               "rlwimi %0,%1,24,0,7;" :
752               "=&r" ((swapped)) : "r" ((value)));
753
754  return( swapped );
755}
756
757#define CPU_swap_u16( value ) \
758  (((value&0xff) << 8) | ((value >> 8)&0xff))
759
760#endif /* ASM */
761
762
763#ifndef ASM
764/* Context handler macros */
765
766/*
767 *  Initialize the context to a state suitable for starting a
768 *  task after a context restore operation.  Generally, this
769 *  involves:
770 *
771 *     - setting a starting address
772 *     - preparing the stack
773 *     - preparing the stack and frame pointers
774 *     - setting the proper interrupt level in the context
775 *     - initializing the floating point context
776 *
777 *  This routine generally does not set any unnecessary register
778 *  in the context.  The state of the "general data" registers is
779 *  undefined at task start time.
780 */
781
782void _CPU_Context_Initialize(
783  Context_Control  *the_context,
784  uint32_t         *stack_base,
785  uint32_t          size,
786  uint32_t          new_level,
787  void             *entry_point,
788  bool              is_fp
789);
790
791/*
792 *  This routine is responsible for somehow restarting the currently
793 *  executing task.  If you are lucky, then all that is necessary
794 *  is restoring the context.  Otherwise, there will need to be
795 *  a special assembly routine which does something special in this
796 *  case.  Context_Restore should work most of the time.  It will
797 *  not work if restarting self conflicts with the stack frame
798 *  assumptions of restoring a context.
799 */
800
801#define _CPU_Context_Restart_self( _the_context ) \
802   _CPU_Context_restore( (_the_context) );
803
804/*
805 *  The purpose of this macro is to allow the initial pointer into
806 *  a floating point context area (used to save the floating point
807 *  context) to be at an arbitrary place in the floating point
808 *  context area.
809 *
810 *  This is necessary because some FP units are designed to have
811 *  their context saved as a stack which grows into lower addresses.
812 *  Other FP units can be saved by simply moving registers into offsets
813 *  from the base of the context area.  Finally some FP units provide
814 *  a "dump context" instruction which could fill in from high to low
815 *  or low to high based on the whim of the CPU designers.
816 */
817
818#define _CPU_Context_Fp_start( _base, _offset ) \
819   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
820
821/*
822 *  This routine initializes the FP context area passed to it to.
823 *  There are a few standard ways in which to initialize the
824 *  floating point context.  The code included for this macro assumes
825 *  that this is a CPU in which a "initial" FP context was saved into
826 *  _CPU_Null_fp_context and it simply copies it to the destination
827 *  context passed to it.
828 *
829 *  Other models include (1) not doing anything, and (2) putting
830 *  a "null FP status word" in the correct place in the FP context.
831 */
832
833#define _CPU_Context_Initialize_fp( _destination ) \
834  memset( *(_destination), 0, sizeof( **(_destination) ) )
835
836/* end of Context handler macros */
837#endif /* ASM */
838
839#ifndef ASM
840/* Bitfield handler macros */
841
842/*
843 *  This routine sets _output to the bit number of the first bit
844 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
845 *  This type may be either 16 or 32 bits wide although only the 16
846 *  least significant bits will be used.
847 *
848 *  There are a number of variables in using a "find first bit" type
849 *  instruction.
850 *
851 *    (1) What happens when run on a value of zero?
852 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
853 *    (3) The numbering may be zero or one based.
854 *    (4) The "find first bit" instruction may search from MSB or LSB.
855 *
856 *  RTEMS guarantees that (1) will never happen so it is not a concern.
857 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
858 *  _CPU_Priority_Bits_index().  These three form a set of routines
859 *  which must logically operate together.  Bits in the _value are
860 *  set and cleared based on masks built by _CPU_Priority_mask().
861 *  The basic major and minor values calculated by _Priority_Major()
862 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
863 *  to properly range between the values returned by the "find first bit"
864 *  instruction.  This makes it possible for _Priority_Get_highest() to
865 *  calculate the major and directly index into the minor table.
866 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
867 *  is the first bit found.
868 *
869 *  This entire "find first bit" and mapping process depends heavily
870 *  on the manner in which a priority is broken into a major and minor
871 *  components with the major being the 4 MSB of a priority and minor
872 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
873 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
874 *  to the lowest priority.
875 *
876 *  If your CPU does not have a "find first bit" instruction, then
877 *  there are ways to make do without it.  Here are a handful of ways
878 *  to implement this in software:
879 *
880 *    - a series of 16 bit test instructions
881 *    - a "binary search using if's"
882 *    - _number = 0
883 *      if _value > 0x00ff
884 *        _value >>=8
885 *        _number = 8;
886 *
887 *      if _value > 0x0000f
888 *        _value >=8
889 *        _number += 4
890 *
891 *      _number += bit_set_table[ _value ]
892 *
893 *    where bit_set_table[ 16 ] has values which indicate the first
894 *      bit set
895 */
896
897#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
898  { \
899    __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
900                  "1" ((_value))); \
901  }
902
903/* end of Bitfield handler macros */
904
905/*
906 *  This routine builds the mask which corresponds to the bit fields
907 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
908 *  for that routine.
909 */
910
911#define _CPU_Priority_Mask( _bit_number ) \
912  ( 0x80000000 >> (_bit_number) )
913
914/*
915 *  This routine translates the bit numbers returned by
916 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
917 *  a major or minor component of a priority.  See the discussion
918 *  for that routine.
919 */
920
921#define _CPU_Priority_bits_index( _priority ) \
922  (_priority)
923
924/* end of Priority handler macros */
925#endif /* ASM */
926
927/* functions */
928
929#ifndef ASM
930
931/*
932 *  _CPU_Initialize
933 *
934 *  This routine performs CPU dependent initialization.
935 */
936
937void _CPU_Initialize(void);
938
939/*
940 *  _CPU_ISR_install_vector
941 *
942 *  This routine installs an interrupt vector.
943 */
944
945void _CPU_ISR_install_vector(
946  uint32_t    vector,
947  proc_ptr    new_handler,
948  proc_ptr   *old_handler
949);
950
951/*
952 *  _CPU_Context_switch
953 *
954 *  This routine switches from the run context to the heir context.
955 */
956
957void _CPU_Context_switch(
958  Context_Control  *run,
959  Context_Control  *heir
960);
961
962/*
963 *  _CPU_Context_restore
964 *
965 *  This routine is generallu used only to restart self in an
966 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
967 *
968 *  NOTE: May be unnecessary to reload some registers.
969 */
970
971void _CPU_Context_restore(
972  Context_Control *new_context
973) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
974
975/*
976 *  _CPU_Context_save_fp
977 *
978 *  This routine saves the floating point context passed to it.
979 */
980
981void _CPU_Context_save_fp(
982  Context_Control_fp **fp_context_ptr
983);
984
985/*
986 *  _CPU_Context_restore_fp
987 *
988 *  This routine restores the floating point context passed to it.
989 */
990
991void _CPU_Context_restore_fp(
992  Context_Control_fp **fp_context_ptr
993);
994
995void _CPU_Context_volatile_clobber( uintptr_t pattern );
996
997void _CPU_Context_validate( uintptr_t pattern );
998
999#ifdef RTEMS_SMP
1000  #define _CPU_Context_switch_to_first_task_smp( _context ) \
1001    _CPU_Context_restore( _context )
1002
1003  static inline void _CPU_Processor_event_broadcast( void )
1004  {
1005    __asm__ volatile ( "" : : : "memory" );
1006  }
1007
1008  static inline void _CPU_Processor_event_receive( void )
1009  {
1010    __asm__ volatile ( "" : : : "memory" );
1011  }
1012#endif
1013
1014typedef struct {
1015  uint32_t EXC_SRR0;
1016  uint32_t EXC_SRR1;
1017  uint32_t _EXC_number;
1018  uint32_t EXC_CR;
1019  uint32_t EXC_CTR;
1020  uint32_t EXC_XER;
1021  uint32_t EXC_LR;
1022  #ifdef __SPE__
1023    uint32_t EXC_SPEFSCR;
1024    uint64_t EXC_ACC;
1025  #endif
1026  PPC_GPR_TYPE GPR0;
1027  PPC_GPR_TYPE GPR1;
1028  PPC_GPR_TYPE GPR2;
1029  PPC_GPR_TYPE GPR3;
1030  PPC_GPR_TYPE GPR4;
1031  PPC_GPR_TYPE GPR5;
1032  PPC_GPR_TYPE GPR6;
1033  PPC_GPR_TYPE GPR7;
1034  PPC_GPR_TYPE GPR8;
1035  PPC_GPR_TYPE GPR9;
1036  PPC_GPR_TYPE GPR10;
1037  PPC_GPR_TYPE GPR11;
1038  PPC_GPR_TYPE GPR12;
1039  PPC_GPR_TYPE GPR13;
1040  PPC_GPR_TYPE GPR14;
1041  PPC_GPR_TYPE GPR15;
1042  PPC_GPR_TYPE GPR16;
1043  PPC_GPR_TYPE GPR17;
1044  PPC_GPR_TYPE GPR18;
1045  PPC_GPR_TYPE GPR19;
1046  PPC_GPR_TYPE GPR20;
1047  PPC_GPR_TYPE GPR21;
1048  PPC_GPR_TYPE GPR22;
1049  PPC_GPR_TYPE GPR23;
1050  PPC_GPR_TYPE GPR24;
1051  PPC_GPR_TYPE GPR25;
1052  PPC_GPR_TYPE GPR26;
1053  PPC_GPR_TYPE GPR27;
1054  PPC_GPR_TYPE GPR28;
1055  PPC_GPR_TYPE GPR29;
1056  PPC_GPR_TYPE GPR30;
1057  PPC_GPR_TYPE GPR31;
1058} CPU_Exception_frame;
1059
1060void _BSP_Exception_frame_print( const CPU_Exception_frame *frame );
1061
1062static inline void _CPU_Exception_frame_print(
1063  const CPU_Exception_frame *frame
1064)
1065{
1066  _BSP_Exception_frame_print( frame );
1067}
1068
1069/*
1070 * _CPU_Initialize_altivec()
1071 *
1072 * Global altivec-related initialization.
1073 */
1074void
1075_CPU_Initialize_altivec(void);
1076
1077/*
1078 * _CPU_Context_switch_altivec
1079 *
1080 * This routine switches the altivec contexts passed to it.
1081 */
1082
1083void
1084_CPU_Context_switch_altivec(
1085  Context_Control *from,
1086  Context_Control *to
1087);
1088
1089/*
1090 * _CPU_Context_restore_altivec
1091 *
1092 * This routine restores the altivec context passed to it.
1093 */
1094
1095void
1096_CPU_Context_restore_altivec(
1097  Context_Control *ctxt
1098);
1099
1100/*
1101 * _CPU_Context_initialize_altivec
1102 *
1103 * This routine initializes the altivec context passed to it.
1104 */
1105
1106void
1107_CPU_Context_initialize_altivec(
1108  Context_Control *ctxt
1109);
1110
1111void _CPU_Fatal_error(
1112  uint32_t   _error
1113);
1114
1115#endif /* ASM */
1116
1117#ifdef __cplusplus
1118}
1119#endif
1120
1121#endif /* _RTEMS_SCORE_CPU_H */
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