source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 35.3 KB
Line 
1/**
2 * @file
3 *
4 * @brief PowerPC CPU Department Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  COPYRIGHT (c) 1995 i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
25 *
26 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
27 *
28 *  Copyright (c) 2010-2013 embedded brains GmbH.
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.rtems.org/license/LICENSE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#include <rtems/score/types.h>
39#include <rtems/score/powerpc.h>
40#include <rtems/powerpc/registers.h>
41
42#ifndef ASM
43  #include <string.h> /* for memset() */
44#endif
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/* conditional compilation parameters */
51
52/*
53 *  Should the calls to _Thread_Enable_dispatch be inlined?
54 *
55 *  If TRUE, then they are inlined.
56 *  If FALSE, then a subroutine call is made.
57 *
58 *  Basically this is an example of the classic trade-off of size
59 *  versus speed.  Inlining the call (TRUE) typically increases the
60 *  size of RTEMS while speeding up the enabling of dispatching.
61 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
62 *  only be 0 or 1 unless you are in an interrupt handler and that
63 *  interrupt handler invokes the executive.]  When not inlined
64 *  something calls _Thread_Enable_dispatch which in turns calls
65 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
66 *  one subroutine call is avoided entirely.]
67 */
68
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/*
72 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
73 *  be unrolled one time?  In unrolled each iteration of the loop examines
74 *  two "nodes" on the chain being searched.  Otherwise, only one node
75 *  is examined per iteration.
76 *
77 *  If TRUE, then the loops are unrolled.
78 *  If FALSE, then the loops are not unrolled.
79 *
80 *  The primary factor in making this decision is the cost of disabling
81 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 *  body of the loop.  On some CPUs, the flash is more expensive than
83 *  one iteration of the loop body.  In this case, it might be desirable
84 *  to unroll the loop.  It is important to note that on some CPUs, this
85 *  code is the longest interrupt disable period in RTEMS.  So it is
86 *  necessary to strike a balance when setting this parameter.
87 */
88
89#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
90
91/*
92 *  Does this port provide a CPU dependent IDLE task implementation?
93 *
94 *  If TRUE, then the routine _CPU_Thread_Idle_body
95 *  must be provided and is the default IDLE thread body instead of
96 *  _CPU_Thread_Idle_body.
97 *
98 *  If FALSE, then use the generic IDLE thread body if the BSP does
99 *  not provide one.
100 *
101 *  This is intended to allow for supporting processors which have
102 *  a low power or idle mode.  When the IDLE thread is executed, then
103 *  the CPU can be powered down.
104 *
105 *  The order of precedence for selecting the IDLE thread body is:
106 *
107 *    1.  BSP provided
108 *    2.  CPU dependent (if provided)
109 *    3.  generic (if no BSP and no CPU dependent)
110 */
111
112#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
113
114/*
115 *  Does the stack grow up (toward higher addresses) or down
116 *  (toward lower addresses)?
117 *
118 *  If TRUE, then the grows upward.
119 *  If FALSE, then the grows toward smaller addresses.
120 */
121
122#define CPU_STACK_GROWS_UP               FALSE
123
124/*
125 *  The following is the variable attribute used to force alignment
126 *  of critical RTEMS structures.  On some processors it may make
127 *  sense to have these aligned on tighter boundaries than
128 *  the minimum requirements of the compiler in order to have as
129 *  much of the critical data area as possible in a cache line.
130 *
131 *  The placement of this macro in the declaration of the variables
132 *  is based on the syntactically requirements of the GNU C
133 *  "__attribute__" extension.  For example with GNU C, use
134 *  the following to force a structures to a 32 byte boundary.
135 *
136 *      __attribute__ ((aligned (32)))
137 *
138 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
139 *         To benefit from using this, the data must be heavily
140 *         used so it will stay in the cache and used frequently enough
141 *         in the executive to justify turning this on.
142 */
143
144#define CPU_STRUCTURE_ALIGNMENT \
145  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
146
147#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
148
149/*
150 *  Define what is required to specify how the network to host conversion
151 *  routines are handled.
152 */
153
154#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
155#define CPU_BIG_ENDIAN                           TRUE
156#define CPU_LITTLE_ENDIAN                        FALSE
157#else
158#define CPU_BIG_ENDIAN                           FALSE
159#define CPU_LITTLE_ENDIAN                        TRUE
160#endif
161
162/*
163 *  Does the CPU have hardware floating point?
164 *
165 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
166 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
167 *
168 *  If there is a FP coprocessor such as the i387 or mc68881, then
169 *  the answer is TRUE.
170 *
171 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
172 *  It indicates whether or not this CPU model has FP support.  For
173 *  example, it would be possible to have an i386_nofp CPU model
174 *  which set this to false to indicate that you have an i386 without
175 *  an i387 and wish to leave floating point support out of RTEMS.
176 */
177
178#if ( PPC_HAS_FPU == 1 )
179#define CPU_HARDWARE_FP     TRUE
180#define CPU_SOFTWARE_FP     FALSE
181#else
182#define CPU_HARDWARE_FP     FALSE
183#define CPU_SOFTWARE_FP     FALSE
184#endif
185
186/*
187 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
188 *
189 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
190 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
191 *
192 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
193 *
194 *  PowerPC Note: It appears the GCC can implicitly generate FPU
195 *  and Altivec instructions when you least expect them.  So make
196 *  all tasks floating point.
197 */
198
199#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
200
201/*
202 *  Should the IDLE task have a floating point context?
203 *
204 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
205 *  and it has a floating point context which is switched in and out.
206 *  If FALSE, then the IDLE task does not have a floating point context.
207 *
208 *  Setting this to TRUE negatively impacts the time required to preempt
209 *  the IDLE task from an interrupt because the floating point context
210 *  must be saved as part of the preemption.
211 */
212
213#define CPU_IDLE_TASK_IS_FP      FALSE
214
215#define CPU_PER_CPU_CONTROL_SIZE 0
216
217/*
218 *  Processor defined structures required for cpukit/score.
219 */
220
221/*
222 * Contexts
223 *
224 *  Generally there are 2 types of context to save.
225 *     1. Interrupt registers to save
226 *     2. Task level registers to save
227 *
228 *  This means we have the following 3 context items:
229 *     1. task level context stuff::  Context_Control
230 *     2. floating point task stuff:: Context_Control_fp
231 *     3. special interrupt level context :: Context_Control_interrupt
232 *
233 *  On some processors, it is cost-effective to save only the callee
234 *  preserved registers during a task context switch.  This means
235 *  that the ISR code needs to save those registers which do not
236 *  persist across function calls.  It is not mandatory to make this
237 *  distinctions between the caller/callee saves registers for the
238 *  purpose of minimizing context saved during task switch and on interrupts.
239 *  If the cost of saving extra registers is minimal, simplicity is the
240 *  choice.  Save the same context on interrupt entry as for tasks in
241 *  this case.
242 *
243 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
244 *  care should be used in designing the context area.
245 *
246 *  On some CPUs with hardware floating point support, the Context_Control_fp
247 *  structure will not be used or it simply consist of an array of a
248 *  fixed number of bytes.   This is done when the floating point context
249 *  is dumped by a "FP save context" type instruction and the format
250 *  is not really defined by the CPU.  In this case, there is no need
251 *  to figure out the exact format -- only the size.  Of course, although
252 *  this is enough information for RTEMS, it is probably not enough for
253 *  a debugger such as gdb.  But that is another problem.
254 */
255
256#ifndef __SPE__
257  #define PPC_GPR_TYPE uint32_t
258  #define PPC_GPR_SIZE 4
259  #define PPC_GPR_LOAD lwz
260  #define PPC_GPR_STORE stw
261#else
262  #define PPC_GPR_TYPE uint64_t
263  #define PPC_GPR_SIZE 8
264  #define PPC_GPR_LOAD evldd
265  #define PPC_GPR_STORE evstdd
266#endif
267
268#define PPC_DEFAULT_CACHE_LINE_SIZE 32
269
270#ifndef ASM
271
272typedef struct {
273  /* There is no CPU specific per-CPU state */
274} CPU_Per_CPU_control;
275
276/*
277 * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according
278 * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 -
279 * Linux and Embedded")
280 */
281typedef struct {
282  uint32_t gpr1;
283  uint32_t msr;
284  uint32_t lr;
285  uint32_t cr;
286  PPC_GPR_TYPE gpr14;
287  PPC_GPR_TYPE gpr15;
288  PPC_GPR_TYPE gpr16;
289  PPC_GPR_TYPE gpr17;
290  PPC_GPR_TYPE gpr18;
291  PPC_GPR_TYPE gpr19;
292  PPC_GPR_TYPE gpr20;
293  PPC_GPR_TYPE gpr21;
294  PPC_GPR_TYPE gpr22;
295  PPC_GPR_TYPE gpr23;
296  PPC_GPR_TYPE gpr24;
297  PPC_GPR_TYPE gpr25;
298  PPC_GPR_TYPE gpr26;
299  PPC_GPR_TYPE gpr27;
300  PPC_GPR_TYPE gpr28;
301  PPC_GPR_TYPE gpr29;
302  PPC_GPR_TYPE gpr30;
303  PPC_GPR_TYPE gpr31;
304  uint32_t gpr2;
305  #ifdef RTEMS_SMP
306    volatile uint32_t is_executing;
307  #endif
308  #ifdef __ALTIVEC__
309    /*
310     * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
311     * and padding to ensure cache-alignment.  Unfortunately, we can't verify
312     * the cache line size here in the cpukit but altivec support code will
313     * produce an error if this is ever different from 32 bytes.
314     *
315     * Note: it is the BSP/CPU-support's responsibility to save/restore
316     *       volatile vregs across interrupts and exceptions.
317     */
318    uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
319  #endif
320} ppc_context;
321
322typedef struct {
323  uint8_t context [
324    PPC_DEFAULT_CACHE_LINE_SIZE
325      + sizeof(ppc_context)
326      + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
327        ? 0
328          : PPC_DEFAULT_CACHE_LINE_SIZE
329            - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
330  ];
331} Context_Control;
332
333static inline ppc_context *ppc_get_context( const Context_Control *context )
334{
335  uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
336  uintptr_t mask = clsz - 1;
337  uintptr_t addr = (uintptr_t) context;
338
339  return (ppc_context *) ((addr & ~mask) + clsz);
340}
341
342#define _CPU_Context_Get_SP( _context ) \
343  ppc_get_context(_context)->gpr1
344
345#ifdef RTEMS_SMP
346  static inline bool _CPU_Context_Get_is_executing(
347    const Context_Control *context
348  )
349  {
350    return ppc_get_context(context)->is_executing;
351  }
352
353  static inline void _CPU_Context_Set_is_executing(
354    Context_Control *context,
355    bool is_executing
356  )
357  {
358    ppc_get_context(context)->is_executing = is_executing;
359  }
360#endif
361#endif /* ASM */
362
363#define PPC_CONTEXT_OFFSET_GPR1 32
364#define PPC_CONTEXT_OFFSET_MSR 36
365#define PPC_CONTEXT_OFFSET_LR 40
366#define PPC_CONTEXT_OFFSET_CR 44
367
368#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
369  (((gpr) - 14) * PPC_GPR_SIZE + 48)
370
371#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
372#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
373#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
374#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
375#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
376#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
377#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
378#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
379#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
380#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
381#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
382#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
383#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
384#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
385#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
386#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
387#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
388#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
389#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 )
390
391#ifdef RTEMS_SMP
392  #define PPC_CONTEXT_OFFSET_IS_EXECUTING (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4)
393#endif
394
395#ifndef ASM
396typedef struct {
397    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
398     * procedure calls.  However, this would mean that the interrupt
399     * frame had to hold f0-f13, and the fpscr.  And as the majority
400     * of tasks will not have an FP context, we will save the whole
401     * context here.
402     */
403#if (PPC_HAS_DOUBLE == 1)
404    double      f[32];
405    uint64_t    fpscr;
406#else
407    float       f[32];
408    uint32_t    fpscr;
409#endif
410} Context_Control_fp;
411
412typedef struct CPU_Interrupt_frame {
413    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
414    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
415
416    /* This is what is left out of the primary contexts */
417    uint32_t   gpr0;
418    uint32_t   gpr2;            /* play safe */
419    uint32_t   gpr3;
420    uint32_t   gpr4;
421    uint32_t   gpr5;
422    uint32_t   gpr6;
423    uint32_t   gpr7;
424    uint32_t   gpr8;
425    uint32_t   gpr9;
426    uint32_t   gpr10;
427    uint32_t   gpr11;
428    uint32_t   gpr12;
429    uint32_t   gpr13;   /* Play safe */
430    uint32_t   gpr28;   /* For internal use by the IRQ handler */
431    uint32_t   gpr29;   /* For internal use by the IRQ handler */
432    uint32_t   gpr30;   /* For internal use by the IRQ handler */
433    uint32_t   gpr31;   /* For internal use by the IRQ handler */
434    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
435    uint32_t   ctr;
436    uint32_t   xer;
437    uint32_t   lr;
438    uint32_t   pc;
439    uint32_t   msr;
440    uint32_t   pad[3];
441} CPU_Interrupt_frame;
442
443#endif /* ASM */
444
445/*
446 *  Does the CPU follow the simple vectored interrupt model?
447 *
448 *  If TRUE, then RTEMS allocates the vector table it internally manages.
449 *  If FALSE, then the BSP is assumed to allocate and manage the vector
450 *  table
451 *
452 *  PowerPC Specific Information:
453 *
454 *  The PowerPC and x86 were the first to use the PIC interrupt model.
455 *  They do not use the simple vectored interrupt model.
456 */
457#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
458
459/*
460 *  Does RTEMS manage a dedicated interrupt stack in software?
461 *
462 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
463 *  If FALSE, nothing is done.
464 *
465 *  If the CPU supports a dedicated interrupt stack in hardware,
466 *  then it is generally the responsibility of the BSP to allocate it
467 *  and set it up.
468 *
469 *  If the CPU does not support a dedicated interrupt stack, then
470 *  the porter has two options: (1) execute interrupts on the
471 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
472 *  interrupt stack.
473 *
474 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
475 *
476 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
477 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
478 *  possible that both are FALSE for a particular CPU.  Although it
479 *  is unclear what that would imply about the interrupt processing
480 *  procedure on that CPU.
481 */
482
483#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
484
485/*
486 *  Does this CPU have hardware support for a dedicated interrupt stack?
487 *
488 *  If TRUE, then it must be installed during initialization.
489 *  If FALSE, then no installation is performed.
490 *
491 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
492 *
493 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
494 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
495 *  possible that both are FALSE for a particular CPU.  Although it
496 *  is unclear what that would imply about the interrupt processing
497 *  procedure on that CPU.
498 */
499
500#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
501
502/*
503 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
504 *
505 *  If TRUE, then the memory is allocated during initialization.
506 *  If FALSE, then the memory is allocated during initialization.
507 *
508 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
509 */
510
511#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
512
513/*
514 *  Does the RTEMS invoke the user's ISR with the vector number and
515 *  a pointer to the saved interrupt frame (1) or just the vector
516 *  number (0)?
517 */
518
519#define CPU_ISR_PASSES_FRAME_POINTER 0
520
521/*
522 *  Should the saving of the floating point registers be deferred
523 *  until a context switch is made to another different floating point
524 *  task?
525 *
526 *  If TRUE, then the floating point context will not be stored until
527 *  necessary.  It will remain in the floating point registers and not
528 *  disturned until another floating point task is switched to.
529 *
530 *  If FALSE, then the floating point context is saved when a floating
531 *  point task is switched out and restored when the next floating point
532 *  task is restored.  The state of the floating point registers between
533 *  those two operations is not specified.
534 *
535 *  If the floating point context does NOT have to be saved as part of
536 *  interrupt dispatching, then it should be safe to set this to TRUE.
537 *
538 *  Setting this flag to TRUE results in using a different algorithm
539 *  for deciding when to save and restore the floating point context.
540 *  The deferred FP switch algorithm minimizes the number of times
541 *  the FP context is saved and restored.  The FP context is not saved
542 *  until a context switch is made to another, different FP task.
543 *  Thus in a system with only one FP task, the FP context will never
544 *  be saved or restored.
545 *
546 *  Note, however that compilers may use floating point registers/
547 *  instructions for optimization or they may save/restore FP registers
548 *  on the stack. You must not use deferred switching in these cases
549 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
550 *  exception.
551 */
552/*
553 *  ACB Note:  This could make debugging tricky..
554 */
555
556/* conservative setting (FALSE); probably doesn't affect performance too much */
557#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
558
559/*
560 *  Processor defined structures required for cpukit/score.
561 */
562
563#ifndef ASM
564
565/*
566 *  This variable is optional.  It is used on CPUs on which it is difficult
567 *  to generate an "uninitialized" FP context.  It is filled in by
568 *  _CPU_Initialize and copied into the task's FP context area during
569 *  _CPU_Context_Initialize.
570 */
571
572/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
573
574#endif /* ndef ASM */
575
576/*
577 *  This defines the number of levels and the mask used to pick those
578 *  bits out of a thread mode.
579 */
580
581#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
582#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
583
584/*
585 *  Nothing prevents the porter from declaring more CPU specific variables.
586 */
587
588#ifndef ASM
589
590SCORE_EXTERN struct {
591  uint32_t      *Disable_level;
592  void          *Stack;
593  volatile bool *Switch_necessary;
594  bool          *Signal;
595
596} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
597
598#endif /* ndef ASM */
599
600/*
601 *  The size of the floating point context area.  On some CPUs this
602 *  will not be a "sizeof" because the format of the floating point
603 *  area is not defined -- only the size is.  This is usually on
604 *  CPUs with a "floating point save context" instruction.
605 */
606
607#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
608
609/*
610 * (Optional) # of bytes for libmisc/stackchk to check
611 * If not specifed, then it defaults to something reasonable
612 * for most architectures.
613 */
614
615#define CPU_STACK_CHECK_SIZE    (128)
616
617/*
618 *  Amount of extra stack (above minimum stack size) required by
619 *  MPCI receive server thread.  Remember that in a multiprocessor
620 *  system this thread must exist and be able to process all directives.
621 */
622
623#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
624
625/*
626 *  This is defined if the port has a special way to report the ISR nesting
627 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
628 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
629 *  being maintained (e.g. watchdog queues).
630 */
631
632#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
633
634/*
635 *  ISR handler macros
636 */
637
638/*
639 *  Disable all interrupts for an RTEMS critical section.  The previous
640 *  level is returned in _isr_cookie.
641 */
642
643#ifndef ASM
644
645static inline uint32_t   _CPU_ISR_Get_level( void )
646{
647  register unsigned int msr;
648  _CPU_MSR_GET(msr);
649  if (msr & MSR_EE) return 0;
650  else  return 1;
651}
652
653static inline void _CPU_ISR_Set_level( uint32_t   level )
654{
655  register unsigned int msr;
656  _CPU_MSR_GET(msr);
657  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
658    msr |= ppc_interrupt_get_disable_mask();
659  }
660  else {
661    msr &= ~ppc_interrupt_get_disable_mask();
662  }
663  _CPU_MSR_SET(msr);
664}
665
666void BSP_panic(char *);
667
668/* Fatal Error manager macros */
669
670/*
671 *  This routine copies _error into a known place -- typically a stack
672 *  location or a register, optionally disables interrupts, and
673 *  halts/stops the CPU.
674 */
675
676void _BSP_Fatal_error(unsigned int);
677
678#endif /* ASM */
679
680#define _CPU_Fatal_halt( _source, _error ) \
681  _BSP_Fatal_error(_error)
682
683/* end of Fatal Error manager macros */
684
685/*
686 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
687 * Now SPRG0 is devoted to the interrupt disable mask.
688 */
689
690#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
691
692/*
693 *  Should be large enough to run all RTEMS tests.  This ensures
694 *  that a "reasonable" small application should not have any problems.
695 */
696
697#define CPU_STACK_MINIMUM_SIZE          (1024*8)
698
699#define CPU_SIZEOF_POINTER 4
700
701/*
702 *  CPU's worst alignment requirement for data types on a byte boundary.  This
703 *  alignment does not take into account the requirements for the stack.
704 */
705
706#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
707
708/*
709 *  This number corresponds to the byte alignment requirement for the
710 *  heap handler.  This alignment requirement may be stricter than that
711 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
712 *  common for the heap to follow the same alignment requirement as
713 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
714 *  then this should be set to CPU_ALIGNMENT.
715 *
716 *  NOTE:  This does not have to be a power of 2.  It does have to
717 *         be greater or equal to than CPU_ALIGNMENT.
718 */
719
720#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
721
722/*
723 *  This number corresponds to the byte alignment requirement for memory
724 *  buffers allocated by the partition manager.  This alignment requirement
725 *  may be stricter than that for the data types alignment specified by
726 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
727 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
728 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
729 *
730 *  NOTE:  This does not have to be a power of 2.  It does have to
731 *         be greater or equal to than CPU_ALIGNMENT.
732 */
733
734#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
735
736/*
737 *  This number corresponds to the byte alignment requirement for the
738 *  stack.  This alignment requirement may be stricter than that for the
739 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
740 *  is strict enough for the stack, then this should be set to 0.
741 *
742 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
743 */
744
745#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
746
747#ifndef ASM
748/*  The following routine swaps the endian format of an unsigned int.
749 *  It must be static because it is referenced indirectly.
750 *
751 *  This version will work on any processor, but if there is a better
752 *  way for your CPU PLEASE use it.  The most common way to do this is to:
753 *
754 *     swap least significant two bytes with 16-bit rotate
755 *     swap upper and lower 16-bits
756 *     swap most significant two bytes with 16-bit rotate
757 *
758 *  Some CPUs have special instructions which swap a 32-bit quantity in
759 *  a single instruction (e.g. i486).  It is probably best to avoid
760 *  an "endian swapping control bit" in the CPU.  One good reason is
761 *  that interrupts would probably have to be disabled to ensure that
762 *  an interrupt does not try to access the same "chunk" with the wrong
763 *  endian.  Another good reason is that on some CPUs, the endian bit
764 *  endianness for ALL fetches -- both code and data -- so the code
765 *  will be fetched incorrectly.
766 */
767
768static inline uint32_t CPU_swap_u32(
769  uint32_t value
770)
771{
772  uint32_t   swapped;
773
774  __asm__ volatile("rlwimi %0,%1,8,24,31;"
775               "rlwimi %0,%1,24,16,23;"
776               "rlwimi %0,%1,8,8,15;"
777               "rlwimi %0,%1,24,0,7;" :
778               "=&r" ((swapped)) : "r" ((value)));
779
780  return( swapped );
781}
782
783#define CPU_swap_u16( value ) \
784  (((value&0xff) << 8) | ((value >> 8)&0xff))
785
786typedef uint32_t CPU_Counter_ticks;
787
788static inline CPU_Counter_ticks _CPU_Counter_read( void )
789{
790  CPU_Counter_ticks value;
791
792#ifdef ppc8540
793  /* Book E has no mftb */
794  __asm__ volatile( "mfspr %0, 268" : "=r" (value) );
795#else
796  __asm__ volatile( "mftb %0" : "=r" (value) );
797#endif
798
799  return value;
800}
801
802static inline CPU_Counter_ticks _CPU_Counter_difference(
803  CPU_Counter_ticks second,
804  CPU_Counter_ticks first
805)
806{
807  return second - first;
808}
809
810#endif /* ASM */
811
812
813#ifndef ASM
814/* Context handler macros */
815
816/*
817 *  Initialize the context to a state suitable for starting a
818 *  task after a context restore operation.  Generally, this
819 *  involves:
820 *
821 *     - setting a starting address
822 *     - preparing the stack
823 *     - preparing the stack and frame pointers
824 *     - setting the proper interrupt level in the context
825 *     - initializing the floating point context
826 *
827 *  This routine generally does not set any unnecessary register
828 *  in the context.  The state of the "general data" registers is
829 *  undefined at task start time.
830 */
831
832void _CPU_Context_Initialize(
833  Context_Control  *the_context,
834  uint32_t         *stack_base,
835  uint32_t          size,
836  uint32_t          new_level,
837  void             *entry_point,
838  bool              is_fp,
839  void             *tls_area
840);
841
842/*
843 *  This routine is responsible for somehow restarting the currently
844 *  executing task.  If you are lucky, then all that is necessary
845 *  is restoring the context.  Otherwise, there will need to be
846 *  a special assembly routine which does something special in this
847 *  case.  Context_Restore should work most of the time.  It will
848 *  not work if restarting self conflicts with the stack frame
849 *  assumptions of restoring a context.
850 */
851
852#define _CPU_Context_Restart_self( _the_context ) \
853   _CPU_Context_restore( (_the_context) );
854
855/*
856 *  The purpose of this macro is to allow the initial pointer into
857 *  a floating point context area (used to save the floating point
858 *  context) to be at an arbitrary place in the floating point
859 *  context area.
860 *
861 *  This is necessary because some FP units are designed to have
862 *  their context saved as a stack which grows into lower addresses.
863 *  Other FP units can be saved by simply moving registers into offsets
864 *  from the base of the context area.  Finally some FP units provide
865 *  a "dump context" instruction which could fill in from high to low
866 *  or low to high based on the whim of the CPU designers.
867 */
868
869#define _CPU_Context_Fp_start( _base, _offset ) \
870   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
871
872/*
873 *  This routine initializes the FP context area passed to it to.
874 *  There are a few standard ways in which to initialize the
875 *  floating point context.  The code included for this macro assumes
876 *  that this is a CPU in which a "initial" FP context was saved into
877 *  _CPU_Null_fp_context and it simply copies it to the destination
878 *  context passed to it.
879 *
880 *  Other models include (1) not doing anything, and (2) putting
881 *  a "null FP status word" in the correct place in the FP context.
882 */
883
884#define _CPU_Context_Initialize_fp( _destination ) \
885  memset( *(_destination), 0, sizeof( **(_destination) ) )
886
887/* end of Context handler macros */
888#endif /* ASM */
889
890#ifndef ASM
891/* Bitfield handler macros */
892
893/*
894 *  This routine sets _output to the bit number of the first bit
895 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
896 *  This type may be either 16 or 32 bits wide although only the 16
897 *  least significant bits will be used.
898 *
899 *  There are a number of variables in using a "find first bit" type
900 *  instruction.
901 *
902 *    (1) What happens when run on a value of zero?
903 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
904 *    (3) The numbering may be zero or one based.
905 *    (4) The "find first bit" instruction may search from MSB or LSB.
906 *
907 *  RTEMS guarantees that (1) will never happen so it is not a concern.
908 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
909 *  _CPU_Priority_Bits_index().  These three form a set of routines
910 *  which must logically operate together.  Bits in the _value are
911 *  set and cleared based on masks built by _CPU_Priority_mask().
912 *  The basic major and minor values calculated by _Priority_Major()
913 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
914 *  to properly range between the values returned by the "find first bit"
915 *  instruction.  This makes it possible for _Priority_Get_highest() to
916 *  calculate the major and directly index into the minor table.
917 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
918 *  is the first bit found.
919 *
920 *  This entire "find first bit" and mapping process depends heavily
921 *  on the manner in which a priority is broken into a major and minor
922 *  components with the major being the 4 MSB of a priority and minor
923 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
924 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
925 *  to the lowest priority.
926 *
927 *  If your CPU does not have a "find first bit" instruction, then
928 *  there are ways to make do without it.  Here are a handful of ways
929 *  to implement this in software:
930 *
931 *    - a series of 16 bit test instructions
932 *    - a "binary search using if's"
933 *    - _number = 0
934 *      if _value > 0x00ff
935 *        _value >>=8
936 *        _number = 8;
937 *
938 *      if _value > 0x0000f
939 *        _value >=8
940 *        _number += 4
941 *
942 *      _number += bit_set_table[ _value ]
943 *
944 *    where bit_set_table[ 16 ] has values which indicate the first
945 *      bit set
946 */
947
948#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
949  { \
950    __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
951                  "1" ((_value))); \
952  }
953
954/* end of Bitfield handler macros */
955
956/*
957 *  This routine builds the mask which corresponds to the bit fields
958 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
959 *  for that routine.
960 */
961
962#define _CPU_Priority_Mask( _bit_number ) \
963  ( 0x80000000 >> (_bit_number) )
964
965/*
966 *  This routine translates the bit numbers returned by
967 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
968 *  a major or minor component of a priority.  See the discussion
969 *  for that routine.
970 */
971
972#define _CPU_Priority_bits_index( _priority ) \
973  (_priority)
974
975/* end of Priority handler macros */
976#endif /* ASM */
977
978/* functions */
979
980#ifndef ASM
981
982/*
983 *  _CPU_Initialize
984 *
985 *  This routine performs CPU dependent initialization.
986 */
987
988void _CPU_Initialize(void);
989
990/*
991 *  _CPU_ISR_install_vector
992 *
993 *  This routine installs an interrupt vector.
994 */
995
996void _CPU_ISR_install_vector(
997  uint32_t    vector,
998  proc_ptr    new_handler,
999  proc_ptr   *old_handler
1000);
1001
1002/*
1003 *  _CPU_Context_switch
1004 *
1005 *  This routine switches from the run context to the heir context.
1006 */
1007
1008void _CPU_Context_switch(
1009  Context_Control  *run,
1010  Context_Control  *heir
1011);
1012
1013/*
1014 *  _CPU_Context_restore
1015 *
1016 *  This routine is generallu used only to restart self in an
1017 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1018 *
1019 *  NOTE: May be unnecessary to reload some registers.
1020 */
1021
1022void _CPU_Context_restore(
1023  Context_Control *new_context
1024) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1025
1026/*
1027 *  _CPU_Context_save_fp
1028 *
1029 *  This routine saves the floating point context passed to it.
1030 */
1031
1032void _CPU_Context_save_fp(
1033  Context_Control_fp **fp_context_ptr
1034);
1035
1036/*
1037 *  _CPU_Context_restore_fp
1038 *
1039 *  This routine restores the floating point context passed to it.
1040 */
1041
1042void _CPU_Context_restore_fp(
1043  Context_Control_fp **fp_context_ptr
1044);
1045
1046void _CPU_Context_volatile_clobber( uintptr_t pattern );
1047
1048void _CPU_Context_validate( uintptr_t pattern );
1049
1050#ifdef RTEMS_SMP
1051  uint32_t _CPU_SMP_Initialize( void );
1052
1053  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1054
1055  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1056
1057  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1058  {
1059    uint32_t pir;
1060
1061    /* Use Book E Processor ID Register (PIR) */
1062    __asm__ volatile (
1063      "mfspr %[pir], 286"
1064      : [pir] "=&r" (pir)
1065    );
1066
1067    return pir;
1068  }
1069
1070  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1071
1072  static inline void _CPU_SMP_Processor_event_broadcast( void )
1073  {
1074    __asm__ volatile ( "" : : : "memory" );
1075  }
1076
1077  static inline void _CPU_SMP_Processor_event_receive( void )
1078  {
1079    __asm__ volatile ( "" : : : "memory" );
1080  }
1081#endif
1082
1083typedef struct {
1084  uint32_t EXC_SRR0;
1085  uint32_t EXC_SRR1;
1086  uint32_t _EXC_number;
1087  uint32_t EXC_CR;
1088  uint32_t EXC_CTR;
1089  uint32_t EXC_XER;
1090  uint32_t EXC_LR;
1091  #ifdef __SPE__
1092    uint32_t EXC_SPEFSCR;
1093    uint64_t EXC_ACC;
1094  #endif
1095  PPC_GPR_TYPE GPR0;
1096  PPC_GPR_TYPE GPR1;
1097  PPC_GPR_TYPE GPR2;
1098  PPC_GPR_TYPE GPR3;
1099  PPC_GPR_TYPE GPR4;
1100  PPC_GPR_TYPE GPR5;
1101  PPC_GPR_TYPE GPR6;
1102  PPC_GPR_TYPE GPR7;
1103  PPC_GPR_TYPE GPR8;
1104  PPC_GPR_TYPE GPR9;
1105  PPC_GPR_TYPE GPR10;
1106  PPC_GPR_TYPE GPR11;
1107  PPC_GPR_TYPE GPR12;
1108  PPC_GPR_TYPE GPR13;
1109  PPC_GPR_TYPE GPR14;
1110  PPC_GPR_TYPE GPR15;
1111  PPC_GPR_TYPE GPR16;
1112  PPC_GPR_TYPE GPR17;
1113  PPC_GPR_TYPE GPR18;
1114  PPC_GPR_TYPE GPR19;
1115  PPC_GPR_TYPE GPR20;
1116  PPC_GPR_TYPE GPR21;
1117  PPC_GPR_TYPE GPR22;
1118  PPC_GPR_TYPE GPR23;
1119  PPC_GPR_TYPE GPR24;
1120  PPC_GPR_TYPE GPR25;
1121  PPC_GPR_TYPE GPR26;
1122  PPC_GPR_TYPE GPR27;
1123  PPC_GPR_TYPE GPR28;
1124  PPC_GPR_TYPE GPR29;
1125  PPC_GPR_TYPE GPR30;
1126  PPC_GPR_TYPE GPR31;
1127} CPU_Exception_frame;
1128
1129void _BSP_Exception_frame_print( const CPU_Exception_frame *frame );
1130
1131static inline void _CPU_Exception_frame_print(
1132  const CPU_Exception_frame *frame
1133)
1134{
1135  _BSP_Exception_frame_print( frame );
1136}
1137
1138/*
1139 * _CPU_Initialize_altivec()
1140 *
1141 * Global altivec-related initialization.
1142 */
1143void
1144_CPU_Initialize_altivec(void);
1145
1146/*
1147 * _CPU_Context_switch_altivec
1148 *
1149 * This routine switches the altivec contexts passed to it.
1150 */
1151
1152void
1153_CPU_Context_switch_altivec(
1154  ppc_context *from,
1155  ppc_context *to
1156);
1157
1158/*
1159 * _CPU_Context_restore_altivec
1160 *
1161 * This routine restores the altivec context passed to it.
1162 */
1163
1164void
1165_CPU_Context_restore_altivec(
1166  ppc_context *ctxt
1167);
1168
1169/*
1170 * _CPU_Context_initialize_altivec
1171 *
1172 * This routine initializes the altivec context passed to it.
1173 */
1174
1175void
1176_CPU_Context_initialize_altivec(
1177  ppc_context *ctxt
1178);
1179
1180void _CPU_Fatal_error(
1181  uint32_t   _error
1182);
1183
1184#endif /* ASM */
1185
1186#ifdef __cplusplus
1187}
1188#endif
1189
1190#endif /* _RTEMS_SCORE_CPU_H */
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