1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #ifndef _RTEMS_SCORE_CPU_H |
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10 | #define _RTEMS_SCORE_CPU_H |
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11 | |
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12 | #include <rtems/score/powerpc.h> /* pick up machine definitions */ |
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13 | #ifndef ASM |
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14 | #include <rtems/score/types.h> |
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15 | #endif |
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16 | |
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17 | /* conditional compilation parameters */ |
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18 | |
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19 | /* |
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20 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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21 | * |
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22 | * If TRUE, then they are inlined. |
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23 | * If FALSE, then a subroutine call is made. |
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24 | * |
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25 | * Basically this is an example of the classic trade-off of size |
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26 | * versus speed. Inlining the call (TRUE) typically increases the |
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27 | * size of RTEMS while speeding up the enabling of dispatching. |
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28 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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29 | * only be 0 or 1 unless you are in an interrupt handler and that |
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30 | * interrupt handler invokes the executive.] When not inlined |
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31 | * something calls _Thread_Enable_dispatch which in turns calls |
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32 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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33 | * one subroutine call is avoided entirely.] |
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34 | */ |
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35 | |
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36 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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37 | |
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38 | /* |
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39 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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40 | * be unrolled one time? In unrolled each iteration of the loop examines |
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41 | * two "nodes" on the chain being searched. Otherwise, only one node |
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42 | * is examined per iteration. |
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43 | * |
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44 | * If TRUE, then the loops are unrolled. |
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45 | * If FALSE, then the loops are not unrolled. |
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46 | * |
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47 | * The primary factor in making this decision is the cost of disabling |
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48 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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49 | * body of the loop. On some CPUs, the flash is more expensive than |
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50 | * one iteration of the loop body. In this case, it might be desirable |
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51 | * to unroll the loop. It is important to note that on some CPUs, this |
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52 | * code is the longest interrupt disable period in RTEMS. So it is |
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53 | * necessary to strike a balance when setting this parameter. |
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54 | */ |
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55 | |
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56 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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57 | |
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58 | #ifdef _OLD_EXCEPTIONS |
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59 | #include <rtems/old-exceptions/cpu.h> |
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60 | #else |
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61 | #include <rtems/new-exceptions/cpu.h> |
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62 | #endif |
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63 | |
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64 | #ifndef ASM |
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65 | /* The following routine swaps the endian format of an unsigned int. |
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66 | * It must be static because it is referenced indirectly. |
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67 | * |
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68 | * This version will work on any processor, but if there is a better |
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69 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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70 | * |
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71 | * swap least significant two bytes with 16-bit rotate |
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72 | * swap upper and lower 16-bits |
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73 | * swap most significant two bytes with 16-bit rotate |
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74 | * |
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75 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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76 | * a single instruction (e.g. i486). It is probably best to avoid |
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77 | * an "endian swapping control bit" in the CPU. One good reason is |
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78 | * that interrupts would probably have to be disabled to insure that |
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79 | * an interrupt does not try to access the same "chunk" with the wrong |
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80 | * endian. Another good reason is that on some CPUs, the endian bit |
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81 | * endianness for ALL fetches -- both code and data -- so the code |
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82 | * will be fetched incorrectly. |
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83 | */ |
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84 | |
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85 | static inline uint32_t CPU_swap_u32( |
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86 | uint32_t value |
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87 | ) |
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88 | { |
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89 | uint32_t swapped; |
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90 | |
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91 | asm volatile("rlwimi %0,%1,8,24,31;" |
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92 | "rlwimi %0,%1,24,16,23;" |
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93 | "rlwimi %0,%1,8,8,15;" |
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94 | "rlwimi %0,%1,24,0,7;" : |
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95 | "=&r" ((swapped)) : "r" ((value))); |
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96 | |
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97 | return( swapped ); |
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98 | } |
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99 | |
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100 | #define CPU_swap_u16( value ) \ |
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101 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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102 | |
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103 | #endif /* ASM */ |
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104 | |
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105 | #ifndef ASM |
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106 | /* |
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107 | * Macros to access PowerPC specific additions to the CPU Table |
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108 | */ |
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109 | |
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110 | #define rtems_cpu_configuration_get_clicks_per_usec() \ |
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111 | (_CPU_Table.clicks_per_usec) |
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112 | |
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113 | #define rtems_cpu_configuration_get_exceptions_in_ram() \ |
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114 | (_CPU_Table.exceptions_in_RAM) |
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115 | |
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116 | #endif /* ASM */ |
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117 | |
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118 | #ifndef /* ASM */ |
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119 | /* |
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120 | * Simple spin delay in microsecond units for device drivers. |
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121 | * This is very dependent on the clock speed of the target. |
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122 | */ |
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123 | |
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124 | #define CPU_Get_timebase_low( _value ) \ |
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125 | asm volatile( "mftb %0" : "=r" (_value) ) |
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126 | |
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127 | #define rtems_bsp_delay( _microseconds ) \ |
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128 | do { \ |
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129 | uint32_t start, ticks, now; \ |
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130 | CPU_Get_timebase_low( start ) ; \ |
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131 | ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \ |
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132 | do \ |
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133 | CPU_Get_timebase_low( now ) ; \ |
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134 | while (now - start < ticks); \ |
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135 | } while (0) |
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136 | |
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137 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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138 | do { \ |
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139 | uint32_t start, now; \ |
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140 | CPU_Get_timebase_low( start ); \ |
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141 | do \ |
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142 | CPU_Get_timebase_low( now ); \ |
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143 | while (now - start < (_cycles)); \ |
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144 | } while (0) |
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145 | |
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146 | #endif /* ASM */ |
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147 | |
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148 | #endif /* _RTEMS_SCORE_CPU_H */ |
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149 | |
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