1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @brief PowerPC CPU Department Source |
---|
5 | */ |
---|
6 | |
---|
7 | /* |
---|
8 | * COPYRIGHT (c) 1989-2012. |
---|
9 | * On-Line Applications Research Corporation (OAR). |
---|
10 | * |
---|
11 | * COPYRIGHT (c) 1995 i-cubed ltd. |
---|
12 | * |
---|
13 | * To anyone who acknowledges that this file is provided "AS IS" |
---|
14 | * without any express or implied warranty: |
---|
15 | * permission to use, copy, modify, and distribute this file |
---|
16 | * for any purpose is hereby granted without fee, provided that |
---|
17 | * the above copyright notice and this notice appears in all |
---|
18 | * copies, and that the name of i-cubed limited not be used in |
---|
19 | * advertising or publicity pertaining to distribution of the |
---|
20 | * software without specific, written prior permission. |
---|
21 | * i-cubed limited makes no representations about the suitability |
---|
22 | * of this software for any purpose. |
---|
23 | * |
---|
24 | * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. |
---|
25 | * |
---|
26 | * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). |
---|
27 | * |
---|
28 | * Copyright (c) 2010-2013 embedded brains GmbH. |
---|
29 | * |
---|
30 | * The license and distribution terms for this file may be |
---|
31 | * found in the file LICENSE in this distribution or at |
---|
32 | * http://www.rtems.org/license/LICENSE. |
---|
33 | */ |
---|
34 | |
---|
35 | #ifndef _RTEMS_SCORE_CPU_H |
---|
36 | #define _RTEMS_SCORE_CPU_H |
---|
37 | |
---|
38 | #include <rtems/score/types.h> |
---|
39 | #include <rtems/score/powerpc.h> |
---|
40 | #include <rtems/powerpc/registers.h> |
---|
41 | |
---|
42 | #ifndef ASM |
---|
43 | #include <string.h> /* for memset() */ |
---|
44 | #endif |
---|
45 | |
---|
46 | #ifdef __cplusplus |
---|
47 | extern "C" { |
---|
48 | #endif |
---|
49 | |
---|
50 | /* conditional compilation parameters */ |
---|
51 | |
---|
52 | /* |
---|
53 | * Should the calls to _Thread_Enable_dispatch be inlined? |
---|
54 | * |
---|
55 | * If TRUE, then they are inlined. |
---|
56 | * If FALSE, then a subroutine call is made. |
---|
57 | * |
---|
58 | * Basically this is an example of the classic trade-off of size |
---|
59 | * versus speed. Inlining the call (TRUE) typically increases the |
---|
60 | * size of RTEMS while speeding up the enabling of dispatching. |
---|
61 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
---|
62 | * only be 0 or 1 unless you are in an interrupt handler and that |
---|
63 | * interrupt handler invokes the executive.] When not inlined |
---|
64 | * something calls _Thread_Enable_dispatch which in turns calls |
---|
65 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
---|
66 | * one subroutine call is avoided entirely.] |
---|
67 | */ |
---|
68 | |
---|
69 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
---|
70 | |
---|
71 | /* |
---|
72 | * Does this port provide a CPU dependent IDLE task implementation? |
---|
73 | * |
---|
74 | * If TRUE, then the routine _CPU_Thread_Idle_body |
---|
75 | * must be provided and is the default IDLE thread body instead of |
---|
76 | * _CPU_Thread_Idle_body. |
---|
77 | * |
---|
78 | * If FALSE, then use the generic IDLE thread body if the BSP does |
---|
79 | * not provide one. |
---|
80 | * |
---|
81 | * This is intended to allow for supporting processors which have |
---|
82 | * a low power or idle mode. When the IDLE thread is executed, then |
---|
83 | * the CPU can be powered down. |
---|
84 | * |
---|
85 | * The order of precedence for selecting the IDLE thread body is: |
---|
86 | * |
---|
87 | * 1. BSP provided |
---|
88 | * 2. CPU dependent (if provided) |
---|
89 | * 3. generic (if no BSP and no CPU dependent) |
---|
90 | */ |
---|
91 | |
---|
92 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
---|
93 | |
---|
94 | /* |
---|
95 | * Does the stack grow up (toward higher addresses) or down |
---|
96 | * (toward lower addresses)? |
---|
97 | * |
---|
98 | * If TRUE, then the grows upward. |
---|
99 | * If FALSE, then the grows toward smaller addresses. |
---|
100 | */ |
---|
101 | |
---|
102 | #define CPU_STACK_GROWS_UP FALSE |
---|
103 | |
---|
104 | /* |
---|
105 | * The following is the variable attribute used to force alignment |
---|
106 | * of critical RTEMS structures. On some processors it may make |
---|
107 | * sense to have these aligned on tighter boundaries than |
---|
108 | * the minimum requirements of the compiler in order to have as |
---|
109 | * much of the critical data area as possible in a cache line. |
---|
110 | * |
---|
111 | * The placement of this macro in the declaration of the variables |
---|
112 | * is based on the syntactically requirements of the GNU C |
---|
113 | * "__attribute__" extension. For example with GNU C, use |
---|
114 | * the following to force a structures to a 32 byte boundary. |
---|
115 | * |
---|
116 | * __attribute__ ((aligned (32))) |
---|
117 | * |
---|
118 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
---|
119 | * To benefit from using this, the data must be heavily |
---|
120 | * used so it will stay in the cache and used frequently enough |
---|
121 | * in the executive to justify turning this on. |
---|
122 | */ |
---|
123 | |
---|
124 | #define CPU_STRUCTURE_ALIGNMENT \ |
---|
125 | __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) |
---|
126 | |
---|
127 | #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE |
---|
128 | |
---|
129 | /* |
---|
130 | * Define what is required to specify how the network to host conversion |
---|
131 | * routines are handled. |
---|
132 | */ |
---|
133 | |
---|
134 | #if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) |
---|
135 | #define CPU_BIG_ENDIAN TRUE |
---|
136 | #define CPU_LITTLE_ENDIAN FALSE |
---|
137 | #else |
---|
138 | #define CPU_BIG_ENDIAN FALSE |
---|
139 | #define CPU_LITTLE_ENDIAN TRUE |
---|
140 | #endif |
---|
141 | |
---|
142 | /* |
---|
143 | * Does the CPU have hardware floating point? |
---|
144 | * |
---|
145 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
---|
146 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
---|
147 | * |
---|
148 | * If there is a FP coprocessor such as the i387 or mc68881, then |
---|
149 | * the answer is TRUE. |
---|
150 | * |
---|
151 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
---|
152 | * It indicates whether or not this CPU model has FP support. For |
---|
153 | * example, it would be possible to have an i386_nofp CPU model |
---|
154 | * which set this to false to indicate that you have an i386 without |
---|
155 | * an i387 and wish to leave floating point support out of RTEMS. |
---|
156 | */ |
---|
157 | |
---|
158 | #if ( PPC_HAS_FPU == 1 ) |
---|
159 | #define CPU_HARDWARE_FP TRUE |
---|
160 | #define CPU_SOFTWARE_FP FALSE |
---|
161 | #else |
---|
162 | #define CPU_HARDWARE_FP FALSE |
---|
163 | #define CPU_SOFTWARE_FP FALSE |
---|
164 | #endif |
---|
165 | |
---|
166 | /* |
---|
167 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
---|
168 | * |
---|
169 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
---|
170 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
---|
171 | * |
---|
172 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
---|
173 | * |
---|
174 | * PowerPC Note: It appears the GCC can implicitly generate FPU |
---|
175 | * and Altivec instructions when you least expect them. So make |
---|
176 | * all tasks floating point. |
---|
177 | */ |
---|
178 | |
---|
179 | #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
---|
180 | |
---|
181 | /* |
---|
182 | * Should the IDLE task have a floating point context? |
---|
183 | * |
---|
184 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
---|
185 | * and it has a floating point context which is switched in and out. |
---|
186 | * If FALSE, then the IDLE task does not have a floating point context. |
---|
187 | * |
---|
188 | * Setting this to TRUE negatively impacts the time required to preempt |
---|
189 | * the IDLE task from an interrupt because the floating point context |
---|
190 | * must be saved as part of the preemption. |
---|
191 | */ |
---|
192 | |
---|
193 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
194 | |
---|
195 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
---|
196 | |
---|
197 | /* |
---|
198 | * Processor defined structures required for cpukit/score. |
---|
199 | */ |
---|
200 | |
---|
201 | /* |
---|
202 | * Contexts |
---|
203 | * |
---|
204 | * Generally there are 2 types of context to save. |
---|
205 | * 1. Interrupt registers to save |
---|
206 | * 2. Task level registers to save |
---|
207 | * |
---|
208 | * This means we have the following 3 context items: |
---|
209 | * 1. task level context stuff:: Context_Control |
---|
210 | * 2. floating point task stuff:: Context_Control_fp |
---|
211 | * 3. special interrupt level context :: Context_Control_interrupt |
---|
212 | * |
---|
213 | * On some processors, it is cost-effective to save only the callee |
---|
214 | * preserved registers during a task context switch. This means |
---|
215 | * that the ISR code needs to save those registers which do not |
---|
216 | * persist across function calls. It is not mandatory to make this |
---|
217 | * distinctions between the caller/callee saves registers for the |
---|
218 | * purpose of minimizing context saved during task switch and on interrupts. |
---|
219 | * If the cost of saving extra registers is minimal, simplicity is the |
---|
220 | * choice. Save the same context on interrupt entry as for tasks in |
---|
221 | * this case. |
---|
222 | * |
---|
223 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
---|
224 | * care should be used in designing the context area. |
---|
225 | * |
---|
226 | * On some CPUs with hardware floating point support, the Context_Control_fp |
---|
227 | * structure will not be used or it simply consist of an array of a |
---|
228 | * fixed number of bytes. This is done when the floating point context |
---|
229 | * is dumped by a "FP save context" type instruction and the format |
---|
230 | * is not really defined by the CPU. In this case, there is no need |
---|
231 | * to figure out the exact format -- only the size. Of course, although |
---|
232 | * this is enough information for RTEMS, it is probably not enough for |
---|
233 | * a debugger such as gdb. But that is another problem. |
---|
234 | */ |
---|
235 | |
---|
236 | #ifndef __SPE__ |
---|
237 | #define PPC_GPR_TYPE uint32_t |
---|
238 | #define PPC_GPR_SIZE 4 |
---|
239 | #define PPC_GPR_LOAD lwz |
---|
240 | #define PPC_GPR_STORE stw |
---|
241 | #else |
---|
242 | #define PPC_GPR_TYPE uint64_t |
---|
243 | #define PPC_GPR_SIZE 8 |
---|
244 | #define PPC_GPR_LOAD evldd |
---|
245 | #define PPC_GPR_STORE evstdd |
---|
246 | #endif |
---|
247 | |
---|
248 | #ifndef ASM |
---|
249 | |
---|
250 | typedef struct { |
---|
251 | /* There is no CPU specific per-CPU state */ |
---|
252 | } CPU_Per_CPU_control; |
---|
253 | |
---|
254 | /* |
---|
255 | * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according |
---|
256 | * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - |
---|
257 | * Linux and Embedded") |
---|
258 | */ |
---|
259 | typedef struct { |
---|
260 | uint32_t gpr1; |
---|
261 | uint32_t msr; |
---|
262 | uint32_t lr; |
---|
263 | uint32_t cr; |
---|
264 | PPC_GPR_TYPE gpr14; |
---|
265 | PPC_GPR_TYPE gpr15; |
---|
266 | PPC_GPR_TYPE gpr16; |
---|
267 | PPC_GPR_TYPE gpr17; |
---|
268 | PPC_GPR_TYPE gpr18; |
---|
269 | PPC_GPR_TYPE gpr19; |
---|
270 | PPC_GPR_TYPE gpr20; |
---|
271 | PPC_GPR_TYPE gpr21; |
---|
272 | PPC_GPR_TYPE gpr22; |
---|
273 | PPC_GPR_TYPE gpr23; |
---|
274 | PPC_GPR_TYPE gpr24; |
---|
275 | PPC_GPR_TYPE gpr25; |
---|
276 | PPC_GPR_TYPE gpr26; |
---|
277 | PPC_GPR_TYPE gpr27; |
---|
278 | PPC_GPR_TYPE gpr28; |
---|
279 | PPC_GPR_TYPE gpr29; |
---|
280 | PPC_GPR_TYPE gpr30; |
---|
281 | PPC_GPR_TYPE gpr31; |
---|
282 | uint32_t gpr2; |
---|
283 | #if defined(PPC_MULTILIB_ALTIVEC) |
---|
284 | uint32_t reserved_for_alignment; |
---|
285 | uint8_t v20[16]; |
---|
286 | uint8_t v21[16]; |
---|
287 | uint8_t v22[16]; |
---|
288 | uint8_t v23[16]; |
---|
289 | uint8_t v24[16]; |
---|
290 | uint8_t v25[16]; |
---|
291 | uint8_t v26[16]; |
---|
292 | uint8_t v27[16]; |
---|
293 | uint8_t v28[16]; |
---|
294 | uint8_t v29[16]; |
---|
295 | uint8_t v30[16]; |
---|
296 | uint8_t v31[16]; |
---|
297 | uint32_t vrsave; |
---|
298 | #elif defined(__ALTIVEC__) |
---|
299 | /* |
---|
300 | * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave |
---|
301 | * and padding to ensure cache-alignment. Unfortunately, we can't verify |
---|
302 | * the cache line size here in the cpukit but altivec support code will |
---|
303 | * produce an error if this is ever different from 32 bytes. |
---|
304 | * |
---|
305 | * Note: it is the BSP/CPU-support's responsibility to save/restore |
---|
306 | * volatile vregs across interrupts and exceptions. |
---|
307 | */ |
---|
308 | uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; |
---|
309 | #endif |
---|
310 | #if defined(PPC_MULTILIB_FPU) |
---|
311 | double f14; |
---|
312 | double f15; |
---|
313 | double f16; |
---|
314 | double f17; |
---|
315 | double f18; |
---|
316 | double f19; |
---|
317 | double f20; |
---|
318 | double f21; |
---|
319 | double f22; |
---|
320 | double f23; |
---|
321 | double f24; |
---|
322 | double f25; |
---|
323 | double f26; |
---|
324 | double f27; |
---|
325 | double f28; |
---|
326 | double f29; |
---|
327 | double f30; |
---|
328 | double f31; |
---|
329 | #endif |
---|
330 | #if defined(RTEMS_SMP) |
---|
331 | /* |
---|
332 | * This item is at the structure end, so that we can use dcbz for the |
---|
333 | * previous items to optimize the context switch. We must not set this |
---|
334 | * item to zero via the dcbz. |
---|
335 | */ |
---|
336 | volatile uint32_t is_executing; |
---|
337 | #endif |
---|
338 | } ppc_context; |
---|
339 | |
---|
340 | typedef struct { |
---|
341 | uint8_t context [ |
---|
342 | PPC_DEFAULT_CACHE_LINE_SIZE |
---|
343 | + sizeof(ppc_context) |
---|
344 | + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 |
---|
345 | ? 0 |
---|
346 | : PPC_DEFAULT_CACHE_LINE_SIZE |
---|
347 | - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) |
---|
348 | ]; |
---|
349 | } Context_Control; |
---|
350 | |
---|
351 | static inline ppc_context *ppc_get_context( const Context_Control *context ) |
---|
352 | { |
---|
353 | uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; |
---|
354 | uintptr_t mask = clsz - 1; |
---|
355 | uintptr_t addr = (uintptr_t) context; |
---|
356 | |
---|
357 | return (ppc_context *) ((addr & ~mask) + clsz); |
---|
358 | } |
---|
359 | |
---|
360 | #define _CPU_Context_Get_SP( _context ) \ |
---|
361 | ppc_get_context(_context)->gpr1 |
---|
362 | |
---|
363 | #ifdef RTEMS_SMP |
---|
364 | static inline bool _CPU_Context_Get_is_executing( |
---|
365 | const Context_Control *context |
---|
366 | ) |
---|
367 | { |
---|
368 | return ppc_get_context(context)->is_executing; |
---|
369 | } |
---|
370 | |
---|
371 | static inline void _CPU_Context_Set_is_executing( |
---|
372 | Context_Control *context, |
---|
373 | bool is_executing |
---|
374 | ) |
---|
375 | { |
---|
376 | ppc_get_context(context)->is_executing = is_executing; |
---|
377 | } |
---|
378 | #endif |
---|
379 | #endif /* ASM */ |
---|
380 | |
---|
381 | #define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0) |
---|
382 | #define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) |
---|
383 | #define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8) |
---|
384 | #define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12) |
---|
385 | |
---|
386 | #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ |
---|
387 | (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16) |
---|
388 | |
---|
389 | #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) |
---|
390 | #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) |
---|
391 | #define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) |
---|
392 | #define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) |
---|
393 | #define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) |
---|
394 | #define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) |
---|
395 | #define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) |
---|
396 | #define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) |
---|
397 | #define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) |
---|
398 | #define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) |
---|
399 | #define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) |
---|
400 | #define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) |
---|
401 | #define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) |
---|
402 | #define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) |
---|
403 | #define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) |
---|
404 | #define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) |
---|
405 | #define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) |
---|
406 | #define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) |
---|
407 | #define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 ) |
---|
408 | |
---|
409 | #ifdef PPC_MULTILIB_ALTIVEC |
---|
410 | #define PPC_CONTEXT_OFFSET_V( v ) \ |
---|
411 | ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) |
---|
412 | #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) |
---|
413 | #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) |
---|
414 | #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) |
---|
415 | #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) |
---|
416 | #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) |
---|
417 | #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) |
---|
418 | #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) |
---|
419 | #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) |
---|
420 | #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) |
---|
421 | #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) |
---|
422 | #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) |
---|
423 | #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) |
---|
424 | #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) |
---|
425 | #define PPC_CONTEXT_OFFSET_F( f ) \ |
---|
426 | ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 ) |
---|
427 | #else |
---|
428 | #define PPC_CONTEXT_OFFSET_F( f ) \ |
---|
429 | ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) |
---|
430 | #endif |
---|
431 | |
---|
432 | #ifdef PPC_MULTILIB_FPU |
---|
433 | #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) |
---|
434 | #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) |
---|
435 | #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) |
---|
436 | #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) |
---|
437 | #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) |
---|
438 | #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) |
---|
439 | #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) |
---|
440 | #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) |
---|
441 | #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) |
---|
442 | #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) |
---|
443 | #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) |
---|
444 | #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) |
---|
445 | #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) |
---|
446 | #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) |
---|
447 | #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) |
---|
448 | #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) |
---|
449 | #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) |
---|
450 | #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) |
---|
451 | #endif |
---|
452 | |
---|
453 | #if defined(PPC_MULTILIB_FPU) |
---|
454 | #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) |
---|
455 | #elif defined(PPC_MULTILIB_ALTIVEC) |
---|
456 | #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) |
---|
457 | #else |
---|
458 | #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4) |
---|
459 | #endif |
---|
460 | |
---|
461 | #ifdef RTEMS_SMP |
---|
462 | #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE |
---|
463 | #endif |
---|
464 | |
---|
465 | #ifndef ASM |
---|
466 | typedef struct { |
---|
467 | #if (PPC_HAS_FPU == 1) |
---|
468 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
---|
469 | * procedure calls. However, this would mean that the interrupt |
---|
470 | * frame had to hold f0-f13, and the fpscr. And as the majority |
---|
471 | * of tasks will not have an FP context, we will save the whole |
---|
472 | * context here. |
---|
473 | */ |
---|
474 | #if (PPC_HAS_DOUBLE == 1) |
---|
475 | double f[32]; |
---|
476 | uint64_t fpscr; |
---|
477 | #else |
---|
478 | float f[32]; |
---|
479 | uint32_t fpscr; |
---|
480 | #endif |
---|
481 | #endif /* (PPC_HAS_FPU == 1) */ |
---|
482 | } Context_Control_fp; |
---|
483 | |
---|
484 | typedef struct CPU_Interrupt_frame { |
---|
485 | uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ |
---|
486 | uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ |
---|
487 | |
---|
488 | /* This is what is left out of the primary contexts */ |
---|
489 | uint32_t gpr0; |
---|
490 | uint32_t gpr2; /* play safe */ |
---|
491 | uint32_t gpr3; |
---|
492 | uint32_t gpr4; |
---|
493 | uint32_t gpr5; |
---|
494 | uint32_t gpr6; |
---|
495 | uint32_t gpr7; |
---|
496 | uint32_t gpr8; |
---|
497 | uint32_t gpr9; |
---|
498 | uint32_t gpr10; |
---|
499 | uint32_t gpr11; |
---|
500 | uint32_t gpr12; |
---|
501 | uint32_t gpr13; /* Play safe */ |
---|
502 | uint32_t gpr28; /* For internal use by the IRQ handler */ |
---|
503 | uint32_t gpr29; /* For internal use by the IRQ handler */ |
---|
504 | uint32_t gpr30; /* For internal use by the IRQ handler */ |
---|
505 | uint32_t gpr31; /* For internal use by the IRQ handler */ |
---|
506 | uint32_t cr; /* Bits of this are volatile, so no-one may save */ |
---|
507 | uint32_t ctr; |
---|
508 | uint32_t xer; |
---|
509 | uint32_t lr; |
---|
510 | uint32_t pc; |
---|
511 | uint32_t msr; |
---|
512 | uint32_t pad[3]; |
---|
513 | } CPU_Interrupt_frame; |
---|
514 | |
---|
515 | #endif /* ASM */ |
---|
516 | |
---|
517 | /* |
---|
518 | * Does the CPU follow the simple vectored interrupt model? |
---|
519 | * |
---|
520 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
---|
521 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
---|
522 | * table |
---|
523 | * |
---|
524 | * PowerPC Specific Information: |
---|
525 | * |
---|
526 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
---|
527 | * They do not use the simple vectored interrupt model. |
---|
528 | */ |
---|
529 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
---|
530 | |
---|
531 | /* |
---|
532 | * Does RTEMS manage a dedicated interrupt stack in software? |
---|
533 | * |
---|
534 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
---|
535 | * If FALSE, nothing is done. |
---|
536 | * |
---|
537 | * If the CPU supports a dedicated interrupt stack in hardware, |
---|
538 | * then it is generally the responsibility of the BSP to allocate it |
---|
539 | * and set it up. |
---|
540 | * |
---|
541 | * If the CPU does not support a dedicated interrupt stack, then |
---|
542 | * the porter has two options: (1) execute interrupts on the |
---|
543 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
---|
544 | * interrupt stack. |
---|
545 | * |
---|
546 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
547 | * |
---|
548 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
549 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
550 | * possible that both are FALSE for a particular CPU. Although it |
---|
551 | * is unclear what that would imply about the interrupt processing |
---|
552 | * procedure on that CPU. |
---|
553 | */ |
---|
554 | |
---|
555 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
---|
556 | |
---|
557 | /* |
---|
558 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
559 | * |
---|
560 | * If TRUE, then it must be installed during initialization. |
---|
561 | * If FALSE, then no installation is performed. |
---|
562 | * |
---|
563 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
564 | * |
---|
565 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
566 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
567 | * possible that both are FALSE for a particular CPU. Although it |
---|
568 | * is unclear what that would imply about the interrupt processing |
---|
569 | * procedure on that CPU. |
---|
570 | */ |
---|
571 | |
---|
572 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
---|
573 | |
---|
574 | /* |
---|
575 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
576 | * |
---|
577 | * If TRUE, then the memory is allocated during initialization. |
---|
578 | * If FALSE, then the memory is allocated during initialization. |
---|
579 | * |
---|
580 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
---|
581 | */ |
---|
582 | |
---|
583 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
---|
584 | |
---|
585 | /* |
---|
586 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
587 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
588 | * number (0)? |
---|
589 | */ |
---|
590 | |
---|
591 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
---|
592 | |
---|
593 | /* |
---|
594 | * Should the saving of the floating point registers be deferred |
---|
595 | * until a context switch is made to another different floating point |
---|
596 | * task? |
---|
597 | * |
---|
598 | * If TRUE, then the floating point context will not be stored until |
---|
599 | * necessary. It will remain in the floating point registers and not |
---|
600 | * disturned until another floating point task is switched to. |
---|
601 | * |
---|
602 | * If FALSE, then the floating point context is saved when a floating |
---|
603 | * point task is switched out and restored when the next floating point |
---|
604 | * task is restored. The state of the floating point registers between |
---|
605 | * those two operations is not specified. |
---|
606 | * |
---|
607 | * If the floating point context does NOT have to be saved as part of |
---|
608 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
609 | * |
---|
610 | * Setting this flag to TRUE results in using a different algorithm |
---|
611 | * for deciding when to save and restore the floating point context. |
---|
612 | * The deferred FP switch algorithm minimizes the number of times |
---|
613 | * the FP context is saved and restored. The FP context is not saved |
---|
614 | * until a context switch is made to another, different FP task. |
---|
615 | * Thus in a system with only one FP task, the FP context will never |
---|
616 | * be saved or restored. |
---|
617 | * |
---|
618 | * Note, however that compilers may use floating point registers/ |
---|
619 | * instructions for optimization or they may save/restore FP registers |
---|
620 | * on the stack. You must not use deferred switching in these cases |
---|
621 | * and on the PowerPC attempting to do so will raise a "FP unavailable" |
---|
622 | * exception. |
---|
623 | */ |
---|
624 | /* |
---|
625 | * ACB Note: This could make debugging tricky.. |
---|
626 | */ |
---|
627 | |
---|
628 | /* conservative setting (FALSE); probably doesn't affect performance too much */ |
---|
629 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
---|
630 | |
---|
631 | /* |
---|
632 | * Processor defined structures required for cpukit/score. |
---|
633 | */ |
---|
634 | |
---|
635 | #ifndef ASM |
---|
636 | |
---|
637 | /* |
---|
638 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
639 | * to generate an "uninitialized" FP context. It is filled in by |
---|
640 | * _CPU_Initialize and copied into the task's FP context area during |
---|
641 | * _CPU_Context_Initialize. |
---|
642 | */ |
---|
643 | |
---|
644 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
---|
645 | |
---|
646 | #endif /* ndef ASM */ |
---|
647 | |
---|
648 | /* |
---|
649 | * This defines the number of levels and the mask used to pick those |
---|
650 | * bits out of a thread mode. |
---|
651 | */ |
---|
652 | |
---|
653 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
---|
654 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
---|
655 | |
---|
656 | /* |
---|
657 | * The size of the floating point context area. On some CPUs this |
---|
658 | * will not be a "sizeof" because the format of the floating point |
---|
659 | * area is not defined -- only the size is. This is usually on |
---|
660 | * CPUs with a "floating point save context" instruction. |
---|
661 | */ |
---|
662 | |
---|
663 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
664 | |
---|
665 | /* |
---|
666 | * (Optional) # of bytes for libmisc/stackchk to check |
---|
667 | * If not specifed, then it defaults to something reasonable |
---|
668 | * for most architectures. |
---|
669 | */ |
---|
670 | |
---|
671 | #define CPU_STACK_CHECK_SIZE (128) |
---|
672 | |
---|
673 | /* |
---|
674 | * Amount of extra stack (above minimum stack size) required by |
---|
675 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
676 | * system this thread must exist and be able to process all directives. |
---|
677 | */ |
---|
678 | |
---|
679 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
680 | |
---|
681 | /* |
---|
682 | * This is defined if the port has a special way to report the ISR nesting |
---|
683 | * level. Most ports maintain the variable _ISR_Nest_level. Note that |
---|
684 | * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
---|
685 | * being maintained (e.g. watchdog queues). |
---|
686 | */ |
---|
687 | |
---|
688 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
689 | |
---|
690 | /* |
---|
691 | * ISR handler macros |
---|
692 | */ |
---|
693 | |
---|
694 | /* |
---|
695 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
696 | * level is returned in _isr_cookie. |
---|
697 | */ |
---|
698 | |
---|
699 | #ifndef ASM |
---|
700 | |
---|
701 | static inline uint32_t _CPU_ISR_Get_level( void ) |
---|
702 | { |
---|
703 | register unsigned int msr; |
---|
704 | _CPU_MSR_GET(msr); |
---|
705 | if (msr & MSR_EE) return 0; |
---|
706 | else return 1; |
---|
707 | } |
---|
708 | |
---|
709 | static inline void _CPU_ISR_Set_level( uint32_t level ) |
---|
710 | { |
---|
711 | register unsigned int msr; |
---|
712 | _CPU_MSR_GET(msr); |
---|
713 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
---|
714 | msr |= ppc_interrupt_get_disable_mask(); |
---|
715 | } |
---|
716 | else { |
---|
717 | msr &= ~ppc_interrupt_get_disable_mask(); |
---|
718 | } |
---|
719 | _CPU_MSR_SET(msr); |
---|
720 | } |
---|
721 | |
---|
722 | void BSP_panic(char *); |
---|
723 | |
---|
724 | /* Fatal Error manager macros */ |
---|
725 | |
---|
726 | /* |
---|
727 | * This routine copies _error into a known place -- typically a stack |
---|
728 | * location or a register, optionally disables interrupts, and |
---|
729 | * halts/stops the CPU. |
---|
730 | */ |
---|
731 | |
---|
732 | void _BSP_Fatal_error(unsigned int); |
---|
733 | |
---|
734 | #endif /* ASM */ |
---|
735 | |
---|
736 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
737 | _BSP_Fatal_error(_error) |
---|
738 | |
---|
739 | /* end of Fatal Error manager macros */ |
---|
740 | |
---|
741 | /* |
---|
742 | * Should be large enough to run all RTEMS tests. This ensures |
---|
743 | * that a "reasonable" small application should not have any problems. |
---|
744 | */ |
---|
745 | |
---|
746 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
---|
747 | |
---|
748 | #define CPU_SIZEOF_POINTER 4 |
---|
749 | |
---|
750 | /* |
---|
751 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
752 | * alignment does not take into account the requirements for the stack. |
---|
753 | */ |
---|
754 | |
---|
755 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
---|
756 | |
---|
757 | /* |
---|
758 | * This number corresponds to the byte alignment requirement for the |
---|
759 | * heap handler. This alignment requirement may be stricter than that |
---|
760 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
761 | * common for the heap to follow the same alignment requirement as |
---|
762 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
763 | * then this should be set to CPU_ALIGNMENT. |
---|
764 | * |
---|
765 | * NOTE: This does not have to be a power of 2. It does have to |
---|
766 | * be greater or equal to than CPU_ALIGNMENT. |
---|
767 | */ |
---|
768 | |
---|
769 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
---|
770 | |
---|
771 | /* |
---|
772 | * This number corresponds to the byte alignment requirement for memory |
---|
773 | * buffers allocated by the partition manager. This alignment requirement |
---|
774 | * may be stricter than that for the data types alignment specified by |
---|
775 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
776 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
777 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
778 | * |
---|
779 | * NOTE: This does not have to be a power of 2. It does have to |
---|
780 | * be greater or equal to than CPU_ALIGNMENT. |
---|
781 | */ |
---|
782 | |
---|
783 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
---|
784 | |
---|
785 | /* |
---|
786 | * This number corresponds to the byte alignment requirement for the |
---|
787 | * stack. This alignment requirement may be stricter than that for the |
---|
788 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
789 | * is strict enough for the stack, then this should be set to 0. |
---|
790 | * |
---|
791 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
792 | */ |
---|
793 | |
---|
794 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
---|
795 | |
---|
796 | #ifndef ASM |
---|
797 | /* The following routine swaps the endian format of an unsigned int. |
---|
798 | * It must be static because it is referenced indirectly. |
---|
799 | * |
---|
800 | * This version will work on any processor, but if there is a better |
---|
801 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
802 | * |
---|
803 | * swap least significant two bytes with 16-bit rotate |
---|
804 | * swap upper and lower 16-bits |
---|
805 | * swap most significant two bytes with 16-bit rotate |
---|
806 | * |
---|
807 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
808 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
809 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
810 | * that interrupts would probably have to be disabled to ensure that |
---|
811 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
812 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
813 | * endianness for ALL fetches -- both code and data -- so the code |
---|
814 | * will be fetched incorrectly. |
---|
815 | */ |
---|
816 | |
---|
817 | static inline uint32_t CPU_swap_u32( |
---|
818 | uint32_t value |
---|
819 | ) |
---|
820 | { |
---|
821 | uint32_t swapped; |
---|
822 | |
---|
823 | __asm__ volatile("rlwimi %0,%1,8,24,31;" |
---|
824 | "rlwimi %0,%1,24,16,23;" |
---|
825 | "rlwimi %0,%1,8,8,15;" |
---|
826 | "rlwimi %0,%1,24,0,7;" : |
---|
827 | "=&r" ((swapped)) : "r" ((value))); |
---|
828 | |
---|
829 | return( swapped ); |
---|
830 | } |
---|
831 | |
---|
832 | #define CPU_swap_u16( value ) \ |
---|
833 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
834 | |
---|
835 | typedef uint32_t CPU_Counter_ticks; |
---|
836 | |
---|
837 | static inline CPU_Counter_ticks _CPU_Counter_read( void ) |
---|
838 | { |
---|
839 | CPU_Counter_ticks value; |
---|
840 | |
---|
841 | #if defined(ppc8540) || defined(__PPC_CPU_E6500__) |
---|
842 | /* Use Alternate Time Base */ |
---|
843 | __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); |
---|
844 | #else |
---|
845 | __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); |
---|
846 | #endif |
---|
847 | |
---|
848 | return value; |
---|
849 | } |
---|
850 | |
---|
851 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
852 | CPU_Counter_ticks second, |
---|
853 | CPU_Counter_ticks first |
---|
854 | ) |
---|
855 | { |
---|
856 | return second - first; |
---|
857 | } |
---|
858 | |
---|
859 | #endif /* ASM */ |
---|
860 | |
---|
861 | |
---|
862 | #ifndef ASM |
---|
863 | /* Context handler macros */ |
---|
864 | |
---|
865 | /* |
---|
866 | * Initialize the context to a state suitable for starting a |
---|
867 | * task after a context restore operation. Generally, this |
---|
868 | * involves: |
---|
869 | * |
---|
870 | * - setting a starting address |
---|
871 | * - preparing the stack |
---|
872 | * - preparing the stack and frame pointers |
---|
873 | * - setting the proper interrupt level in the context |
---|
874 | * - initializing the floating point context |
---|
875 | * |
---|
876 | * This routine generally does not set any unnecessary register |
---|
877 | * in the context. The state of the "general data" registers is |
---|
878 | * undefined at task start time. |
---|
879 | */ |
---|
880 | |
---|
881 | void _CPU_Context_Initialize( |
---|
882 | Context_Control *the_context, |
---|
883 | uint32_t *stack_base, |
---|
884 | uint32_t size, |
---|
885 | uint32_t new_level, |
---|
886 | void *entry_point, |
---|
887 | bool is_fp, |
---|
888 | void *tls_area |
---|
889 | ); |
---|
890 | |
---|
891 | /* |
---|
892 | * This routine is responsible for somehow restarting the currently |
---|
893 | * executing task. If you are lucky, then all that is necessary |
---|
894 | * is restoring the context. Otherwise, there will need to be |
---|
895 | * a special assembly routine which does something special in this |
---|
896 | * case. Context_Restore should work most of the time. It will |
---|
897 | * not work if restarting self conflicts with the stack frame |
---|
898 | * assumptions of restoring a context. |
---|
899 | */ |
---|
900 | |
---|
901 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
902 | _CPU_Context_restore( (_the_context) ); |
---|
903 | |
---|
904 | /* |
---|
905 | * The purpose of this macro is to allow the initial pointer into |
---|
906 | * a floating point context area (used to save the floating point |
---|
907 | * context) to be at an arbitrary place in the floating point |
---|
908 | * context area. |
---|
909 | * |
---|
910 | * This is necessary because some FP units are designed to have |
---|
911 | * their context saved as a stack which grows into lower addresses. |
---|
912 | * Other FP units can be saved by simply moving registers into offsets |
---|
913 | * from the base of the context area. Finally some FP units provide |
---|
914 | * a "dump context" instruction which could fill in from high to low |
---|
915 | * or low to high based on the whim of the CPU designers. |
---|
916 | */ |
---|
917 | |
---|
918 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
919 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
920 | |
---|
921 | /* |
---|
922 | * This routine initializes the FP context area passed to it to. |
---|
923 | * There are a few standard ways in which to initialize the |
---|
924 | * floating point context. The code included for this macro assumes |
---|
925 | * that this is a CPU in which a "initial" FP context was saved into |
---|
926 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
927 | * context passed to it. |
---|
928 | * |
---|
929 | * Other models include (1) not doing anything, and (2) putting |
---|
930 | * a "null FP status word" in the correct place in the FP context. |
---|
931 | */ |
---|
932 | |
---|
933 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
934 | memset( *(_destination), 0, sizeof( **(_destination) ) ) |
---|
935 | |
---|
936 | /* end of Context handler macros */ |
---|
937 | #endif /* ASM */ |
---|
938 | |
---|
939 | #ifndef ASM |
---|
940 | /* Bitfield handler macros */ |
---|
941 | |
---|
942 | /* |
---|
943 | * This routine sets _output to the bit number of the first bit |
---|
944 | * set in _value. _value is of CPU dependent type Priority_bit_map_Word. |
---|
945 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
946 | * least significant bits will be used. |
---|
947 | * |
---|
948 | * There are a number of variables in using a "find first bit" type |
---|
949 | * instruction. |
---|
950 | * |
---|
951 | * (1) What happens when run on a value of zero? |
---|
952 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
953 | * (3) The numbering may be zero or one based. |
---|
954 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
955 | * |
---|
956 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
957 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
958 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
959 | * which must logically operate together. Bits in the _value are |
---|
960 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
961 | * The basic major and minor values calculated by _Priority_Major() |
---|
962 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
963 | * to properly range between the values returned by the "find first bit" |
---|
964 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
965 | * calculate the major and directly index into the minor table. |
---|
966 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
967 | * is the first bit found. |
---|
968 | * |
---|
969 | * This entire "find first bit" and mapping process depends heavily |
---|
970 | * on the manner in which a priority is broken into a major and minor |
---|
971 | * components with the major being the 4 MSB of a priority and minor |
---|
972 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
973 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
974 | * to the lowest priority. |
---|
975 | * |
---|
976 | * If your CPU does not have a "find first bit" instruction, then |
---|
977 | * there are ways to make do without it. Here are a handful of ways |
---|
978 | * to implement this in software: |
---|
979 | * |
---|
980 | * - a series of 16 bit test instructions |
---|
981 | * - a "binary search using if's" |
---|
982 | * - _number = 0 |
---|
983 | * if _value > 0x00ff |
---|
984 | * _value >>=8 |
---|
985 | * _number = 8; |
---|
986 | * |
---|
987 | * if _value > 0x0000f |
---|
988 | * _value >=8 |
---|
989 | * _number += 4 |
---|
990 | * |
---|
991 | * _number += bit_set_table[ _value ] |
---|
992 | * |
---|
993 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
994 | * bit set |
---|
995 | */ |
---|
996 | |
---|
997 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
998 | { \ |
---|
999 | __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
---|
1000 | "1" ((_value))); \ |
---|
1001 | } |
---|
1002 | |
---|
1003 | /* end of Bitfield handler macros */ |
---|
1004 | |
---|
1005 | /* |
---|
1006 | * This routine builds the mask which corresponds to the bit fields |
---|
1007 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
1008 | * for that routine. |
---|
1009 | */ |
---|
1010 | |
---|
1011 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
1012 | ( 0x80000000 >> (_bit_number) ) |
---|
1013 | |
---|
1014 | /* |
---|
1015 | * This routine translates the bit numbers returned by |
---|
1016 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
1017 | * a major or minor component of a priority. See the discussion |
---|
1018 | * for that routine. |
---|
1019 | */ |
---|
1020 | |
---|
1021 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
1022 | (_priority) |
---|
1023 | |
---|
1024 | /* end of Priority handler macros */ |
---|
1025 | #endif /* ASM */ |
---|
1026 | |
---|
1027 | /* functions */ |
---|
1028 | |
---|
1029 | #ifndef ASM |
---|
1030 | |
---|
1031 | /* |
---|
1032 | * _CPU_Initialize |
---|
1033 | * |
---|
1034 | * This routine performs CPU dependent initialization. |
---|
1035 | */ |
---|
1036 | |
---|
1037 | void _CPU_Initialize(void); |
---|
1038 | |
---|
1039 | /* |
---|
1040 | * _CPU_ISR_install_vector |
---|
1041 | * |
---|
1042 | * This routine installs an interrupt vector. |
---|
1043 | */ |
---|
1044 | |
---|
1045 | void _CPU_ISR_install_vector( |
---|
1046 | uint32_t vector, |
---|
1047 | proc_ptr new_handler, |
---|
1048 | proc_ptr *old_handler |
---|
1049 | ); |
---|
1050 | |
---|
1051 | /* |
---|
1052 | * _CPU_Context_switch |
---|
1053 | * |
---|
1054 | * This routine switches from the run context to the heir context. |
---|
1055 | */ |
---|
1056 | |
---|
1057 | void _CPU_Context_switch( |
---|
1058 | Context_Control *run, |
---|
1059 | Context_Control *heir |
---|
1060 | ); |
---|
1061 | |
---|
1062 | /* |
---|
1063 | * _CPU_Context_restore |
---|
1064 | * |
---|
1065 | * This routine is generallu used only to restart self in an |
---|
1066 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
1067 | * |
---|
1068 | * NOTE: May be unnecessary to reload some registers. |
---|
1069 | */ |
---|
1070 | |
---|
1071 | void _CPU_Context_restore( |
---|
1072 | Context_Control *new_context |
---|
1073 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
1074 | |
---|
1075 | /* |
---|
1076 | * _CPU_Context_save_fp |
---|
1077 | * |
---|
1078 | * This routine saves the floating point context passed to it. |
---|
1079 | */ |
---|
1080 | |
---|
1081 | void _CPU_Context_save_fp( |
---|
1082 | Context_Control_fp **fp_context_ptr |
---|
1083 | ); |
---|
1084 | |
---|
1085 | /* |
---|
1086 | * _CPU_Context_restore_fp |
---|
1087 | * |
---|
1088 | * This routine restores the floating point context passed to it. |
---|
1089 | */ |
---|
1090 | |
---|
1091 | void _CPU_Context_restore_fp( |
---|
1092 | Context_Control_fp **fp_context_ptr |
---|
1093 | ); |
---|
1094 | |
---|
1095 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
---|
1096 | |
---|
1097 | void _CPU_Context_validate( uintptr_t pattern ); |
---|
1098 | |
---|
1099 | #ifdef RTEMS_SMP |
---|
1100 | uint32_t _CPU_SMP_Initialize( void ); |
---|
1101 | |
---|
1102 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
---|
1103 | |
---|
1104 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
---|
1105 | |
---|
1106 | void _CPU_SMP_Prepare_start_multitasking( void ); |
---|
1107 | |
---|
1108 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
1109 | { |
---|
1110 | uint32_t pir; |
---|
1111 | |
---|
1112 | /* Use Book E Processor ID Register (PIR) */ |
---|
1113 | __asm__ volatile ( |
---|
1114 | "mfspr %[pir], 286" |
---|
1115 | : [pir] "=&r" (pir) |
---|
1116 | ); |
---|
1117 | |
---|
1118 | return pir; |
---|
1119 | } |
---|
1120 | |
---|
1121 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
1122 | |
---|
1123 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
1124 | { |
---|
1125 | __asm__ volatile ( "" : : : "memory" ); |
---|
1126 | } |
---|
1127 | |
---|
1128 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
1129 | { |
---|
1130 | __asm__ volatile ( "" : : : "memory" ); |
---|
1131 | } |
---|
1132 | #endif |
---|
1133 | |
---|
1134 | typedef struct { |
---|
1135 | uint32_t EXC_SRR0; |
---|
1136 | uint32_t EXC_SRR1; |
---|
1137 | uint32_t _EXC_number; |
---|
1138 | uint32_t EXC_CR; |
---|
1139 | uint32_t EXC_CTR; |
---|
1140 | uint32_t EXC_XER; |
---|
1141 | uint32_t EXC_LR; |
---|
1142 | #ifdef __SPE__ |
---|
1143 | uint32_t EXC_SPEFSCR; |
---|
1144 | uint64_t EXC_ACC; |
---|
1145 | #endif |
---|
1146 | PPC_GPR_TYPE GPR0; |
---|
1147 | PPC_GPR_TYPE GPR1; |
---|
1148 | PPC_GPR_TYPE GPR2; |
---|
1149 | PPC_GPR_TYPE GPR3; |
---|
1150 | PPC_GPR_TYPE GPR4; |
---|
1151 | PPC_GPR_TYPE GPR5; |
---|
1152 | PPC_GPR_TYPE GPR6; |
---|
1153 | PPC_GPR_TYPE GPR7; |
---|
1154 | PPC_GPR_TYPE GPR8; |
---|
1155 | PPC_GPR_TYPE GPR9; |
---|
1156 | PPC_GPR_TYPE GPR10; |
---|
1157 | PPC_GPR_TYPE GPR11; |
---|
1158 | PPC_GPR_TYPE GPR12; |
---|
1159 | PPC_GPR_TYPE GPR13; |
---|
1160 | PPC_GPR_TYPE GPR14; |
---|
1161 | PPC_GPR_TYPE GPR15; |
---|
1162 | PPC_GPR_TYPE GPR16; |
---|
1163 | PPC_GPR_TYPE GPR17; |
---|
1164 | PPC_GPR_TYPE GPR18; |
---|
1165 | PPC_GPR_TYPE GPR19; |
---|
1166 | PPC_GPR_TYPE GPR20; |
---|
1167 | PPC_GPR_TYPE GPR21; |
---|
1168 | PPC_GPR_TYPE GPR22; |
---|
1169 | PPC_GPR_TYPE GPR23; |
---|
1170 | PPC_GPR_TYPE GPR24; |
---|
1171 | PPC_GPR_TYPE GPR25; |
---|
1172 | PPC_GPR_TYPE GPR26; |
---|
1173 | PPC_GPR_TYPE GPR27; |
---|
1174 | PPC_GPR_TYPE GPR28; |
---|
1175 | PPC_GPR_TYPE GPR29; |
---|
1176 | PPC_GPR_TYPE GPR30; |
---|
1177 | PPC_GPR_TYPE GPR31; |
---|
1178 | #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU) |
---|
1179 | uint32_t reserved_for_alignment; |
---|
1180 | #endif |
---|
1181 | #ifdef PPC_MULTILIB_ALTIVEC |
---|
1182 | uint32_t VRSAVE; |
---|
1183 | |
---|
1184 | /* This field must take stvewx/lvewx requirements into account */ |
---|
1185 | uint32_t VSCR; |
---|
1186 | |
---|
1187 | uint8_t V0[16]; |
---|
1188 | uint8_t V1[16]; |
---|
1189 | uint8_t V2[16]; |
---|
1190 | uint8_t V3[16]; |
---|
1191 | uint8_t V4[16]; |
---|
1192 | uint8_t V5[16]; |
---|
1193 | uint8_t V6[16]; |
---|
1194 | uint8_t V7[16]; |
---|
1195 | uint8_t V8[16]; |
---|
1196 | uint8_t V9[16]; |
---|
1197 | uint8_t V10[16]; |
---|
1198 | uint8_t V11[16]; |
---|
1199 | uint8_t V12[16]; |
---|
1200 | uint8_t V13[16]; |
---|
1201 | uint8_t V14[16]; |
---|
1202 | uint8_t V15[16]; |
---|
1203 | uint8_t V16[16]; |
---|
1204 | uint8_t V17[16]; |
---|
1205 | uint8_t V18[16]; |
---|
1206 | uint8_t V19[16]; |
---|
1207 | uint8_t V20[16]; |
---|
1208 | uint8_t V21[16]; |
---|
1209 | uint8_t V22[16]; |
---|
1210 | uint8_t V23[16]; |
---|
1211 | uint8_t V24[16]; |
---|
1212 | uint8_t V25[16]; |
---|
1213 | uint8_t V26[16]; |
---|
1214 | uint8_t V27[16]; |
---|
1215 | uint8_t V28[16]; |
---|
1216 | uint8_t V29[16]; |
---|
1217 | uint8_t V30[16]; |
---|
1218 | uint8_t V31[16]; |
---|
1219 | #endif |
---|
1220 | #ifdef PPC_MULTILIB_FPU |
---|
1221 | double F0; |
---|
1222 | double F1; |
---|
1223 | double F2; |
---|
1224 | double F3; |
---|
1225 | double F4; |
---|
1226 | double F5; |
---|
1227 | double F6; |
---|
1228 | double F7; |
---|
1229 | double F8; |
---|
1230 | double F9; |
---|
1231 | double F10; |
---|
1232 | double F11; |
---|
1233 | double F12; |
---|
1234 | double F13; |
---|
1235 | double F14; |
---|
1236 | double F15; |
---|
1237 | double F16; |
---|
1238 | double F17; |
---|
1239 | double F18; |
---|
1240 | double F19; |
---|
1241 | double F20; |
---|
1242 | double F21; |
---|
1243 | double F22; |
---|
1244 | double F23; |
---|
1245 | double F24; |
---|
1246 | double F25; |
---|
1247 | double F26; |
---|
1248 | double F27; |
---|
1249 | double F28; |
---|
1250 | double F29; |
---|
1251 | double F30; |
---|
1252 | double F31; |
---|
1253 | uint64_t FPSCR; |
---|
1254 | #endif |
---|
1255 | } CPU_Exception_frame; |
---|
1256 | |
---|
1257 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
1258 | |
---|
1259 | /* |
---|
1260 | * _CPU_Initialize_altivec() |
---|
1261 | * |
---|
1262 | * Global altivec-related initialization. |
---|
1263 | */ |
---|
1264 | void |
---|
1265 | _CPU_Initialize_altivec(void); |
---|
1266 | |
---|
1267 | /* |
---|
1268 | * _CPU_Context_switch_altivec |
---|
1269 | * |
---|
1270 | * This routine switches the altivec contexts passed to it. |
---|
1271 | */ |
---|
1272 | |
---|
1273 | void |
---|
1274 | _CPU_Context_switch_altivec( |
---|
1275 | ppc_context *from, |
---|
1276 | ppc_context *to |
---|
1277 | ); |
---|
1278 | |
---|
1279 | /* |
---|
1280 | * _CPU_Context_restore_altivec |
---|
1281 | * |
---|
1282 | * This routine restores the altivec context passed to it. |
---|
1283 | */ |
---|
1284 | |
---|
1285 | void |
---|
1286 | _CPU_Context_restore_altivec( |
---|
1287 | ppc_context *ctxt |
---|
1288 | ); |
---|
1289 | |
---|
1290 | /* |
---|
1291 | * _CPU_Context_initialize_altivec |
---|
1292 | * |
---|
1293 | * This routine initializes the altivec context passed to it. |
---|
1294 | */ |
---|
1295 | |
---|
1296 | void |
---|
1297 | _CPU_Context_initialize_altivec( |
---|
1298 | ppc_context *ctxt |
---|
1299 | ); |
---|
1300 | |
---|
1301 | void _CPU_Fatal_error( |
---|
1302 | uint32_t _error |
---|
1303 | ); |
---|
1304 | |
---|
1305 | #endif /* ASM */ |
---|
1306 | |
---|
1307 | #ifdef __cplusplus |
---|
1308 | } |
---|
1309 | #endif |
---|
1310 | |
---|
1311 | #endif /* _RTEMS_SCORE_CPU_H */ |
---|