1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #ifndef _RTEMS_SCORE_CPU_H |
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10 | #define _RTEMS_SCORE_CPU_H |
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11 | |
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12 | #include <rtems/score/powerpc.h> /* pick up machine definitions */ |
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13 | #ifndef ASM |
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14 | #include <rtems/score/types.h> |
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15 | #endif |
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16 | |
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17 | /* conditional compilation parameters */ |
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18 | |
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19 | /* |
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20 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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21 | * |
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22 | * If TRUE, then they are inlined. |
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23 | * If FALSE, then a subroutine call is made. |
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24 | * |
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25 | * Basically this is an example of the classic trade-off of size |
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26 | * versus speed. Inlining the call (TRUE) typically increases the |
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27 | * size of RTEMS while speeding up the enabling of dispatching. |
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28 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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29 | * only be 0 or 1 unless you are in an interrupt handler and that |
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30 | * interrupt handler invokes the executive.] When not inlined |
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31 | * something calls _Thread_Enable_dispatch which in turns calls |
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32 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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33 | * one subroutine call is avoided entirely.] |
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34 | */ |
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35 | |
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36 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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37 | |
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38 | /* |
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39 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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40 | * be unrolled one time? In unrolled each iteration of the loop examines |
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41 | * two "nodes" on the chain being searched. Otherwise, only one node |
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42 | * is examined per iteration. |
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43 | * |
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44 | * If TRUE, then the loops are unrolled. |
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45 | * If FALSE, then the loops are not unrolled. |
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46 | * |
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47 | * The primary factor in making this decision is the cost of disabling |
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48 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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49 | * body of the loop. On some CPUs, the flash is more expensive than |
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50 | * one iteration of the loop body. In this case, it might be desirable |
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51 | * to unroll the loop. It is important to note that on some CPUs, this |
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52 | * code is the longest interrupt disable period in RTEMS. So it is |
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53 | * necessary to strike a balance when setting this parameter. |
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54 | */ |
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55 | |
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56 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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57 | |
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58 | /* |
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59 | * Processor defined structures required for cpukit/score. |
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60 | */ |
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61 | |
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62 | /* |
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63 | * Contexts |
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64 | * |
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65 | * Generally there are 2 types of context to save. |
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66 | * 1. Interrupt registers to save |
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67 | * 2. Task level registers to save |
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68 | * |
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69 | * This means we have the following 3 context items: |
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70 | * 1. task level context stuff:: Context_Control |
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71 | * 2. floating point task stuff:: Context_Control_fp |
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72 | * 3. special interrupt level context :: Context_Control_interrupt |
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73 | * |
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74 | * On some processors, it is cost-effective to save only the callee |
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75 | * preserved registers during a task context switch. This means |
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76 | * that the ISR code needs to save those registers which do not |
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77 | * persist across function calls. It is not mandatory to make this |
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78 | * distinctions between the caller/callee saves registers for the |
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79 | * purpose of minimizing context saved during task switch and on interrupts. |
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80 | * If the cost of saving extra registers is minimal, simplicity is the |
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81 | * choice. Save the same context on interrupt entry as for tasks in |
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82 | * this case. |
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83 | * |
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84 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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85 | * care should be used in designing the context area. |
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86 | * |
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87 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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88 | * structure will not be used or it simply consist of an array of a |
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89 | * fixed number of bytes. This is done when the floating point context |
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90 | * is dumped by a "FP save context" type instruction and the format |
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91 | * is not really defined by the CPU. In this case, there is no need |
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92 | * to figure out the exact format -- only the size. Of course, although |
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93 | * this is enough information for RTEMS, it is probably not enough for |
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94 | * a debugger such as gdb. But that is another problem. |
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95 | */ |
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96 | |
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97 | #ifndef ASM |
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98 | typedef struct { |
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99 | uint32_t gpr1; /* Stack pointer for all */ |
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100 | uint32_t gpr2; /* Reserved SVR4, section ptr EABI + */ |
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101 | uint32_t gpr13; /* Section ptr SVR4/EABI */ |
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102 | uint32_t gpr14; /* Non volatile for all */ |
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103 | uint32_t gpr15; /* Non volatile for all */ |
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104 | uint32_t gpr16; /* Non volatile for all */ |
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105 | uint32_t gpr17; /* Non volatile for all */ |
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106 | uint32_t gpr18; /* Non volatile for all */ |
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107 | uint32_t gpr19; /* Non volatile for all */ |
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108 | uint32_t gpr20; /* Non volatile for all */ |
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109 | uint32_t gpr21; /* Non volatile for all */ |
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110 | uint32_t gpr22; /* Non volatile for all */ |
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111 | uint32_t gpr23; /* Non volatile for all */ |
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112 | uint32_t gpr24; /* Non volatile for all */ |
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113 | uint32_t gpr25; /* Non volatile for all */ |
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114 | uint32_t gpr26; /* Non volatile for all */ |
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115 | uint32_t gpr27; /* Non volatile for all */ |
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116 | uint32_t gpr28; /* Non volatile for all */ |
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117 | uint32_t gpr29; /* Non volatile for all */ |
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118 | uint32_t gpr30; /* Non volatile for all */ |
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119 | uint32_t gpr31; /* Non volatile for all */ |
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120 | uint32_t cr; /* PART of the CR is non volatile for all */ |
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121 | uint32_t pc; /* Program counter/Link register */ |
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122 | uint32_t msr; /* Initial interrupt level */ |
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123 | } Context_Control; |
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124 | |
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125 | typedef struct { |
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126 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
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127 | * procedure calls. However, this would mean that the interrupt |
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128 | * frame had to hold f0-f13, and the fpscr. And as the majority |
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129 | * of tasks will not have an FP context, we will save the whole |
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130 | * context here. |
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131 | */ |
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132 | #if (PPC_HAS_DOUBLE == 1) |
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133 | double f[32]; |
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134 | double fpscr; |
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135 | #else |
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136 | float f[32]; |
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137 | float fpscr; |
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138 | #endif |
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139 | } Context_Control_fp; |
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140 | #endif /* ASM */ |
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141 | |
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142 | #ifndef ASM |
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143 | typedef struct CPU_Interrupt_frame { |
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144 | uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ |
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145 | uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ |
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146 | |
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147 | /* This is what is left out of the primary contexts */ |
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148 | uint32_t gpr0; |
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149 | uint32_t gpr2; /* play safe */ |
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150 | uint32_t gpr3; |
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151 | uint32_t gpr4; |
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152 | uint32_t gpr5; |
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153 | uint32_t gpr6; |
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154 | uint32_t gpr7; |
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155 | uint32_t gpr8; |
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156 | uint32_t gpr9; |
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157 | uint32_t gpr10; |
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158 | uint32_t gpr11; |
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159 | uint32_t gpr12; |
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160 | uint32_t gpr13; /* Play safe */ |
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161 | uint32_t gpr28; /* For internal use by the IRQ handler */ |
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162 | uint32_t gpr29; /* For internal use by the IRQ handler */ |
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163 | uint32_t gpr30; /* For internal use by the IRQ handler */ |
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164 | uint32_t gpr31; /* For internal use by the IRQ handler */ |
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165 | uint32_t cr; /* Bits of this are volatile, so no-one may save */ |
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166 | uint32_t ctr; |
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167 | uint32_t xer; |
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168 | uint32_t lr; |
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169 | uint32_t pc; |
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170 | uint32_t msr; |
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171 | uint32_t pad[3]; |
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172 | } CPU_Interrupt_frame; |
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173 | #endif /* ASM */ |
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174 | |
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175 | #ifdef _OLD_EXCEPTIONS |
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176 | #include <rtems/old-exceptions/cpu.h> |
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177 | #else |
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178 | #include <rtems/new-exceptions/cpu.h> |
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179 | #endif |
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180 | |
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181 | /* |
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182 | * Should be large enough to run all RTEMS tests. This insures |
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183 | * that a "reasonable" small application should not have any problems. |
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184 | */ |
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185 | |
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186 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
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187 | |
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188 | /* |
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189 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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190 | * alignment does not take into account the requirements for the stack. |
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191 | */ |
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192 | |
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193 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
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194 | |
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195 | /* |
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196 | * This number corresponds to the byte alignment requirement for the |
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197 | * heap handler. This alignment requirement may be stricter than that |
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198 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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199 | * common for the heap to follow the same alignment requirement as |
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200 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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201 | * then this should be set to CPU_ALIGNMENT. |
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202 | * |
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203 | * NOTE: This does not have to be a power of 2. It does have to |
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204 | * be greater or equal to than CPU_ALIGNMENT. |
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205 | */ |
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206 | |
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207 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
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208 | |
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209 | /* |
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210 | * This number corresponds to the byte alignment requirement for memory |
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211 | * buffers allocated by the partition manager. This alignment requirement |
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212 | * may be stricter than that for the data types alignment specified by |
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213 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
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214 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
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215 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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216 | * |
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217 | * NOTE: This does not have to be a power of 2. It does have to |
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218 | * be greater or equal to than CPU_ALIGNMENT. |
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219 | */ |
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220 | |
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221 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
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222 | |
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223 | /* |
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224 | * This number corresponds to the byte alignment requirement for the |
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225 | * stack. This alignment requirement may be stricter than that for the |
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226 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
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227 | * is strict enough for the stack, then this should be set to 0. |
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228 | * |
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229 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
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230 | */ |
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231 | |
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232 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
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233 | |
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234 | #ifndef ASM |
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235 | /* The following routine swaps the endian format of an unsigned int. |
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236 | * It must be static because it is referenced indirectly. |
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237 | * |
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238 | * This version will work on any processor, but if there is a better |
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239 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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240 | * |
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241 | * swap least significant two bytes with 16-bit rotate |
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242 | * swap upper and lower 16-bits |
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243 | * swap most significant two bytes with 16-bit rotate |
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244 | * |
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245 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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246 | * a single instruction (e.g. i486). It is probably best to avoid |
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247 | * an "endian swapping control bit" in the CPU. One good reason is |
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248 | * that interrupts would probably have to be disabled to insure that |
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249 | * an interrupt does not try to access the same "chunk" with the wrong |
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250 | * endian. Another good reason is that on some CPUs, the endian bit |
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251 | * endianness for ALL fetches -- both code and data -- so the code |
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252 | * will be fetched incorrectly. |
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253 | */ |
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254 | |
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255 | static inline uint32_t CPU_swap_u32( |
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256 | uint32_t value |
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257 | ) |
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258 | { |
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259 | uint32_t swapped; |
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260 | |
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261 | asm volatile("rlwimi %0,%1,8,24,31;" |
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262 | "rlwimi %0,%1,24,16,23;" |
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263 | "rlwimi %0,%1,8,8,15;" |
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264 | "rlwimi %0,%1,24,0,7;" : |
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265 | "=&r" ((swapped)) : "r" ((value))); |
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266 | |
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267 | return( swapped ); |
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268 | } |
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269 | |
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270 | #define CPU_swap_u16( value ) \ |
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271 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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272 | |
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273 | #endif /* ASM */ |
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274 | |
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275 | #ifndef ASM |
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276 | /* |
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277 | * Macros to access PowerPC specific additions to the CPU Table |
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278 | */ |
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279 | |
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280 | #define rtems_cpu_configuration_get_clicks_per_usec() \ |
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281 | (_CPU_Table.clicks_per_usec) |
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282 | |
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283 | #define rtems_cpu_configuration_get_exceptions_in_ram() \ |
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284 | (_CPU_Table.exceptions_in_RAM) |
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285 | |
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286 | #endif /* ASM */ |
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287 | |
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288 | #ifndef ASM |
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289 | /* |
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290 | * Simple spin delay in microsecond units for device drivers. |
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291 | * This is very dependent on the clock speed of the target. |
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292 | */ |
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293 | |
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294 | #define CPU_Get_timebase_low( _value ) \ |
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295 | asm volatile( "mftb %0" : "=r" (_value) ) |
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296 | |
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297 | #define rtems_bsp_delay( _microseconds ) \ |
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298 | do { \ |
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299 | uint32_t start, ticks, now; \ |
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300 | CPU_Get_timebase_low( start ) ; \ |
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301 | ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \ |
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302 | do \ |
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303 | CPU_Get_timebase_low( now ) ; \ |
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304 | while (now - start < ticks); \ |
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305 | } while (0) |
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306 | |
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307 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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308 | do { \ |
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309 | uint32_t start, now; \ |
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310 | CPU_Get_timebase_low( start ); \ |
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311 | do \ |
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312 | CPU_Get_timebase_low( now ); \ |
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313 | while (now - start < (_cycles)); \ |
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314 | } while (0) |
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315 | |
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316 | #endif /* ASM */ |
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317 | |
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318 | #ifndef ASM |
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319 | /* |
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320 | * Routines to access the decrementer register |
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321 | */ |
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322 | |
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323 | #define PPC_Set_decrementer( _clicks ) \ |
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324 | do { \ |
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325 | asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ |
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326 | } while (0) |
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327 | |
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328 | #define PPC_Get_decrementer( _clicks ) \ |
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329 | asm volatile( "mfdec %0" : "=r" (_clicks) ) |
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330 | |
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331 | #endif /* ASM */ |
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332 | |
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333 | #ifndef ASM |
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334 | /* |
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335 | * Routines to access the time base register |
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336 | */ |
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337 | |
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338 | static inline uint64_t PPC_Get_timebase_register( void ) |
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339 | { |
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340 | uint32_t tbr_low; |
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341 | uint32_t tbr_high; |
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342 | uint32_t tbr_high_old; |
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343 | uint64_t tbr; |
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344 | |
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345 | do { |
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346 | asm volatile( "mftbu %0" : "=r" (tbr_high_old)); |
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347 | asm volatile( "mftb %0" : "=r" (tbr_low)); |
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348 | asm volatile( "mftbu %0" : "=r" (tbr_high)); |
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349 | } while ( tbr_high_old != tbr_high ); |
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350 | |
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351 | tbr = tbr_high; |
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352 | tbr <<= 32; |
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353 | tbr |= tbr_low; |
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354 | return tbr; |
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355 | } |
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356 | |
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357 | static inline void PPC_Set_timebase_register (uint64_t tbr) |
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358 | { |
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359 | uint32_t tbr_low; |
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360 | uint32_t tbr_high; |
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361 | |
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362 | tbr_low = (tbr & 0xffffffff) ; |
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363 | tbr_high = (tbr >> 32) & 0xffffffff; |
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364 | asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); |
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365 | asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); |
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366 | |
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367 | } |
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368 | #endif /* ASM */ |
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369 | |
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370 | #ifndef ASM |
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371 | /* Context handler macros */ |
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372 | |
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373 | /* |
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374 | * Initialize the context to a state suitable for starting a |
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375 | * task after a context restore operation. Generally, this |
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376 | * involves: |
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377 | * |
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378 | * - setting a starting address |
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379 | * - preparing the stack |
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380 | * - preparing the stack and frame pointers |
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381 | * - setting the proper interrupt level in the context |
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382 | * - initializing the floating point context |
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383 | * |
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384 | * This routine generally does not set any unnecessary register |
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385 | * in the context. The state of the "general data" registers is |
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386 | * undefined at task start time. |
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387 | */ |
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388 | |
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389 | void _CPU_Context_Initialize( |
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390 | Context_Control *the_context, |
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391 | uint32_t *stack_base, |
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392 | uint32_t size, |
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393 | uint32_t new_level, |
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394 | void *entry_point, |
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395 | boolean is_fp |
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396 | ); |
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397 | |
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398 | /* |
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399 | * This routine is responsible for somehow restarting the currently |
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400 | * executing task. If you are lucky, then all that is necessary |
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401 | * is restoring the context. Otherwise, there will need to be |
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402 | * a special assembly routine which does something special in this |
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403 | * case. Context_Restore should work most of the time. It will |
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404 | * not work if restarting self conflicts with the stack frame |
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405 | * assumptions of restoring a context. |
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406 | */ |
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407 | |
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408 | #define _CPU_Context_Restart_self( _the_context ) \ |
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409 | _CPU_Context_restore( (_the_context) ); |
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410 | |
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411 | /* |
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412 | * The purpose of this macro is to allow the initial pointer into |
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413 | * a floating point context area (used to save the floating point |
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414 | * context) to be at an arbitrary place in the floating point |
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415 | * context area. |
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416 | * |
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417 | * This is necessary because some FP units are designed to have |
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418 | * their context saved as a stack which grows into lower addresses. |
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419 | * Other FP units can be saved by simply moving registers into offsets |
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420 | * from the base of the context area. Finally some FP units provide |
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421 | * a "dump context" instruction which could fill in from high to low |
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422 | * or low to high based on the whim of the CPU designers. |
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423 | */ |
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424 | |
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425 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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426 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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427 | |
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428 | /* |
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429 | * This routine initializes the FP context area passed to it to. |
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430 | * There are a few standard ways in which to initialize the |
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431 | * floating point context. The code included for this macro assumes |
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432 | * that this is a CPU in which a "initial" FP context was saved into |
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433 | * _CPU_Null_fp_context and it simply copies it to the destination |
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434 | * context passed to it. |
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435 | * |
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436 | * Other models include (1) not doing anything, and (2) putting |
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437 | * a "null FP status word" in the correct place in the FP context. |
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438 | */ |
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439 | |
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440 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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441 | { \ |
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442 | ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \ |
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443 | } |
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444 | |
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445 | /* end of Context handler macros */ |
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446 | #endif /* ASM */ |
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447 | |
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448 | #ifndef ASM |
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449 | /* Bitfield handler macros */ |
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450 | |
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451 | /* |
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452 | * This routine sets _output to the bit number of the first bit |
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453 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
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454 | * This type may be either 16 or 32 bits wide although only the 16 |
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455 | * least significant bits will be used. |
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456 | * |
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457 | * There are a number of variables in using a "find first bit" type |
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458 | * instruction. |
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459 | * |
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460 | * (1) What happens when run on a value of zero? |
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461 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
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462 | * (3) The numbering may be zero or one based. |
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463 | * (4) The "find first bit" instruction may search from MSB or LSB. |
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464 | * |
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465 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
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466 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
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467 | * _CPU_Priority_Bits_index(). These three form a set of routines |
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468 | * which must logically operate together. Bits in the _value are |
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469 | * set and cleared based on masks built by _CPU_Priority_mask(). |
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470 | * The basic major and minor values calculated by _Priority_Major() |
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471 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
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472 | * to properly range between the values returned by the "find first bit" |
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473 | * instruction. This makes it possible for _Priority_Get_highest() to |
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474 | * calculate the major and directly index into the minor table. |
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475 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
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476 | * is the first bit found. |
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477 | * |
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478 | * This entire "find first bit" and mapping process depends heavily |
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479 | * on the manner in which a priority is broken into a major and minor |
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480 | * components with the major being the 4 MSB of a priority and minor |
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481 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
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482 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
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483 | * to the lowest priority. |
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484 | * |
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485 | * If your CPU does not have a "find first bit" instruction, then |
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486 | * there are ways to make do without it. Here are a handful of ways |
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487 | * to implement this in software: |
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488 | * |
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489 | * - a series of 16 bit test instructions |
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490 | * - a "binary search using if's" |
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491 | * - _number = 0 |
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492 | * if _value > 0x00ff |
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493 | * _value >>=8 |
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494 | * _number = 8; |
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495 | * |
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496 | * if _value > 0x0000f |
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497 | * _value >=8 |
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498 | * _number += 4 |
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499 | * |
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500 | * _number += bit_set_table[ _value ] |
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501 | * |
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502 | * where bit_set_table[ 16 ] has values which indicate the first |
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503 | * bit set |
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504 | */ |
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505 | |
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506 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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507 | { \ |
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508 | asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
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509 | "1" ((_value))); \ |
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510 | } |
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511 | |
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512 | /* end of Bitfield handler macros */ |
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513 | |
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514 | /* |
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515 | * This routine builds the mask which corresponds to the bit fields |
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516 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
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517 | * for that routine. |
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518 | */ |
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519 | |
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520 | #define _CPU_Priority_Mask( _bit_number ) \ |
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521 | ( 0x80000000 >> (_bit_number) ) |
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522 | |
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523 | /* |
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524 | * This routine translates the bit numbers returned by |
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525 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
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526 | * a major or minor component of a priority. See the discussion |
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527 | * for that routine. |
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528 | */ |
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529 | |
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530 | #define _CPU_Priority_bits_index( _priority ) \ |
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531 | (_priority) |
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532 | |
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533 | /* end of Priority handler macros */ |
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534 | #endif /* ASM */ |
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535 | |
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536 | /* functions */ |
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537 | |
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538 | #ifndef ASM |
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539 | |
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540 | /* |
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541 | * _CPU_Initialize |
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542 | * |
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543 | * This routine performs CPU dependent initialization. |
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544 | */ |
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545 | |
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546 | void _CPU_Initialize( |
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547 | rtems_cpu_table *cpu_table, |
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548 | void (*thread_dispatch) |
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549 | ); |
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550 | |
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551 | /* |
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552 | * _CPU_ISR_install_vector |
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553 | * |
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554 | * This routine installs an interrupt vector. |
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555 | */ |
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556 | |
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557 | void _CPU_ISR_install_vector( |
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558 | uint32_t vector, |
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559 | proc_ptr new_handler, |
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560 | proc_ptr *old_handler |
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561 | ); |
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562 | |
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563 | /* |
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564 | * _CPU_Install_interrupt_stack |
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565 | * |
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566 | * This routine installs the hardware interrupt stack pointer. |
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567 | * |
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568 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
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569 | * is TRUE. |
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570 | */ |
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571 | |
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572 | void _CPU_Install_interrupt_stack( void ); |
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573 | |
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574 | /* |
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575 | * _CPU_Context_switch |
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576 | * |
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577 | * This routine switches from the run context to the heir context. |
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578 | */ |
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579 | |
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580 | void _CPU_Context_switch( |
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581 | Context_Control *run, |
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582 | Context_Control *heir |
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583 | ); |
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584 | |
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585 | /* |
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586 | * _CPU_Context_restore |
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587 | * |
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588 | * This routine is generallu used only to restart self in an |
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589 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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590 | * |
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591 | * NOTE: May be unnecessary to reload some registers. |
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592 | */ |
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593 | |
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594 | void _CPU_Context_restore( |
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595 | Context_Control *new_context |
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596 | ); |
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597 | |
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598 | /* |
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599 | * _CPU_Context_save_fp |
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600 | * |
---|
601 | * This routine saves the floating point context passed to it. |
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602 | */ |
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603 | |
---|
604 | void _CPU_Context_save_fp( |
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605 | void **fp_context_ptr |
---|
606 | ); |
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607 | |
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608 | /* |
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609 | * _CPU_Context_restore_fp |
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610 | * |
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611 | * This routine restores the floating point context passed to it. |
---|
612 | */ |
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613 | |
---|
614 | void _CPU_Context_restore_fp( |
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615 | void **fp_context_ptr |
---|
616 | ); |
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617 | |
---|
618 | void _CPU_Fatal_error( |
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619 | uint32_t _error |
---|
620 | ); |
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621 | |
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622 | #endif /* ASM */ |
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623 | |
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624 | #endif /* _RTEMS_SCORE_CPU_H */ |
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