source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ 5d42c1b7

4.104.114.9
Last change on this file since 5d42c1b7 was 5d42c1b7, checked in by Ralf Corsepius <ralf.corsepius@…>, on Sep 5, 2008 at 2:00:15 AM

Convert to "bool".

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File size: 23.8 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 * $Id$
14 */
15 
16#ifndef _RTEMS_SCORE_CPU_H
17#define _RTEMS_SCORE_CPU_H
18
19#include <rtems/score/powerpc.h>              /* pick up machine definitions */
20#ifndef ASM
21#include <rtems/score/types.h>
22#endif
23
24/* conditional compilation parameters */
25
26/*
27 *  Should the calls to _Thread_Enable_dispatch be inlined?
28 *
29 *  If TRUE, then they are inlined.
30 *  If FALSE, then a subroutine call is made.
31 *
32 *  Basically this is an example of the classic trade-off of size
33 *  versus speed.  Inlining the call (TRUE) typically increases the
34 *  size of RTEMS while speeding up the enabling of dispatching.
35 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
36 *  only be 0 or 1 unless you are in an interrupt handler and that
37 *  interrupt handler invokes the executive.]  When not inlined
38 *  something calls _Thread_Enable_dispatch which in turns calls
39 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
40 *  one subroutine call is avoided entirely.]
41 */
42
43#define CPU_INLINE_ENABLE_DISPATCH       FALSE
44
45/*
46 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
47 *  be unrolled one time?  In unrolled each iteration of the loop examines
48 *  two "nodes" on the chain being searched.  Otherwise, only one node
49 *  is examined per iteration.
50 *
51 *  If TRUE, then the loops are unrolled.
52 *  If FALSE, then the loops are not unrolled.
53 *
54 *  The primary factor in making this decision is the cost of disabling
55 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
56 *  body of the loop.  On some CPUs, the flash is more expensive than
57 *  one iteration of the loop body.  In this case, it might be desirable
58 *  to unroll the loop.  It is important to note that on some CPUs, this
59 *  code is the longest interrupt disable period in RTEMS.  So it is
60 *  necessary to strike a balance when setting this parameter.
61 */
62
63#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
64
65/*
66 *  Does this port provide a CPU dependent IDLE task implementation?
67 *
68 *  If TRUE, then the routine _CPU_Thread_Idle_body
69 *  must be provided and is the default IDLE thread body instead of
70 *  _CPU_Thread_Idle_body.
71 *
72 *  If FALSE, then use the generic IDLE thread body if the BSP does
73 *  not provide one.
74 *
75 *  This is intended to allow for supporting processors which have
76 *  a low power or idle mode.  When the IDLE thread is executed, then
77 *  the CPU can be powered down.
78 *
79 *  The order of precedence for selecting the IDLE thread body is:
80 *
81 *    1.  BSP provided
82 *    2.  CPU dependent (if provided)
83 *    3.  generic (if no BSP and no CPU dependent)
84 */
85
86#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
87
88/*
89 *  Does the stack grow up (toward higher addresses) or down
90 *  (toward lower addresses)?
91 *
92 *  If TRUE, then the grows upward.
93 *  If FALSE, then the grows toward smaller addresses.
94 */
95
96#define CPU_STACK_GROWS_UP               FALSE
97
98/*
99 *  The following is the variable attribute used to force alignment
100 *  of critical RTEMS structures.  On some processors it may make
101 *  sense to have these aligned on tighter boundaries than
102 *  the minimum requirements of the compiler in order to have as
103 *  much of the critical data area as possible in a cache line.
104 *
105 *  The placement of this macro in the declaration of the variables
106 *  is based on the syntactically requirements of the GNU C
107 *  "__attribute__" extension.  For example with GNU C, use
108 *  the following to force a structures to a 32 byte boundary.
109 *
110 *      __attribute__ ((aligned (32)))
111 *
112 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
113 *         To benefit from using this, the data must be heavily
114 *         used so it will stay in the cache and used frequently enough
115 *         in the executive to justify turning this on.
116 */
117
118#define CPU_STRUCTURE_ALIGNMENT \
119  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
120
121/*
122 *  Define what is required to specify how the network to host conversion
123 *  routines are handled.
124 */
125
126#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
127#define CPU_BIG_ENDIAN                           TRUE
128#define CPU_LITTLE_ENDIAN                        FALSE
129#else
130#define CPU_BIG_ENDIAN                           FALSE
131#define CPU_LITTLE_ENDIAN                        TRUE
132#endif
133
134/*
135 *  Does the CPU have hardware floating point?
136 *
137 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
138 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
139 *
140 *  If there is a FP coprocessor such as the i387 or mc68881, then
141 *  the answer is TRUE.
142 *
143 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
144 *  It indicates whether or not this CPU model has FP support.  For
145 *  example, it would be possible to have an i386_nofp CPU model
146 *  which set this to false to indicate that you have an i386 without
147 *  an i387 and wish to leave floating point support out of RTEMS.
148 */
149
150#if ( PPC_HAS_FPU == 1 )
151#define CPU_HARDWARE_FP     TRUE
152#define CPU_SOFTWARE_FP     FALSE
153#else
154#define CPU_HARDWARE_FP     FALSE
155#define CPU_SOFTWARE_FP     FALSE
156#endif
157
158/*
159 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
160 *
161 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
162 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
163 *
164 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
165 *
166 *  PowerPC Note: It appears the GCC can implicitly generate FPU
167 *  and Altivec instructions when you least expect them.  So make
168 *  all tasks floating point.
169 */
170
171#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
172
173/*
174 *  Should the IDLE task have a floating point context?
175 *
176 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
177 *  and it has a floating point context which is switched in and out.
178 *  If FALSE, then the IDLE task does not have a floating point context.
179 *
180 *  Setting this to TRUE negatively impacts the time required to preempt
181 *  the IDLE task from an interrupt because the floating point context
182 *  must be saved as part of the preemption.
183 */
184
185#define CPU_IDLE_TASK_IS_FP      FALSE
186
187/*
188 *  Processor defined structures required for cpukit/score.
189 */
190
191/*
192 * Contexts
193 *
194 *  Generally there are 2 types of context to save.
195 *     1. Interrupt registers to save
196 *     2. Task level registers to save
197 *
198 *  This means we have the following 3 context items:
199 *     1. task level context stuff::  Context_Control
200 *     2. floating point task stuff:: Context_Control_fp
201 *     3. special interrupt level context :: Context_Control_interrupt
202 *
203 *  On some processors, it is cost-effective to save only the callee
204 *  preserved registers during a task context switch.  This means
205 *  that the ISR code needs to save those registers which do not
206 *  persist across function calls.  It is not mandatory to make this
207 *  distinctions between the caller/callee saves registers for the
208 *  purpose of minimizing context saved during task switch and on interrupts.
209 *  If the cost of saving extra registers is minimal, simplicity is the
210 *  choice.  Save the same context on interrupt entry as for tasks in
211 *  this case.
212 *
213 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
214 *  care should be used in designing the context area.
215 *
216 *  On some CPUs with hardware floating point support, the Context_Control_fp
217 *  structure will not be used or it simply consist of an array of a
218 *  fixed number of bytes.   This is done when the floating point context
219 *  is dumped by a "FP save context" type instruction and the format
220 *  is not really defined by the CPU.  In this case, there is no need
221 *  to figure out the exact format -- only the size.  Of course, although
222 *  this is enough information for RTEMS, it is probably not enough for
223 *  a debugger such as gdb.  But that is another problem.
224 */
225
226#ifndef ASM
227typedef struct {
228    uint32_t   gpr1;    /* Stack pointer for all */
229    uint32_t   gpr2;    /* Reserved SVR4, section ptr EABI + */
230    uint32_t   gpr13;   /* Section ptr SVR4/EABI */
231    uint32_t   gpr14;   /* Non volatile for all */
232    uint32_t   gpr15;   /* Non volatile for all */
233    uint32_t   gpr16;   /* Non volatile for all */
234    uint32_t   gpr17;   /* Non volatile for all */
235    uint32_t   gpr18;   /* Non volatile for all */
236    uint32_t   gpr19;   /* Non volatile for all */
237    uint32_t   gpr20;   /* Non volatile for all */
238    uint32_t   gpr21;   /* Non volatile for all */
239    uint32_t   gpr22;   /* Non volatile for all */
240    uint32_t   gpr23;   /* Non volatile for all */
241    uint32_t   gpr24;   /* Non volatile for all */
242    uint32_t   gpr25;   /* Non volatile for all */
243    uint32_t   gpr26;   /* Non volatile for all */
244    uint32_t   gpr27;   /* Non volatile for all */
245    uint32_t   gpr28;   /* Non volatile for all */
246    uint32_t   gpr29;   /* Non volatile for all */
247    uint32_t   gpr30;   /* Non volatile for all */
248    uint32_t   gpr31;   /* Non volatile for all */
249    uint32_t   cr;      /* PART of the CR is non volatile for all */
250    uint32_t   pc;      /* Program counter/Link register */
251    uint32_t   msr;     /* Initial interrupt level */
252} Context_Control;
253
254#define _CPU_Context_Get_SP( _context ) \
255  (_context)->gpr1
256
257typedef struct {
258    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
259     * procedure calls.  However, this would mean that the interrupt
260     * frame had to hold f0-f13, and the fpscr.  And as the majority
261     * of tasks will not have an FP context, we will save the whole
262     * context here.
263     */
264#if (PPC_HAS_DOUBLE == 1)
265    double      f[32];
266    double      fpscr;
267#else
268    float       f[32];
269    float       fpscr;
270#endif
271} Context_Control_fp;
272#endif /* ASM */
273
274#ifndef ASM
275typedef struct CPU_Interrupt_frame {
276    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
277    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
278
279    /* This is what is left out of the primary contexts */
280    uint32_t   gpr0;
281    uint32_t   gpr2;            /* play safe */
282    uint32_t   gpr3;
283    uint32_t   gpr4;
284    uint32_t   gpr5;
285    uint32_t   gpr6;
286    uint32_t   gpr7;
287    uint32_t   gpr8;
288    uint32_t   gpr9;
289    uint32_t   gpr10;
290    uint32_t   gpr11;
291    uint32_t   gpr12;
292    uint32_t   gpr13;   /* Play safe */
293    uint32_t   gpr28;   /* For internal use by the IRQ handler */
294    uint32_t   gpr29;   /* For internal use by the IRQ handler */
295    uint32_t   gpr30;   /* For internal use by the IRQ handler */
296    uint32_t   gpr31;   /* For internal use by the IRQ handler */
297    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
298    uint32_t   ctr;
299    uint32_t   xer;
300    uint32_t   lr;
301    uint32_t   pc;
302    uint32_t   msr;
303    uint32_t   pad[3];
304} CPU_Interrupt_frame;
305#endif /* ASM */
306
307#include <rtems/new-exceptions/cpu.h>
308
309/*
310 *  Should be large enough to run all RTEMS tests.  This ensures
311 *  that a "reasonable" small application should not have any problems.
312 */
313
314#define CPU_STACK_MINIMUM_SIZE          (1024*8)
315
316/*
317 *  CPU's worst alignment requirement for data types on a byte boundary.  This
318 *  alignment does not take into account the requirements for the stack.
319 */
320
321#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
322
323/*
324 *  This number corresponds to the byte alignment requirement for the
325 *  heap handler.  This alignment requirement may be stricter than that
326 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
327 *  common for the heap to follow the same alignment requirement as
328 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
329 *  then this should be set to CPU_ALIGNMENT.
330 *
331 *  NOTE:  This does not have to be a power of 2.  It does have to
332 *         be greater or equal to than CPU_ALIGNMENT.
333 */
334
335#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
336
337/*
338 *  This number corresponds to the byte alignment requirement for memory
339 *  buffers allocated by the partition manager.  This alignment requirement
340 *  may be stricter than that for the data types alignment specified by
341 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
342 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
343 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
344 *
345 *  NOTE:  This does not have to be a power of 2.  It does have to
346 *         be greater or equal to than CPU_ALIGNMENT.
347 */
348
349#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
350
351/*
352 *  This number corresponds to the byte alignment requirement for the
353 *  stack.  This alignment requirement may be stricter than that for the
354 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
355 *  is strict enough for the stack, then this should be set to 0.
356 *
357 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
358 */
359
360#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
361
362#ifndef ASM
363/*  The following routine swaps the endian format of an unsigned int.
364 *  It must be static because it is referenced indirectly.
365 *
366 *  This version will work on any processor, but if there is a better
367 *  way for your CPU PLEASE use it.  The most common way to do this is to:
368 *
369 *     swap least significant two bytes with 16-bit rotate
370 *     swap upper and lower 16-bits
371 *     swap most significant two bytes with 16-bit rotate
372 *
373 *  Some CPUs have special instructions which swap a 32-bit quantity in
374 *  a single instruction (e.g. i486).  It is probably best to avoid
375 *  an "endian swapping control bit" in the CPU.  One good reason is
376 *  that interrupts would probably have to be disabled to ensure that
377 *  an interrupt does not try to access the same "chunk" with the wrong
378 *  endian.  Another good reason is that on some CPUs, the endian bit
379 *  endianness for ALL fetches -- both code and data -- so the code
380 *  will be fetched incorrectly.
381 */
382 
383static inline uint32_t CPU_swap_u32(
384  uint32_t value
385)
386{
387  uint32_t   swapped;
388 
389  asm volatile("rlwimi %0,%1,8,24,31;"
390               "rlwimi %0,%1,24,16,23;"
391               "rlwimi %0,%1,8,8,15;"
392               "rlwimi %0,%1,24,0,7;" :
393               "=&r" ((swapped)) : "r" ((value)));
394
395  return( swapped );
396}
397
398#define CPU_swap_u16( value ) \
399  (((value&0xff) << 8) | ((value >> 8)&0xff))
400
401#endif /* ASM */
402
403#ifndef ASM
404/*
405 *  Simple spin delay in microsecond units for device drivers.
406 *  This is very dependent on the clock speed of the target.
407 */
408
409#if 0
410/* Wonderful bookE doesn't have mftb/mftbu; they only
411 * define the TBRU/TBRL SPRs so we use these. Luckily,
412 * we run in supervisory mode so that should work on
413 * all CPUs. In user mode we'd have a problem...
414 * 2007/11/30, T.S.
415 *
416 * OTOH, PSIM currently lacks support for reading
417 * SPRs 268/269. You need GDB patch sim/2376 to avoid
418 * a crash...
419 */
420#define CPU_Get_timebase_low( _value ) \
421    asm volatile( "mftb  %0" : "=r" (_value) )
422#else
423#define CPU_Get_timebase_low( _value ) \
424    asm volatile( "mfspr %0,268" : "=r" (_value) )
425#endif
426
427#define rtems_bsp_delay( _microseconds ) \
428  do { \
429    uint32_t   start, ticks, now; \
430    extern     uint32_t bsp_clicks_per_usec; \
431    CPU_Get_timebase_low( start ) ; \
432    ticks = (_microseconds) * bsp_clicks_per_usec; \
433    do \
434      CPU_Get_timebase_low( now ) ; \
435    while (now - start < ticks); \
436  } while (0)
437
438#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
439  do { \
440    uint32_t   start, now; \
441    CPU_Get_timebase_low( start ); \
442    do \
443      CPU_Get_timebase_low( now ); \
444    while (now - start < (_cycles)); \
445  } while (0)
446
447#endif /* ASM */
448
449#ifndef ASM
450/*
451 *  Routines to access the decrementer register
452 */
453
454#define PPC_Set_decrementer( _clicks ) \
455  do { \
456    asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
457  } while (0)
458
459#define PPC_Get_decrementer( _clicks ) \
460    asm volatile( "mfdec  %0" : "=r" (_clicks) )
461
462#endif /* ASM */
463
464#ifndef ASM
465/*
466 *  Routines to access the time base register
467 */
468
469static inline uint64_t PPC_Get_timebase_register( void )
470{
471  uint32_t tbr_low;
472  uint32_t tbr_high;
473  uint32_t tbr_high_old;
474  uint64_t tbr;
475
476  do {
477#if 0
478/* See comment above (CPU_Get_timebase_low) */
479    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
480    asm volatile( "mftb  %0" : "=r" (tbr_low));
481    asm volatile( "mftbu %0" : "=r" (tbr_high));
482#else
483    asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
484    asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
485    asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
486#endif
487  } while ( tbr_high_old != tbr_high );
488
489  tbr = tbr_high;
490  tbr <<= 32;
491  tbr |= tbr_low;
492  return tbr;
493}
494
495static inline  void PPC_Set_timebase_register (uint64_t tbr)
496{
497  uint32_t tbr_low;
498  uint32_t tbr_high;
499
500  tbr_low = (tbr & 0xffffffff) ;
501  tbr_high = (tbr >> 32) & 0xffffffff;
502  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
503  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
504 
505}
506#endif /* ASM */
507
508#ifndef ASM
509/* Context handler macros */
510
511/*
512 *  Initialize the context to a state suitable for starting a
513 *  task after a context restore operation.  Generally, this
514 *  involves:
515 *
516 *     - setting a starting address
517 *     - preparing the stack
518 *     - preparing the stack and frame pointers
519 *     - setting the proper interrupt level in the context
520 *     - initializing the floating point context
521 *
522 *  This routine generally does not set any unnecessary register
523 *  in the context.  The state of the "general data" registers is
524 *  undefined at task start time.
525 */
526
527void _CPU_Context_Initialize(
528  Context_Control  *the_context,
529  uint32_t         *stack_base,
530  uint32_t          size,
531  uint32_t          new_level,
532  void             *entry_point,
533  bool              is_fp
534);
535
536/*
537 *  This routine is responsible for somehow restarting the currently
538 *  executing task.  If you are lucky, then all that is necessary
539 *  is restoring the context.  Otherwise, there will need to be
540 *  a special assembly routine which does something special in this
541 *  case.  Context_Restore should work most of the time.  It will
542 *  not work if restarting self conflicts with the stack frame
543 *  assumptions of restoring a context.
544 */
545
546#define _CPU_Context_Restart_self( _the_context ) \
547   _CPU_Context_restore( (_the_context) );
548
549/*
550 *  The purpose of this macro is to allow the initial pointer into
551 *  a floating point context area (used to save the floating point
552 *  context) to be at an arbitrary place in the floating point
553 *  context area.
554 *
555 *  This is necessary because some FP units are designed to have
556 *  their context saved as a stack which grows into lower addresses.
557 *  Other FP units can be saved by simply moving registers into offsets
558 *  from the base of the context area.  Finally some FP units provide
559 *  a "dump context" instruction which could fill in from high to low
560 *  or low to high based on the whim of the CPU designers.
561 */
562
563#define _CPU_Context_Fp_start( _base, _offset ) \
564   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
565
566/*
567 *  This routine initializes the FP context area passed to it to.
568 *  There are a few standard ways in which to initialize the
569 *  floating point context.  The code included for this macro assumes
570 *  that this is a CPU in which a "initial" FP context was saved into
571 *  _CPU_Null_fp_context and it simply copies it to the destination
572 *  context passed to it.
573 *
574 *  Other models include (1) not doing anything, and (2) putting
575 *  a "null FP status word" in the correct place in the FP context.
576 */
577
578#define _CPU_Context_Initialize_fp( _destination ) \
579  { \
580    (*(_destination))->fpscr = PPC_INIT_FPSCR; \
581  }
582
583/* end of Context handler macros */
584#endif /* ASM */
585
586#ifndef ASM
587/* Bitfield handler macros */
588
589/*
590 *  This routine sets _output to the bit number of the first bit
591 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
592 *  This type may be either 16 or 32 bits wide although only the 16
593 *  least significant bits will be used.
594 *
595 *  There are a number of variables in using a "find first bit" type
596 *  instruction.
597 *
598 *    (1) What happens when run on a value of zero?
599 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
600 *    (3) The numbering may be zero or one based.
601 *    (4) The "find first bit" instruction may search from MSB or LSB.
602 *
603 *  RTEMS guarantees that (1) will never happen so it is not a concern.
604 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
605 *  _CPU_Priority_Bits_index().  These three form a set of routines
606 *  which must logically operate together.  Bits in the _value are
607 *  set and cleared based on masks built by _CPU_Priority_mask().
608 *  The basic major and minor values calculated by _Priority_Major()
609 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
610 *  to properly range between the values returned by the "find first bit"
611 *  instruction.  This makes it possible for _Priority_Get_highest() to
612 *  calculate the major and directly index into the minor table.
613 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
614 *  is the first bit found.
615 *
616 *  This entire "find first bit" and mapping process depends heavily
617 *  on the manner in which a priority is broken into a major and minor
618 *  components with the major being the 4 MSB of a priority and minor
619 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
620 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
621 *  to the lowest priority.
622 *
623 *  If your CPU does not have a "find first bit" instruction, then
624 *  there are ways to make do without it.  Here are a handful of ways
625 *  to implement this in software:
626 *
627 *    - a series of 16 bit test instructions
628 *    - a "binary search using if's"
629 *    - _number = 0
630 *      if _value > 0x00ff
631 *        _value >>=8
632 *        _number = 8;
633 *
634 *      if _value > 0x0000f
635 *        _value >=8
636 *        _number += 4
637 *
638 *      _number += bit_set_table[ _value ]
639 *
640 *    where bit_set_table[ 16 ] has values which indicate the first
641 *      bit set
642 */
643
644#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
645  { \
646    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
647                  "1" ((_value))); \
648  }
649
650/* end of Bitfield handler macros */
651
652/*
653 *  This routine builds the mask which corresponds to the bit fields
654 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
655 *  for that routine.
656 */
657
658#define _CPU_Priority_Mask( _bit_number ) \
659  ( 0x80000000 >> (_bit_number) )
660
661/*
662 *  This routine translates the bit numbers returned by
663 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
664 *  a major or minor component of a priority.  See the discussion
665 *  for that routine.
666 */
667
668#define _CPU_Priority_bits_index( _priority ) \
669  (_priority)
670
671/* end of Priority handler macros */
672#endif /* ASM */
673
674/* functions */
675
676#ifndef ASM
677
678/*
679 *  _CPU_Initialize
680 *
681 *  This routine performs CPU dependent initialization.
682 */
683
684void _CPU_Initialize(
685  void            (*thread_dispatch)
686);
687
688/*
689 *  _CPU_ISR_install_vector
690 *
691 *  This routine installs an interrupt vector.
692 */
693
694void _CPU_ISR_install_vector(
695  uint32_t    vector,
696  proc_ptr    new_handler,
697  proc_ptr   *old_handler
698);
699
700/*
701 *  _CPU_Install_interrupt_stack
702 *
703 *  This routine installs the hardware interrupt stack pointer.
704 *
705 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
706 *         is TRUE.
707 */
708
709void _CPU_Install_interrupt_stack( void );
710
711/*
712 *  _CPU_Context_switch
713 *
714 *  This routine switches from the run context to the heir context.
715 */
716
717void _CPU_Context_switch(
718  Context_Control  *run,
719  Context_Control  *heir
720);
721
722/*
723 *  _CPU_Context_restore
724 *
725 *  This routine is generallu used only to restart self in an
726 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
727 *
728 *  NOTE: May be unnecessary to reload some registers.
729 */
730
731void _CPU_Context_restore(
732  Context_Control *new_context
733);
734
735/*
736 *  _CPU_Context_save_fp
737 *
738 *  This routine saves the floating point context passed to it.
739 */
740
741void _CPU_Context_save_fp(
742  Context_Control_fp **fp_context_ptr
743);
744
745/*
746 *  _CPU_Context_restore_fp
747 *
748 *  This routine restores the floating point context passed to it.
749 */
750
751void _CPU_Context_restore_fp(
752  Context_Control_fp **fp_context_ptr
753);
754
755void _CPU_Fatal_error(
756  uint32_t   _error
757);
758
759#endif /* ASM */
760
761#endif /* _RTEMS_SCORE_CPU_H */
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