source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 30.4 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  COPYRIGHT (c) 1995 i-cubed ltd.
10 *
11 *  To anyone who acknowledges that this file is provided "AS IS"
12 *  without any express or implied warranty:
13 *      permission to use, copy, modify, and distribute this file
14 *      for any purpose is hereby granted without fee, provided that
15 *      the above copyright notice and this notice appears in all
16 *      copies, and that the name of i-cubed limited not be used in
17 *      advertising or publicity pertaining to distribution of the
18 *      software without specific, written prior permission.
19 *      i-cubed limited makes no representations about the suitability
20 *      of this software for any purpose.
21 *
22 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
23 *
24 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
25 *
26 *  Copyright (c) 2010 embedded brains GmbH.
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
30 *  http://www.rtems.com/license/LICENSE.
31 *
32 * $Id$
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#include <rtems/score/types.h>
39#include <rtems/score/powerpc.h>
40#include <rtems/powerpc/registers.h>
41
42#ifndef ASM
43  #include <string.h> /* for memset() */
44#endif
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/* conditional compilation parameters */
51
52/*
53 *  Should the calls to _Thread_Enable_dispatch be inlined?
54 *
55 *  If TRUE, then they are inlined.
56 *  If FALSE, then a subroutine call is made.
57 *
58 *  Basically this is an example of the classic trade-off of size
59 *  versus speed.  Inlining the call (TRUE) typically increases the
60 *  size of RTEMS while speeding up the enabling of dispatching.
61 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
62 *  only be 0 or 1 unless you are in an interrupt handler and that
63 *  interrupt handler invokes the executive.]  When not inlined
64 *  something calls _Thread_Enable_dispatch which in turns calls
65 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
66 *  one subroutine call is avoided entirely.]
67 */
68
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/*
72 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
73 *  be unrolled one time?  In unrolled each iteration of the loop examines
74 *  two "nodes" on the chain being searched.  Otherwise, only one node
75 *  is examined per iteration.
76 *
77 *  If TRUE, then the loops are unrolled.
78 *  If FALSE, then the loops are not unrolled.
79 *
80 *  The primary factor in making this decision is the cost of disabling
81 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 *  body of the loop.  On some CPUs, the flash is more expensive than
83 *  one iteration of the loop body.  In this case, it might be desirable
84 *  to unroll the loop.  It is important to note that on some CPUs, this
85 *  code is the longest interrupt disable period in RTEMS.  So it is
86 *  necessary to strike a balance when setting this parameter.
87 */
88
89#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
90
91/*
92 *  Does this port provide a CPU dependent IDLE task implementation?
93 *
94 *  If TRUE, then the routine _CPU_Thread_Idle_body
95 *  must be provided and is the default IDLE thread body instead of
96 *  _CPU_Thread_Idle_body.
97 *
98 *  If FALSE, then use the generic IDLE thread body if the BSP does
99 *  not provide one.
100 *
101 *  This is intended to allow for supporting processors which have
102 *  a low power or idle mode.  When the IDLE thread is executed, then
103 *  the CPU can be powered down.
104 *
105 *  The order of precedence for selecting the IDLE thread body is:
106 *
107 *    1.  BSP provided
108 *    2.  CPU dependent (if provided)
109 *    3.  generic (if no BSP and no CPU dependent)
110 */
111
112#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
113
114/*
115 *  Does the stack grow up (toward higher addresses) or down
116 *  (toward lower addresses)?
117 *
118 *  If TRUE, then the grows upward.
119 *  If FALSE, then the grows toward smaller addresses.
120 */
121
122#define CPU_STACK_GROWS_UP               FALSE
123
124/*
125 *  The following is the variable attribute used to force alignment
126 *  of critical RTEMS structures.  On some processors it may make
127 *  sense to have these aligned on tighter boundaries than
128 *  the minimum requirements of the compiler in order to have as
129 *  much of the critical data area as possible in a cache line.
130 *
131 *  The placement of this macro in the declaration of the variables
132 *  is based on the syntactically requirements of the GNU C
133 *  "__attribute__" extension.  For example with GNU C, use
134 *  the following to force a structures to a 32 byte boundary.
135 *
136 *      __attribute__ ((aligned (32)))
137 *
138 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
139 *         To benefit from using this, the data must be heavily
140 *         used so it will stay in the cache and used frequently enough
141 *         in the executive to justify turning this on.
142 */
143
144#define CPU_STRUCTURE_ALIGNMENT \
145  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
146
147/*
148 *  Define what is required to specify how the network to host conversion
149 *  routines are handled.
150 */
151
152#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
153#define CPU_BIG_ENDIAN                           TRUE
154#define CPU_LITTLE_ENDIAN                        FALSE
155#else
156#define CPU_BIG_ENDIAN                           FALSE
157#define CPU_LITTLE_ENDIAN                        TRUE
158#endif
159
160/*
161 *  Does the CPU have hardware floating point?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
165 *
166 *  If there is a FP coprocessor such as the i387 or mc68881, then
167 *  the answer is TRUE.
168 *
169 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
170 *  It indicates whether or not this CPU model has FP support.  For
171 *  example, it would be possible to have an i386_nofp CPU model
172 *  which set this to false to indicate that you have an i386 without
173 *  an i387 and wish to leave floating point support out of RTEMS.
174 */
175
176#if ( PPC_HAS_FPU == 1 )
177#define CPU_HARDWARE_FP     TRUE
178#define CPU_SOFTWARE_FP     FALSE
179#else
180#define CPU_HARDWARE_FP     FALSE
181#define CPU_SOFTWARE_FP     FALSE
182#endif
183
184/*
185 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
186 *
187 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
188 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
189 *
190 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
191 *
192 *  PowerPC Note: It appears the GCC can implicitly generate FPU
193 *  and Altivec instructions when you least expect them.  So make
194 *  all tasks floating point.
195 */
196
197#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
198
199/*
200 *  Should the IDLE task have a floating point context?
201 *
202 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
203 *  and it has a floating point context which is switched in and out.
204 *  If FALSE, then the IDLE task does not have a floating point context.
205 *
206 *  Setting this to TRUE negatively impacts the time required to preempt
207 *  the IDLE task from an interrupt because the floating point context
208 *  must be saved as part of the preemption.
209 */
210
211#define CPU_IDLE_TASK_IS_FP      FALSE
212
213/*
214 *  Processor defined structures required for cpukit/score.
215 */
216
217/*
218 * Contexts
219 *
220 *  Generally there are 2 types of context to save.
221 *     1. Interrupt registers to save
222 *     2. Task level registers to save
223 *
224 *  This means we have the following 3 context items:
225 *     1. task level context stuff::  Context_Control
226 *     2. floating point task stuff:: Context_Control_fp
227 *     3. special interrupt level context :: Context_Control_interrupt
228 *
229 *  On some processors, it is cost-effective to save only the callee
230 *  preserved registers during a task context switch.  This means
231 *  that the ISR code needs to save those registers which do not
232 *  persist across function calls.  It is not mandatory to make this
233 *  distinctions between the caller/callee saves registers for the
234 *  purpose of minimizing context saved during task switch and on interrupts.
235 *  If the cost of saving extra registers is minimal, simplicity is the
236 *  choice.  Save the same context on interrupt entry as for tasks in
237 *  this case.
238 *
239 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
240 *  care should be used in designing the context area.
241 *
242 *  On some CPUs with hardware floating point support, the Context_Control_fp
243 *  structure will not be used or it simply consist of an array of a
244 *  fixed number of bytes.   This is done when the floating point context
245 *  is dumped by a "FP save context" type instruction and the format
246 *  is not really defined by the CPU.  In this case, there is no need
247 *  to figure out the exact format -- only the size.  Of course, although
248 *  this is enough information for RTEMS, it is probably not enough for
249 *  a debugger such as gdb.  But that is another problem.
250 */
251
252#ifndef ASM
253
254typedef struct {
255    uint32_t   gpr1;    /* Stack pointer for all */
256    uint32_t   gpr2;    /* Reserved SVR4, section ptr EABI + */
257    uint32_t   gpr13;   /* Section ptr SVR4/EABI */
258    uint32_t   gpr14;   /* Non volatile for all */
259    uint32_t   gpr15;   /* Non volatile for all */
260    uint32_t   gpr16;   /* Non volatile for all */
261    uint32_t   gpr17;   /* Non volatile for all */
262    uint32_t   gpr18;   /* Non volatile for all */
263    uint32_t   gpr19;   /* Non volatile for all */
264    uint32_t   gpr20;   /* Non volatile for all */
265    uint32_t   gpr21;   /* Non volatile for all */
266    uint32_t   gpr22;   /* Non volatile for all */
267    uint32_t   gpr23;   /* Non volatile for all */
268    uint32_t   gpr24;   /* Non volatile for all */
269    uint32_t   gpr25;   /* Non volatile for all */
270    uint32_t   gpr26;   /* Non volatile for all */
271    uint32_t   gpr27;   /* Non volatile for all */
272    uint32_t   gpr28;   /* Non volatile for all */
273    uint32_t   gpr29;   /* Non volatile for all */
274    uint32_t   gpr30;   /* Non volatile for all */
275    uint32_t   gpr31;   /* Non volatile for all */
276    uint32_t   cr;      /* PART of the CR is non volatile for all */
277    uint32_t   pc;      /* Program counter/Link register */
278    uint32_t   msr;     /* Initial interrupt level */
279#ifdef __ALTIVEC__
280        /* 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
281         * and padding to ensure cache-alignment.
282         * Unfortunately, we can't verify the cache line size here
283         * in the cpukit but altivec support code will produce an
284         * error if this is ever different from 32 bytes.
285         *
286         * Note: it is the BSP/CPU-support's responsibility to
287         *       save/restore volatile vregs across interrupts
288         *       and exceptions.
289         */
290        uint8_t    altivec[16*12 + 32 + 32];
291#endif
292} Context_Control;
293
294#define _CPU_Context_Get_SP( _context ) \
295  (_context)->gpr1
296
297typedef struct {
298    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
299     * procedure calls.  However, this would mean that the interrupt
300     * frame had to hold f0-f13, and the fpscr.  And as the majority
301     * of tasks will not have an FP context, we will save the whole
302     * context here.
303     */
304#if (PPC_HAS_DOUBLE == 1)
305    double      f[32];
306    uint64_t    fpscr;
307#else
308    float       f[32];
309    uint32_t    fpscr;
310#endif
311} Context_Control_fp;
312
313typedef struct CPU_Interrupt_frame {
314    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
315    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
316
317    /* This is what is left out of the primary contexts */
318    uint32_t   gpr0;
319    uint32_t   gpr2;            /* play safe */
320    uint32_t   gpr3;
321    uint32_t   gpr4;
322    uint32_t   gpr5;
323    uint32_t   gpr6;
324    uint32_t   gpr7;
325    uint32_t   gpr8;
326    uint32_t   gpr9;
327    uint32_t   gpr10;
328    uint32_t   gpr11;
329    uint32_t   gpr12;
330    uint32_t   gpr13;   /* Play safe */
331    uint32_t   gpr28;   /* For internal use by the IRQ handler */
332    uint32_t   gpr29;   /* For internal use by the IRQ handler */
333    uint32_t   gpr30;   /* For internal use by the IRQ handler */
334    uint32_t   gpr31;   /* For internal use by the IRQ handler */
335    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
336    uint32_t   ctr;
337    uint32_t   xer;
338    uint32_t   lr;
339    uint32_t   pc;
340    uint32_t   msr;
341    uint32_t   pad[3];
342} CPU_Interrupt_frame;
343
344#endif /* ASM */
345
346/*
347 *  Does RTEMS manage a dedicated interrupt stack in software?
348 *
349 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
350 *  If FALSE, nothing is done.
351 *
352 *  If the CPU supports a dedicated interrupt stack in hardware,
353 *  then it is generally the responsibility of the BSP to allocate it
354 *  and set it up.
355 *
356 *  If the CPU does not support a dedicated interrupt stack, then
357 *  the porter has two options: (1) execute interrupts on the
358 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
359 *  interrupt stack.
360 *
361 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
362 *
363 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
364 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
365 *  possible that both are FALSE for a particular CPU.  Although it
366 *  is unclear what that would imply about the interrupt processing
367 *  procedure on that CPU.
368 */
369
370#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
371
372/*
373 *  Does this CPU have hardware support for a dedicated interrupt stack?
374 *
375 *  If TRUE, then it must be installed during initialization.
376 *  If FALSE, then no installation is performed.
377 *
378 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
379 *
380 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
381 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
382 *  possible that both are FALSE for a particular CPU.  Although it
383 *  is unclear what that would imply about the interrupt processing
384 *  procedure on that CPU.
385 */
386
387#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
388
389/*
390 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
391 *
392 *  If TRUE, then the memory is allocated during initialization.
393 *  If FALSE, then the memory is allocated during initialization.
394 *
395 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
396 */
397
398#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
399
400/*
401 *  Does the RTEMS invoke the user's ISR with the vector number and
402 *  a pointer to the saved interrupt frame (1) or just the vector
403 *  number (0)?
404 */
405
406#define CPU_ISR_PASSES_FRAME_POINTER 0
407
408/*
409 *  Should the saving of the floating point registers be deferred
410 *  until a context switch is made to another different floating point
411 *  task?
412 *
413 *  If TRUE, then the floating point context will not be stored until
414 *  necessary.  It will remain in the floating point registers and not
415 *  disturned until another floating point task is switched to.
416 *
417 *  If FALSE, then the floating point context is saved when a floating
418 *  point task is switched out and restored when the next floating point
419 *  task is restored.  The state of the floating point registers between
420 *  those two operations is not specified.
421 *
422 *  If the floating point context does NOT have to be saved as part of
423 *  interrupt dispatching, then it should be safe to set this to TRUE.
424 *
425 *  Setting this flag to TRUE results in using a different algorithm
426 *  for deciding when to save and restore the floating point context.
427 *  The deferred FP switch algorithm minimizes the number of times
428 *  the FP context is saved and restored.  The FP context is not saved
429 *  until a context switch is made to another, different FP task.
430 *  Thus in a system with only one FP task, the FP context will never
431 *  be saved or restored.
432 *
433 *  Note, however that compilers may use floating point registers/
434 *  instructions for optimization or they may save/restore FP registers
435 *  on the stack. You must not use deferred switching in these cases
436 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
437 *  exception.
438 */
439/*
440 *  ACB Note:  This could make debugging tricky..
441 */
442
443/* conservative setting (FALSE); probably doesn't affect performance too much */
444#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
445
446/*
447 *  Processor defined structures required for cpukit/score.
448 */
449
450#ifndef ASM
451
452/*
453 *  This variable is optional.  It is used on CPUs on which it is difficult
454 *  to generate an "uninitialized" FP context.  It is filled in by
455 *  _CPU_Initialize and copied into the task's FP context area during
456 *  _CPU_Context_Initialize.
457 */
458
459/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
460
461#endif /* ndef ASM */
462
463/*
464 *  This defines the number of levels and the mask used to pick those
465 *  bits out of a thread mode.
466 */
467
468#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
469#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
470
471/*
472 *  Nothing prevents the porter from declaring more CPU specific variables.
473 */
474
475#ifndef ASM
476
477SCORE_EXTERN struct {
478  uint32_t      *Disable_level;
479  void          *Stack;
480  volatile bool *Switch_necessary;
481  bool          *Signal;
482
483} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
484
485#endif /* ndef ASM */
486
487/*
488 *  The size of the floating point context area.  On some CPUs this
489 *  will not be a "sizeof" because the format of the floating point
490 *  area is not defined -- only the size is.  This is usually on
491 *  CPUs with a "floating point save context" instruction.
492 */
493
494#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
495
496/*
497 * (Optional) # of bytes for libmisc/stackchk to check
498 * If not specifed, then it defaults to something reasonable
499 * for most architectures.
500 */
501
502#define CPU_STACK_CHECK_SIZE    (128)
503
504/*
505 *  Amount of extra stack (above minimum stack size) required by
506 *  MPCI receive server thread.  Remember that in a multiprocessor
507 *  system this thread must exist and be able to process all directives.
508 */
509
510#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
511
512/*
513 *  This defines the number of entries in the ISR_Vector_table managed
514 *  by RTEMS.
515 */
516
517#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (0)
518#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (UINT32_MAX)
519
520/*
521 *  This is defined if the port has a special way to report the ISR nesting
522 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
523 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
524 *  being maintained (e.g. watchdog queues).
525 */
526
527#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
528
529/*
530 *  ISR handler macros
531 */
532
533#define _CPU_Initialize_vectors()
534
535/*
536 *  Disable all interrupts for an RTEMS critical section.  The previous
537 *  level is returned in _isr_cookie.
538 */
539
540#ifndef ASM
541
542static inline uint32_t   _CPU_ISR_Get_level( void )
543{
544  register unsigned int msr;
545  _CPU_MSR_GET(msr);
546  if (msr & MSR_EE) return 0;
547  else  return 1;
548}
549
550static inline void _CPU_ISR_Set_level( uint32_t   level )
551{
552  register unsigned int msr;
553  _CPU_MSR_GET(msr);
554  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
555    msr |= ppc_interrupt_get_disable_mask();
556  }
557  else {
558    msr &= ~ppc_interrupt_get_disable_mask();
559  }
560  _CPU_MSR_SET(msr);
561}
562
563void BSP_panic(char *);
564
565/* Fatal Error manager macros */
566
567/*
568 *  This routine copies _error into a known place -- typically a stack
569 *  location or a register, optionally disables interrupts, and
570 *  halts/stops the CPU.
571 */
572
573void _BSP_Fatal_error(unsigned int);
574
575#endif /* ASM */
576
577#define _CPU_Fatal_halt( _error ) \
578  _BSP_Fatal_error(_error)
579
580/* end of Fatal Error manager macros */
581
582/*
583 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
584 * Now SPRG0 is devoted to the interrupt disable mask.
585 */
586
587#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
588
589/*
590 *  Should be large enough to run all RTEMS tests.  This ensures
591 *  that a "reasonable" small application should not have any problems.
592 */
593
594#define CPU_STACK_MINIMUM_SIZE          (1024*8)
595
596/*
597 *  CPU's worst alignment requirement for data types on a byte boundary.  This
598 *  alignment does not take into account the requirements for the stack.
599 */
600
601#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
602
603/*
604 *  This number corresponds to the byte alignment requirement for the
605 *  heap handler.  This alignment requirement may be stricter than that
606 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
607 *  common for the heap to follow the same alignment requirement as
608 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
609 *  then this should be set to CPU_ALIGNMENT.
610 *
611 *  NOTE:  This does not have to be a power of 2.  It does have to
612 *         be greater or equal to than CPU_ALIGNMENT.
613 */
614
615#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
616
617/*
618 *  This number corresponds to the byte alignment requirement for memory
619 *  buffers allocated by the partition manager.  This alignment requirement
620 *  may be stricter than that for the data types alignment specified by
621 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
622 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
623 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
624 *
625 *  NOTE:  This does not have to be a power of 2.  It does have to
626 *         be greater or equal to than CPU_ALIGNMENT.
627 */
628
629#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
630
631/*
632 *  This number corresponds to the byte alignment requirement for the
633 *  stack.  This alignment requirement may be stricter than that for the
634 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
635 *  is strict enough for the stack, then this should be set to 0.
636 *
637 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
638 */
639
640#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
641
642#ifndef ASM
643/*  The following routine swaps the endian format of an unsigned int.
644 *  It must be static because it is referenced indirectly.
645 *
646 *  This version will work on any processor, but if there is a better
647 *  way for your CPU PLEASE use it.  The most common way to do this is to:
648 *
649 *     swap least significant two bytes with 16-bit rotate
650 *     swap upper and lower 16-bits
651 *     swap most significant two bytes with 16-bit rotate
652 *
653 *  Some CPUs have special instructions which swap a 32-bit quantity in
654 *  a single instruction (e.g. i486).  It is probably best to avoid
655 *  an "endian swapping control bit" in the CPU.  One good reason is
656 *  that interrupts would probably have to be disabled to ensure that
657 *  an interrupt does not try to access the same "chunk" with the wrong
658 *  endian.  Another good reason is that on some CPUs, the endian bit
659 *  endianness for ALL fetches -- both code and data -- so the code
660 *  will be fetched incorrectly.
661 */
662
663static inline uint32_t CPU_swap_u32(
664  uint32_t value
665)
666{
667  uint32_t   swapped;
668
669  asm volatile("rlwimi %0,%1,8,24,31;"
670               "rlwimi %0,%1,24,16,23;"
671               "rlwimi %0,%1,8,8,15;"
672               "rlwimi %0,%1,24,0,7;" :
673               "=&r" ((swapped)) : "r" ((value)));
674
675  return( swapped );
676}
677
678#define CPU_swap_u16( value ) \
679  (((value&0xff) << 8) | ((value >> 8)&0xff))
680
681#endif /* ASM */
682
683
684#ifndef ASM
685/* Context handler macros */
686
687/*
688 *  Initialize the context to a state suitable for starting a
689 *  task after a context restore operation.  Generally, this
690 *  involves:
691 *
692 *     - setting a starting address
693 *     - preparing the stack
694 *     - preparing the stack and frame pointers
695 *     - setting the proper interrupt level in the context
696 *     - initializing the floating point context
697 *
698 *  This routine generally does not set any unnecessary register
699 *  in the context.  The state of the "general data" registers is
700 *  undefined at task start time.
701 */
702
703void _CPU_Context_Initialize(
704  Context_Control  *the_context,
705  uint32_t         *stack_base,
706  uint32_t          size,
707  uint32_t          new_level,
708  void             *entry_point,
709  bool              is_fp
710);
711
712/*
713 *  This routine is responsible for somehow restarting the currently
714 *  executing task.  If you are lucky, then all that is necessary
715 *  is restoring the context.  Otherwise, there will need to be
716 *  a special assembly routine which does something special in this
717 *  case.  Context_Restore should work most of the time.  It will
718 *  not work if restarting self conflicts with the stack frame
719 *  assumptions of restoring a context.
720 */
721
722#define _CPU_Context_Restart_self( _the_context ) \
723   _CPU_Context_restore( (_the_context) );
724
725/*
726 *  The purpose of this macro is to allow the initial pointer into
727 *  a floating point context area (used to save the floating point
728 *  context) to be at an arbitrary place in the floating point
729 *  context area.
730 *
731 *  This is necessary because some FP units are designed to have
732 *  their context saved as a stack which grows into lower addresses.
733 *  Other FP units can be saved by simply moving registers into offsets
734 *  from the base of the context area.  Finally some FP units provide
735 *  a "dump context" instruction which could fill in from high to low
736 *  or low to high based on the whim of the CPU designers.
737 */
738
739#define _CPU_Context_Fp_start( _base, _offset ) \
740   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
741
742/*
743 *  This routine initializes the FP context area passed to it to.
744 *  There are a few standard ways in which to initialize the
745 *  floating point context.  The code included for this macro assumes
746 *  that this is a CPU in which a "initial" FP context was saved into
747 *  _CPU_Null_fp_context and it simply copies it to the destination
748 *  context passed to it.
749 *
750 *  Other models include (1) not doing anything, and (2) putting
751 *  a "null FP status word" in the correct place in the FP context.
752 */
753
754#define _CPU_Context_Initialize_fp( _destination ) \
755  memset( *(_destination), 0, sizeof( **(_destination) ) )
756
757/* end of Context handler macros */
758#endif /* ASM */
759
760#ifndef ASM
761/* Bitfield handler macros */
762
763/*
764 *  This routine sets _output to the bit number of the first bit
765 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
766 *  This type may be either 16 or 32 bits wide although only the 16
767 *  least significant bits will be used.
768 *
769 *  There are a number of variables in using a "find first bit" type
770 *  instruction.
771 *
772 *    (1) What happens when run on a value of zero?
773 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
774 *    (3) The numbering may be zero or one based.
775 *    (4) The "find first bit" instruction may search from MSB or LSB.
776 *
777 *  RTEMS guarantees that (1) will never happen so it is not a concern.
778 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
779 *  _CPU_Priority_Bits_index().  These three form a set of routines
780 *  which must logically operate together.  Bits in the _value are
781 *  set and cleared based on masks built by _CPU_Priority_mask().
782 *  The basic major and minor values calculated by _Priority_Major()
783 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
784 *  to properly range between the values returned by the "find first bit"
785 *  instruction.  This makes it possible for _Priority_Get_highest() to
786 *  calculate the major and directly index into the minor table.
787 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
788 *  is the first bit found.
789 *
790 *  This entire "find first bit" and mapping process depends heavily
791 *  on the manner in which a priority is broken into a major and minor
792 *  components with the major being the 4 MSB of a priority and minor
793 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
794 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
795 *  to the lowest priority.
796 *
797 *  If your CPU does not have a "find first bit" instruction, then
798 *  there are ways to make do without it.  Here are a handful of ways
799 *  to implement this in software:
800 *
801 *    - a series of 16 bit test instructions
802 *    - a "binary search using if's"
803 *    - _number = 0
804 *      if _value > 0x00ff
805 *        _value >>=8
806 *        _number = 8;
807 *
808 *      if _value > 0x0000f
809 *        _value >=8
810 *        _number += 4
811 *
812 *      _number += bit_set_table[ _value ]
813 *
814 *    where bit_set_table[ 16 ] has values which indicate the first
815 *      bit set
816 */
817
818#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
819  { \
820    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
821                  "1" ((_value))); \
822  }
823
824/* end of Bitfield handler macros */
825
826/*
827 *  This routine builds the mask which corresponds to the bit fields
828 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
829 *  for that routine.
830 */
831
832#define _CPU_Priority_Mask( _bit_number ) \
833  ( 0x80000000 >> (_bit_number) )
834
835/*
836 *  This routine translates the bit numbers returned by
837 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
838 *  a major or minor component of a priority.  See the discussion
839 *  for that routine.
840 */
841
842#define _CPU_Priority_bits_index( _priority ) \
843  (_priority)
844
845/* end of Priority handler macros */
846#endif /* ASM */
847
848/* functions */
849
850#ifndef ASM
851
852/*
853 *  _CPU_Initialize
854 *
855 *  This routine performs CPU dependent initialization.
856 */
857
858void _CPU_Initialize(void);
859
860/*
861 *  _CPU_ISR_install_vector
862 *
863 *  This routine installs an interrupt vector.
864 */
865
866void _CPU_ISR_install_vector(
867  uint32_t    vector,
868  proc_ptr    new_handler,
869  proc_ptr   *old_handler
870);
871
872/*
873 *  _CPU_Install_interrupt_stack
874 *
875 *  This routine installs the hardware interrupt stack pointer.
876 *
877 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
878 *         is TRUE.
879 */
880
881void _CPU_Install_interrupt_stack( void );
882
883/*
884 *  _CPU_Context_switch
885 *
886 *  This routine switches from the run context to the heir context.
887 */
888
889void _CPU_Context_switch(
890  Context_Control  *run,
891  Context_Control  *heir
892);
893
894/*
895 *  _CPU_Context_restore
896 *
897 *  This routine is generallu used only to restart self in an
898 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
899 *
900 *  NOTE: May be unnecessary to reload some registers.
901 */
902
903void _CPU_Context_restore(
904  Context_Control *new_context
905);
906
907/*
908 *  _CPU_Context_save_fp
909 *
910 *  This routine saves the floating point context passed to it.
911 */
912
913void _CPU_Context_save_fp(
914  Context_Control_fp **fp_context_ptr
915);
916
917/*
918 *  _CPU_Context_restore_fp
919 *
920 *  This routine restores the floating point context passed to it.
921 */
922
923void _CPU_Context_restore_fp(
924  Context_Control_fp **fp_context_ptr
925);
926
927/*
928 * _CPU_Initialize_altivec()
929 *
930 * Global altivec-related initialization.
931 */
932void
933_CPU_Initialize_altivec(void);
934
935/*
936 * _CPU_Context_switch_altivec
937 *
938 * This routine switches the altivec contexts passed to it.
939 */
940
941void
942_CPU_Context_switch_altivec(
943  Context_Control *from,
944  Context_Control *to
945);
946
947/*
948 * _CPU_Context_restore_altivec
949 *
950 * This routine restores the altivec context passed to it.
951 */
952
953void
954_CPU_Context_restore_altivec(
955  Context_Control *ctxt
956);
957
958/*
959 * _CPU_Context_initialize_altivec
960 *
961 * This routine initializes the altivec context passed to it.
962 */
963
964void
965_CPU_Context_initialize_altivec(
966  Context_Control *ctxt
967);
968
969void _CPU_Fatal_error(
970  uint32_t   _error
971);
972
973#endif /* ASM */
974
975#ifdef __cplusplus
976}
977#endif
978
979#endif /* _RTEMS_SCORE_CPU_H */
Note: See TracBrowser for help on using the repository browser.