source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ 3fcc78ae

4.104.115
Last change on this file since 3fcc78ae was 3fcc78ae, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 10/30/09 at 19:28:46

move timebase access functions from cpukit to libcpu

  • Property mode set to 100644
File size: 21.3 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 * $Id$
14 */
15 
16#ifndef _RTEMS_SCORE_CPU_H
17#define _RTEMS_SCORE_CPU_H
18
19#include <rtems/score/powerpc.h>              /* pick up machine definitions */
20
21#ifndef ASM
22  #include <string.h> /* for memset() */
23  #include <rtems/score/types.h>
24#endif
25
26/* conditional compilation parameters */
27
28/*
29 *  Should the calls to _Thread_Enable_dispatch be inlined?
30 *
31 *  If TRUE, then they are inlined.
32 *  If FALSE, then a subroutine call is made.
33 *
34 *  Basically this is an example of the classic trade-off of size
35 *  versus speed.  Inlining the call (TRUE) typically increases the
36 *  size of RTEMS while speeding up the enabling of dispatching.
37 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
38 *  only be 0 or 1 unless you are in an interrupt handler and that
39 *  interrupt handler invokes the executive.]  When not inlined
40 *  something calls _Thread_Enable_dispatch which in turns calls
41 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
42 *  one subroutine call is avoided entirely.]
43 */
44
45#define CPU_INLINE_ENABLE_DISPATCH       FALSE
46
47/*
48 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
49 *  be unrolled one time?  In unrolled each iteration of the loop examines
50 *  two "nodes" on the chain being searched.  Otherwise, only one node
51 *  is examined per iteration.
52 *
53 *  If TRUE, then the loops are unrolled.
54 *  If FALSE, then the loops are not unrolled.
55 *
56 *  The primary factor in making this decision is the cost of disabling
57 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
58 *  body of the loop.  On some CPUs, the flash is more expensive than
59 *  one iteration of the loop body.  In this case, it might be desirable
60 *  to unroll the loop.  It is important to note that on some CPUs, this
61 *  code is the longest interrupt disable period in RTEMS.  So it is
62 *  necessary to strike a balance when setting this parameter.
63 */
64
65#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
66
67/*
68 *  Does this port provide a CPU dependent IDLE task implementation?
69 *
70 *  If TRUE, then the routine _CPU_Thread_Idle_body
71 *  must be provided and is the default IDLE thread body instead of
72 *  _CPU_Thread_Idle_body.
73 *
74 *  If FALSE, then use the generic IDLE thread body if the BSP does
75 *  not provide one.
76 *
77 *  This is intended to allow for supporting processors which have
78 *  a low power or idle mode.  When the IDLE thread is executed, then
79 *  the CPU can be powered down.
80 *
81 *  The order of precedence for selecting the IDLE thread body is:
82 *
83 *    1.  BSP provided
84 *    2.  CPU dependent (if provided)
85 *    3.  generic (if no BSP and no CPU dependent)
86 */
87
88#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
89
90/*
91 *  Does the stack grow up (toward higher addresses) or down
92 *  (toward lower addresses)?
93 *
94 *  If TRUE, then the grows upward.
95 *  If FALSE, then the grows toward smaller addresses.
96 */
97
98#define CPU_STACK_GROWS_UP               FALSE
99
100/*
101 *  The following is the variable attribute used to force alignment
102 *  of critical RTEMS structures.  On some processors it may make
103 *  sense to have these aligned on tighter boundaries than
104 *  the minimum requirements of the compiler in order to have as
105 *  much of the critical data area as possible in a cache line.
106 *
107 *  The placement of this macro in the declaration of the variables
108 *  is based on the syntactically requirements of the GNU C
109 *  "__attribute__" extension.  For example with GNU C, use
110 *  the following to force a structures to a 32 byte boundary.
111 *
112 *      __attribute__ ((aligned (32)))
113 *
114 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
115 *         To benefit from using this, the data must be heavily
116 *         used so it will stay in the cache and used frequently enough
117 *         in the executive to justify turning this on.
118 */
119
120#define CPU_STRUCTURE_ALIGNMENT \
121  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
122
123/*
124 *  Define what is required to specify how the network to host conversion
125 *  routines are handled.
126 */
127
128#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
129#define CPU_BIG_ENDIAN                           TRUE
130#define CPU_LITTLE_ENDIAN                        FALSE
131#else
132#define CPU_BIG_ENDIAN                           FALSE
133#define CPU_LITTLE_ENDIAN                        TRUE
134#endif
135
136/*
137 *  Does the CPU have hardware floating point?
138 *
139 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
140 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
141 *
142 *  If there is a FP coprocessor such as the i387 or mc68881, then
143 *  the answer is TRUE.
144 *
145 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
146 *  It indicates whether or not this CPU model has FP support.  For
147 *  example, it would be possible to have an i386_nofp CPU model
148 *  which set this to false to indicate that you have an i386 without
149 *  an i387 and wish to leave floating point support out of RTEMS.
150 */
151
152#if ( PPC_HAS_FPU == 1 )
153#define CPU_HARDWARE_FP     TRUE
154#define CPU_SOFTWARE_FP     FALSE
155#else
156#define CPU_HARDWARE_FP     FALSE
157#define CPU_SOFTWARE_FP     FALSE
158#endif
159
160/*
161 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
165 *
166 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
167 *
168 *  PowerPC Note: It appears the GCC can implicitly generate FPU
169 *  and Altivec instructions when you least expect them.  So make
170 *  all tasks floating point.
171 */
172
173#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
174
175/*
176 *  Should the IDLE task have a floating point context?
177 *
178 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
179 *  and it has a floating point context which is switched in and out.
180 *  If FALSE, then the IDLE task does not have a floating point context.
181 *
182 *  Setting this to TRUE negatively impacts the time required to preempt
183 *  the IDLE task from an interrupt because the floating point context
184 *  must be saved as part of the preemption.
185 */
186
187#define CPU_IDLE_TASK_IS_FP      FALSE
188
189/*
190 *  Processor defined structures required for cpukit/score.
191 */
192
193/*
194 * Contexts
195 *
196 *  Generally there are 2 types of context to save.
197 *     1. Interrupt registers to save
198 *     2. Task level registers to save
199 *
200 *  This means we have the following 3 context items:
201 *     1. task level context stuff::  Context_Control
202 *     2. floating point task stuff:: Context_Control_fp
203 *     3. special interrupt level context :: Context_Control_interrupt
204 *
205 *  On some processors, it is cost-effective to save only the callee
206 *  preserved registers during a task context switch.  This means
207 *  that the ISR code needs to save those registers which do not
208 *  persist across function calls.  It is not mandatory to make this
209 *  distinctions between the caller/callee saves registers for the
210 *  purpose of minimizing context saved during task switch and on interrupts.
211 *  If the cost of saving extra registers is minimal, simplicity is the
212 *  choice.  Save the same context on interrupt entry as for tasks in
213 *  this case.
214 *
215 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
216 *  care should be used in designing the context area.
217 *
218 *  On some CPUs with hardware floating point support, the Context_Control_fp
219 *  structure will not be used or it simply consist of an array of a
220 *  fixed number of bytes.   This is done when the floating point context
221 *  is dumped by a "FP save context" type instruction and the format
222 *  is not really defined by the CPU.  In this case, there is no need
223 *  to figure out the exact format -- only the size.  Of course, although
224 *  this is enough information for RTEMS, it is probably not enough for
225 *  a debugger such as gdb.  But that is another problem.
226 */
227
228#ifndef ASM
229
230typedef struct {
231    uint32_t   gpr1;    /* Stack pointer for all */
232    uint32_t   gpr2;    /* Reserved SVR4, section ptr EABI + */
233    uint32_t   gpr13;   /* Section ptr SVR4/EABI */
234    uint32_t   gpr14;   /* Non volatile for all */
235    uint32_t   gpr15;   /* Non volatile for all */
236    uint32_t   gpr16;   /* Non volatile for all */
237    uint32_t   gpr17;   /* Non volatile for all */
238    uint32_t   gpr18;   /* Non volatile for all */
239    uint32_t   gpr19;   /* Non volatile for all */
240    uint32_t   gpr20;   /* Non volatile for all */
241    uint32_t   gpr21;   /* Non volatile for all */
242    uint32_t   gpr22;   /* Non volatile for all */
243    uint32_t   gpr23;   /* Non volatile for all */
244    uint32_t   gpr24;   /* Non volatile for all */
245    uint32_t   gpr25;   /* Non volatile for all */
246    uint32_t   gpr26;   /* Non volatile for all */
247    uint32_t   gpr27;   /* Non volatile for all */
248    uint32_t   gpr28;   /* Non volatile for all */
249    uint32_t   gpr29;   /* Non volatile for all */
250    uint32_t   gpr30;   /* Non volatile for all */
251    uint32_t   gpr31;   /* Non volatile for all */
252    uint32_t   cr;      /* PART of the CR is non volatile for all */
253    uint32_t   pc;      /* Program counter/Link register */
254    uint32_t   msr;     /* Initial interrupt level */
255} Context_Control;
256
257#define _CPU_Context_Get_SP( _context ) \
258  (_context)->gpr1
259
260typedef struct {
261    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
262     * procedure calls.  However, this would mean that the interrupt
263     * frame had to hold f0-f13, and the fpscr.  And as the majority
264     * of tasks will not have an FP context, we will save the whole
265     * context here.
266     */
267#if (PPC_HAS_DOUBLE == 1)
268    double      f[32];
269    uint64_t    fpscr;
270#else
271    float       f[32];
272    uint32_t    fpscr;
273#endif
274} Context_Control_fp;
275
276typedef struct CPU_Interrupt_frame {
277    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
278    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
279
280    /* This is what is left out of the primary contexts */
281    uint32_t   gpr0;
282    uint32_t   gpr2;            /* play safe */
283    uint32_t   gpr3;
284    uint32_t   gpr4;
285    uint32_t   gpr5;
286    uint32_t   gpr6;
287    uint32_t   gpr7;
288    uint32_t   gpr8;
289    uint32_t   gpr9;
290    uint32_t   gpr10;
291    uint32_t   gpr11;
292    uint32_t   gpr12;
293    uint32_t   gpr13;   /* Play safe */
294    uint32_t   gpr28;   /* For internal use by the IRQ handler */
295    uint32_t   gpr29;   /* For internal use by the IRQ handler */
296    uint32_t   gpr30;   /* For internal use by the IRQ handler */
297    uint32_t   gpr31;   /* For internal use by the IRQ handler */
298    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
299    uint32_t   ctr;
300    uint32_t   xer;
301    uint32_t   lr;
302    uint32_t   pc;
303    uint32_t   msr;
304    uint32_t   pad[3];
305} CPU_Interrupt_frame;
306
307#endif /* ASM */
308
309#include <rtems/new-exceptions/cpu.h>
310
311/*
312 *  Should be large enough to run all RTEMS tests.  This ensures
313 *  that a "reasonable" small application should not have any problems.
314 */
315
316#define CPU_STACK_MINIMUM_SIZE          (1024*8)
317
318/*
319 *  CPU's worst alignment requirement for data types on a byte boundary.  This
320 *  alignment does not take into account the requirements for the stack.
321 */
322
323#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
324
325/*
326 *  This number corresponds to the byte alignment requirement for the
327 *  heap handler.  This alignment requirement may be stricter than that
328 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
329 *  common for the heap to follow the same alignment requirement as
330 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
331 *  then this should be set to CPU_ALIGNMENT.
332 *
333 *  NOTE:  This does not have to be a power of 2.  It does have to
334 *         be greater or equal to than CPU_ALIGNMENT.
335 */
336
337#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
338
339/*
340 *  This number corresponds to the byte alignment requirement for memory
341 *  buffers allocated by the partition manager.  This alignment requirement
342 *  may be stricter than that for the data types alignment specified by
343 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
344 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
345 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
346 *
347 *  NOTE:  This does not have to be a power of 2.  It does have to
348 *         be greater or equal to than CPU_ALIGNMENT.
349 */
350
351#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
352
353/*
354 *  This number corresponds to the byte alignment requirement for the
355 *  stack.  This alignment requirement may be stricter than that for the
356 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
357 *  is strict enough for the stack, then this should be set to 0.
358 *
359 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
360 */
361
362#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
363
364#ifndef ASM
365/*  The following routine swaps the endian format of an unsigned int.
366 *  It must be static because it is referenced indirectly.
367 *
368 *  This version will work on any processor, but if there is a better
369 *  way for your CPU PLEASE use it.  The most common way to do this is to:
370 *
371 *     swap least significant two bytes with 16-bit rotate
372 *     swap upper and lower 16-bits
373 *     swap most significant two bytes with 16-bit rotate
374 *
375 *  Some CPUs have special instructions which swap a 32-bit quantity in
376 *  a single instruction (e.g. i486).  It is probably best to avoid
377 *  an "endian swapping control bit" in the CPU.  One good reason is
378 *  that interrupts would probably have to be disabled to ensure that
379 *  an interrupt does not try to access the same "chunk" with the wrong
380 *  endian.  Another good reason is that on some CPUs, the endian bit
381 *  endianness for ALL fetches -- both code and data -- so the code
382 *  will be fetched incorrectly.
383 */
384 
385static inline uint32_t CPU_swap_u32(
386  uint32_t value
387)
388{
389  uint32_t   swapped;
390 
391  asm volatile("rlwimi %0,%1,8,24,31;"
392               "rlwimi %0,%1,24,16,23;"
393               "rlwimi %0,%1,8,8,15;"
394               "rlwimi %0,%1,24,0,7;" :
395               "=&r" ((swapped)) : "r" ((value)));
396
397  return( swapped );
398}
399
400#define CPU_swap_u16( value ) \
401  (((value&0xff) << 8) | ((value >> 8)&0xff))
402
403#endif /* ASM */
404
405
406#ifndef ASM
407/* Context handler macros */
408
409/*
410 *  Initialize the context to a state suitable for starting a
411 *  task after a context restore operation.  Generally, this
412 *  involves:
413 *
414 *     - setting a starting address
415 *     - preparing the stack
416 *     - preparing the stack and frame pointers
417 *     - setting the proper interrupt level in the context
418 *     - initializing the floating point context
419 *
420 *  This routine generally does not set any unnecessary register
421 *  in the context.  The state of the "general data" registers is
422 *  undefined at task start time.
423 */
424
425void _CPU_Context_Initialize(
426  Context_Control  *the_context,
427  uint32_t         *stack_base,
428  uint32_t          size,
429  uint32_t          new_level,
430  void             *entry_point,
431  bool              is_fp
432);
433
434/*
435 *  This routine is responsible for somehow restarting the currently
436 *  executing task.  If you are lucky, then all that is necessary
437 *  is restoring the context.  Otherwise, there will need to be
438 *  a special assembly routine which does something special in this
439 *  case.  Context_Restore should work most of the time.  It will
440 *  not work if restarting self conflicts with the stack frame
441 *  assumptions of restoring a context.
442 */
443
444#define _CPU_Context_Restart_self( _the_context ) \
445   _CPU_Context_restore( (_the_context) );
446
447/*
448 *  The purpose of this macro is to allow the initial pointer into
449 *  a floating point context area (used to save the floating point
450 *  context) to be at an arbitrary place in the floating point
451 *  context area.
452 *
453 *  This is necessary because some FP units are designed to have
454 *  their context saved as a stack which grows into lower addresses.
455 *  Other FP units can be saved by simply moving registers into offsets
456 *  from the base of the context area.  Finally some FP units provide
457 *  a "dump context" instruction which could fill in from high to low
458 *  or low to high based on the whim of the CPU designers.
459 */
460
461#define _CPU_Context_Fp_start( _base, _offset ) \
462   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
463
464/*
465 *  This routine initializes the FP context area passed to it to.
466 *  There are a few standard ways in which to initialize the
467 *  floating point context.  The code included for this macro assumes
468 *  that this is a CPU in which a "initial" FP context was saved into
469 *  _CPU_Null_fp_context and it simply copies it to the destination
470 *  context passed to it.
471 *
472 *  Other models include (1) not doing anything, and (2) putting
473 *  a "null FP status word" in the correct place in the FP context.
474 */
475
476#define _CPU_Context_Initialize_fp( _destination ) \
477  memset( *(_destination), 0, sizeof( **(_destination) ) )
478
479/* end of Context handler macros */
480#endif /* ASM */
481
482#ifndef ASM
483/* Bitfield handler macros */
484
485/*
486 *  This routine sets _output to the bit number of the first bit
487 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
488 *  This type may be either 16 or 32 bits wide although only the 16
489 *  least significant bits will be used.
490 *
491 *  There are a number of variables in using a "find first bit" type
492 *  instruction.
493 *
494 *    (1) What happens when run on a value of zero?
495 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
496 *    (3) The numbering may be zero or one based.
497 *    (4) The "find first bit" instruction may search from MSB or LSB.
498 *
499 *  RTEMS guarantees that (1) will never happen so it is not a concern.
500 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
501 *  _CPU_Priority_Bits_index().  These three form a set of routines
502 *  which must logically operate together.  Bits in the _value are
503 *  set and cleared based on masks built by _CPU_Priority_mask().
504 *  The basic major and minor values calculated by _Priority_Major()
505 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
506 *  to properly range between the values returned by the "find first bit"
507 *  instruction.  This makes it possible for _Priority_Get_highest() to
508 *  calculate the major and directly index into the minor table.
509 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
510 *  is the first bit found.
511 *
512 *  This entire "find first bit" and mapping process depends heavily
513 *  on the manner in which a priority is broken into a major and minor
514 *  components with the major being the 4 MSB of a priority and minor
515 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
516 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
517 *  to the lowest priority.
518 *
519 *  If your CPU does not have a "find first bit" instruction, then
520 *  there are ways to make do without it.  Here are a handful of ways
521 *  to implement this in software:
522 *
523 *    - a series of 16 bit test instructions
524 *    - a "binary search using if's"
525 *    - _number = 0
526 *      if _value > 0x00ff
527 *        _value >>=8
528 *        _number = 8;
529 *
530 *      if _value > 0x0000f
531 *        _value >=8
532 *        _number += 4
533 *
534 *      _number += bit_set_table[ _value ]
535 *
536 *    where bit_set_table[ 16 ] has values which indicate the first
537 *      bit set
538 */
539
540#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
541  { \
542    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
543                  "1" ((_value))); \
544  }
545
546/* end of Bitfield handler macros */
547
548/*
549 *  This routine builds the mask which corresponds to the bit fields
550 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
551 *  for that routine.
552 */
553
554#define _CPU_Priority_Mask( _bit_number ) \
555  ( 0x80000000 >> (_bit_number) )
556
557/*
558 *  This routine translates the bit numbers returned by
559 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
560 *  a major or minor component of a priority.  See the discussion
561 *  for that routine.
562 */
563
564#define _CPU_Priority_bits_index( _priority ) \
565  (_priority)
566
567/* end of Priority handler macros */
568#endif /* ASM */
569
570/* functions */
571
572#ifndef ASM
573
574/*
575 *  _CPU_Initialize
576 *
577 *  This routine performs CPU dependent initialization.
578 */
579
580void _CPU_Initialize(void);
581
582/*
583 *  _CPU_ISR_install_vector
584 *
585 *  This routine installs an interrupt vector.
586 */
587
588void _CPU_ISR_install_vector(
589  uint32_t    vector,
590  proc_ptr    new_handler,
591  proc_ptr   *old_handler
592);
593
594/*
595 *  _CPU_Install_interrupt_stack
596 *
597 *  This routine installs the hardware interrupt stack pointer.
598 *
599 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
600 *         is TRUE.
601 */
602
603void _CPU_Install_interrupt_stack( void );
604
605/*
606 *  _CPU_Context_switch
607 *
608 *  This routine switches from the run context to the heir context.
609 */
610
611void _CPU_Context_switch(
612  Context_Control  *run,
613  Context_Control  *heir
614);
615
616/*
617 *  _CPU_Context_restore
618 *
619 *  This routine is generallu used only to restart self in an
620 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
621 *
622 *  NOTE: May be unnecessary to reload some registers.
623 */
624
625void _CPU_Context_restore(
626  Context_Control *new_context
627);
628
629/*
630 *  _CPU_Context_save_fp
631 *
632 *  This routine saves the floating point context passed to it.
633 */
634
635void _CPU_Context_save_fp(
636  Context_Control_fp **fp_context_ptr
637);
638
639/*
640 *  _CPU_Context_restore_fp
641 *
642 *  This routine restores the floating point context passed to it.
643 */
644
645void _CPU_Context_restore_fp(
646  Context_Control_fp **fp_context_ptr
647);
648
649void _CPU_Fatal_error(
650  uint32_t   _error
651);
652
653#endif /* ASM */
654
655#endif /* _RTEMS_SCORE_CPU_H */
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