source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ 27bfcd8

5
Last change on this file since 27bfcd8 was 27bfcd8, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 25, 2017 at 1:32:02 PM

score: Delete _CPU_Context_Fp_start()

Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().

Close #1400.

  • Property mode set to 100644
File size: 35.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief PowerPC CPU Department Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  COPYRIGHT (c) 1995 i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
25 *
26 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
27 *
28 *  Copyright (c) 2010, 2016 embedded brains GmbH.
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.rtems.org/license/LICENSE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#include <rtems/score/types.h>
39#include <rtems/score/powerpc.h>
40#include <rtems/powerpc/registers.h>
41
42#ifndef ASM
43  #include <string.h> /* for memset() */
44#endif
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/* conditional compilation parameters */
51
52/*
53 *  Does this port provide a CPU dependent IDLE task implementation?
54 *
55 *  If TRUE, then the routine _CPU_Thread_Idle_body
56 *  must be provided and is the default IDLE thread body instead of
57 *  _CPU_Thread_Idle_body.
58 *
59 *  If FALSE, then use the generic IDLE thread body if the BSP does
60 *  not provide one.
61 *
62 *  This is intended to allow for supporting processors which have
63 *  a low power or idle mode.  When the IDLE thread is executed, then
64 *  the CPU can be powered down.
65 *
66 *  The order of precedence for selecting the IDLE thread body is:
67 *
68 *    1.  BSP provided
69 *    2.  CPU dependent (if provided)
70 *    3.  generic (if no BSP and no CPU dependent)
71 */
72
73#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
74
75/*
76 *  Does the stack grow up (toward higher addresses) or down
77 *  (toward lower addresses)?
78 *
79 *  If TRUE, then the grows upward.
80 *  If FALSE, then the grows toward smaller addresses.
81 */
82
83#define CPU_STACK_GROWS_UP               FALSE
84
85#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT
86
87#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
88
89/*
90 *  Does the CPU have hardware floating point?
91 *
92 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
93 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
94 *
95 *  If there is a FP coprocessor such as the i387 or mc68881, then
96 *  the answer is TRUE.
97 *
98 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
99 *  It indicates whether or not this CPU model has FP support.  For
100 *  example, it would be possible to have an i386_nofp CPU model
101 *  which set this to false to indicate that you have an i386 without
102 *  an i387 and wish to leave floating point support out of RTEMS.
103 */
104
105#if ( PPC_HAS_FPU == 1 )
106#define CPU_HARDWARE_FP     TRUE
107#define CPU_SOFTWARE_FP     FALSE
108#else
109#define CPU_HARDWARE_FP     FALSE
110#define CPU_SOFTWARE_FP     FALSE
111#endif
112
113/*
114 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
115 *
116 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
117 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
118 *
119 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
120 *
121 *  PowerPC Note: It appears the GCC can implicitly generate FPU
122 *  and Altivec instructions when you least expect them.  So make
123 *  all tasks floating point.
124 */
125
126#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
127
128/*
129 *  Should the IDLE task have a floating point context?
130 *
131 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
132 *  and it has a floating point context which is switched in and out.
133 *  If FALSE, then the IDLE task does not have a floating point context.
134 *
135 *  Setting this to TRUE negatively impacts the time required to preempt
136 *  the IDLE task from an interrupt because the floating point context
137 *  must be saved as part of the preemption.
138 */
139
140#define CPU_IDLE_TASK_IS_FP      FALSE
141
142#define CPU_MAXIMUM_PROCESSORS 32
143
144/*
145 *  Processor defined structures required for cpukit/score.
146 */
147
148/*
149 * Contexts
150 *
151 *  Generally there are 2 types of context to save.
152 *     1. Interrupt registers to save
153 *     2. Task level registers to save
154 *
155 *  This means we have the following 3 context items:
156 *     1. task level context stuff::  Context_Control
157 *     2. floating point task stuff:: Context_Control_fp
158 *     3. special interrupt level context :: Context_Control_interrupt
159 *
160 *  On some processors, it is cost-effective to save only the callee
161 *  preserved registers during a task context switch.  This means
162 *  that the ISR code needs to save those registers which do not
163 *  persist across function calls.  It is not mandatory to make this
164 *  distinctions between the caller/callee saves registers for the
165 *  purpose of minimizing context saved during task switch and on interrupts.
166 *  If the cost of saving extra registers is minimal, simplicity is the
167 *  choice.  Save the same context on interrupt entry as for tasks in
168 *  this case.
169 *
170 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
171 *  care should be used in designing the context area.
172 *
173 *  On some CPUs with hardware floating point support, the Context_Control_fp
174 *  structure will not be used or it simply consist of an array of a
175 *  fixed number of bytes.   This is done when the floating point context
176 *  is dumped by a "FP save context" type instruction and the format
177 *  is not really defined by the CPU.  In this case, there is no need
178 *  to figure out the exact format -- only the size.  Of course, although
179 *  this is enough information for RTEMS, it is probably not enough for
180 *  a debugger such as gdb.  But that is another problem.
181 */
182
183#ifndef __SPE__
184  #define PPC_GPR_TYPE uint32_t
185  #define PPC_GPR_SIZE 4
186  #define PPC_GPR_LOAD lwz
187  #define PPC_GPR_STORE stw
188#else
189  #define PPC_GPR_TYPE uint64_t
190  #define PPC_GPR_SIZE 8
191  #define PPC_GPR_LOAD evldd
192  #define PPC_GPR_STORE evstdd
193#endif
194
195#ifndef ASM
196
197/*
198 * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according
199 * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 -
200 * Linux and Embedded")
201 */
202typedef struct {
203  uint32_t gpr1;
204  uint32_t msr;
205  uint32_t lr;
206  uint32_t cr;
207  PPC_GPR_TYPE gpr14;
208  PPC_GPR_TYPE gpr15;
209  PPC_GPR_TYPE gpr16;
210  PPC_GPR_TYPE gpr17;
211  PPC_GPR_TYPE gpr18;
212  PPC_GPR_TYPE gpr19;
213  PPC_GPR_TYPE gpr20;
214  PPC_GPR_TYPE gpr21;
215  PPC_GPR_TYPE gpr22;
216  PPC_GPR_TYPE gpr23;
217  PPC_GPR_TYPE gpr24;
218  PPC_GPR_TYPE gpr25;
219  PPC_GPR_TYPE gpr26;
220  PPC_GPR_TYPE gpr27;
221  PPC_GPR_TYPE gpr28;
222  PPC_GPR_TYPE gpr29;
223  PPC_GPR_TYPE gpr30;
224  PPC_GPR_TYPE gpr31;
225  uint32_t gpr2;
226  uint32_t isr_dispatch_disable;
227  #if defined(PPC_MULTILIB_ALTIVEC)
228    uint8_t v20[16];
229    uint8_t v21[16];
230    uint8_t v22[16];
231    uint8_t v23[16];
232    uint8_t v24[16];
233    uint8_t v25[16];
234    uint8_t v26[16];
235    uint8_t v27[16];
236    uint8_t v28[16];
237    uint8_t v29[16];
238    uint8_t v30[16];
239    uint8_t v31[16];
240    uint32_t vrsave;
241  #elif defined(__ALTIVEC__)
242    /*
243     * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
244     * and padding to ensure cache-alignment.  Unfortunately, we can't verify
245     * the cache line size here in the cpukit but altivec support code will
246     * produce an error if this is ever different from 32 bytes.
247     *
248     * Note: it is the BSP/CPU-support's responsibility to save/restore
249     *       volatile vregs across interrupts and exceptions.
250     */
251    uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
252  #endif
253  #if defined(PPC_MULTILIB_FPU)
254    double f14;
255    double f15;
256    double f16;
257    double f17;
258    double f18;
259    double f19;
260    double f20;
261    double f21;
262    double f22;
263    double f23;
264    double f24;
265    double f25;
266    double f26;
267    double f27;
268    double f28;
269    double f29;
270    double f30;
271    double f31;
272  #endif
273  #if defined(RTEMS_SMP)
274    /*
275     * This item is at the structure end, so that we can use dcbz for the
276     * previous items to optimize the context switch.  We must not set this
277     * item to zero via the dcbz.
278     */
279    volatile uint32_t is_executing;
280  #endif
281} ppc_context;
282
283typedef struct {
284  uint8_t context [
285    PPC_DEFAULT_CACHE_LINE_SIZE
286      + sizeof(ppc_context)
287      + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
288        ? 0
289          : PPC_DEFAULT_CACHE_LINE_SIZE
290            - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
291  ];
292} Context_Control;
293
294static inline ppc_context *ppc_get_context( const Context_Control *context )
295{
296  uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
297  uintptr_t mask = clsz - 1;
298  uintptr_t addr = (uintptr_t) context;
299
300  return (ppc_context *) ((addr & ~mask) + clsz);
301}
302
303#define _CPU_Context_Get_SP( _context ) \
304  ppc_get_context(_context)->gpr1
305
306#ifdef RTEMS_SMP
307  static inline bool _CPU_Context_Get_is_executing(
308    const Context_Control *context
309  )
310  {
311    return ppc_get_context(context)->is_executing;
312  }
313
314  static inline void _CPU_Context_Set_is_executing(
315    Context_Control *context,
316    bool is_executing
317  )
318  {
319    ppc_get_context(context)->is_executing = is_executing;
320  }
321#endif
322#endif /* ASM */
323
324#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0)
325#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4)
326#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8)
327#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12)
328
329#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
330  (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16)
331
332#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
333#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
334#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
335#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
336#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
337#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
338#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
339#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
340#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
341#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
342#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
343#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
344#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
345#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
346#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
347#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
348#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
349#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
350#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 )
351#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE \
352  ( PPC_CONTEXT_GPR_OFFSET( 32 ) + 4 )
353
354#ifdef PPC_MULTILIB_ALTIVEC
355  #define PPC_CONTEXT_OFFSET_V( v ) \
356    ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 )
357  #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 )
358  #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 )
359  #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 )
360  #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 )
361  #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 )
362  #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 )
363  #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 )
364  #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 )
365  #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 )
366  #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 )
367  #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 )
368  #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 )
369  #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 )
370  #define PPC_CONTEXT_OFFSET_F( f ) \
371    ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 )
372#else
373  #define PPC_CONTEXT_OFFSET_F( f ) \
374    ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 )
375#endif
376
377#ifdef PPC_MULTILIB_FPU
378  #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 )
379  #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 )
380  #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 )
381  #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 )
382  #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 )
383  #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 )
384  #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 )
385  #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 )
386  #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 )
387  #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 )
388  #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 )
389  #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 )
390  #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 )
391  #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 )
392  #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 )
393  #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 )
394  #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 )
395  #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 )
396#endif
397
398#if defined(PPC_MULTILIB_FPU)
399  #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 )
400#elif defined(PPC_MULTILIB_ALTIVEC)
401  #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4)
402#else
403  #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4)
404#endif
405
406#ifdef RTEMS_SMP
407  #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE
408#endif
409
410#ifndef ASM
411typedef struct {
412#if (PPC_HAS_FPU == 1)
413    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
414     * procedure calls.  However, this would mean that the interrupt
415     * frame had to hold f0-f13, and the fpscr.  And as the majority
416     * of tasks will not have an FP context, we will save the whole
417     * context here.
418     */
419#if (PPC_HAS_DOUBLE == 1)
420    double      f[32];
421    uint64_t    fpscr;
422#else
423    float       f[32];
424    uint32_t    fpscr;
425#endif
426#endif /* (PPC_HAS_FPU == 1) */
427} Context_Control_fp;
428
429#endif /* ASM */
430
431/*
432 *  Does the CPU follow the simple vectored interrupt model?
433 *
434 *  If TRUE, then RTEMS allocates the vector table it internally manages.
435 *  If FALSE, then the BSP is assumed to allocate and manage the vector
436 *  table
437 *
438 *  PowerPC Specific Information:
439 *
440 *  The PowerPC and x86 were the first to use the PIC interrupt model.
441 *  They do not use the simple vectored interrupt model.
442 */
443#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
444
445/*
446 *  Does RTEMS manage a dedicated interrupt stack in software?
447 *
448 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
449 *  If FALSE, nothing is done.
450 *
451 *  If the CPU supports a dedicated interrupt stack in hardware,
452 *  then it is generally the responsibility of the BSP to allocate it
453 *  and set it up.
454 *
455 *  If the CPU does not support a dedicated interrupt stack, then
456 *  the porter has two options: (1) execute interrupts on the
457 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
458 *  interrupt stack.
459 *
460 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
461 *
462 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
463 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
464 *  possible that both are FALSE for a particular CPU.  Although it
465 *  is unclear what that would imply about the interrupt processing
466 *  procedure on that CPU.
467 */
468
469#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
470
471/*
472 *  Does this CPU have hardware support for a dedicated interrupt stack?
473 *
474 *  If TRUE, then it must be installed during initialization.
475 *  If FALSE, then no installation is performed.
476 *
477 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
478 *
479 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
480 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
481 *  possible that both are FALSE for a particular CPU.  Although it
482 *  is unclear what that would imply about the interrupt processing
483 *  procedure on that CPU.
484 */
485
486#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
487
488/*
489 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
490 *
491 *  If TRUE, then the memory is allocated during initialization.
492 *  If FALSE, then the memory is allocated during initialization.
493 *
494 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
495 */
496
497#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
498
499/*
500 *  Does the RTEMS invoke the user's ISR with the vector number and
501 *  a pointer to the saved interrupt frame (1) or just the vector
502 *  number (0)?
503 */
504
505#define CPU_ISR_PASSES_FRAME_POINTER FALSE
506
507/*
508 *  Should the saving of the floating point registers be deferred
509 *  until a context switch is made to another different floating point
510 *  task?
511 *
512 *  If TRUE, then the floating point context will not be stored until
513 *  necessary.  It will remain in the floating point registers and not
514 *  disturned until another floating point task is switched to.
515 *
516 *  If FALSE, then the floating point context is saved when a floating
517 *  point task is switched out and restored when the next floating point
518 *  task is restored.  The state of the floating point registers between
519 *  those two operations is not specified.
520 *
521 *  If the floating point context does NOT have to be saved as part of
522 *  interrupt dispatching, then it should be safe to set this to TRUE.
523 *
524 *  Setting this flag to TRUE results in using a different algorithm
525 *  for deciding when to save and restore the floating point context.
526 *  The deferred FP switch algorithm minimizes the number of times
527 *  the FP context is saved and restored.  The FP context is not saved
528 *  until a context switch is made to another, different FP task.
529 *  Thus in a system with only one FP task, the FP context will never
530 *  be saved or restored.
531 *
532 *  Note, however that compilers may use floating point registers/
533 *  instructions for optimization or they may save/restore FP registers
534 *  on the stack. You must not use deferred switching in these cases
535 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
536 *  exception.
537 */
538/*
539 *  ACB Note:  This could make debugging tricky..
540 */
541
542/* conservative setting (FALSE); probably doesn't affect performance too much */
543#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
544
545#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
546
547/*
548 *  Processor defined structures required for cpukit/score.
549 */
550
551#ifndef ASM
552
553/*
554 *  This variable is optional.  It is used on CPUs on which it is difficult
555 *  to generate an "uninitialized" FP context.  It is filled in by
556 *  _CPU_Initialize and copied into the task's FP context area during
557 *  _CPU_Context_Initialize.
558 */
559
560/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
561
562#endif /* ndef ASM */
563
564/*
565 *  This defines the number of levels and the mask used to pick those
566 *  bits out of a thread mode.
567 */
568
569#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
570#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
571
572/*
573 *  The size of the floating point context area.  On some CPUs this
574 *  will not be a "sizeof" because the format of the floating point
575 *  area is not defined -- only the size is.  This is usually on
576 *  CPUs with a "floating point save context" instruction.
577 */
578
579#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
580
581/*
582 * (Optional) # of bytes for libmisc/stackchk to check
583 * If not specifed, then it defaults to something reasonable
584 * for most architectures.
585 */
586
587#define CPU_STACK_CHECK_PATTERN_INITIALIZER \
588  { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
589    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
590    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
591    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
592    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
593    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
594    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
595    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 }
596
597/*
598 *  Amount of extra stack (above minimum stack size) required by
599 *  MPCI receive server thread.  Remember that in a multiprocessor
600 *  system this thread must exist and be able to process all directives.
601 */
602
603#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
604
605/*
606 *  This is defined if the port has a special way to report the ISR nesting
607 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
608 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
609 *  being maintained (e.g. watchdog queues).
610 */
611
612#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
613
614/*
615 *  ISR handler macros
616 */
617
618/*
619 *  Disable all interrupts for an RTEMS critical section.  The previous
620 *  level is returned in _isr_cookie.
621 */
622
623#ifndef ASM
624
625RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
626{
627  return ( level & MSR_EE ) != 0;
628}
629
630static inline uint32_t   _CPU_ISR_Get_level( void )
631{
632  register unsigned int msr;
633  _CPU_MSR_GET(msr);
634  if (msr & MSR_EE) return 0;
635  else  return 1;
636}
637
638static inline void _CPU_ISR_Set_level( uint32_t   level )
639{
640  register unsigned int msr;
641  _CPU_MSR_GET(msr);
642  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
643    msr |= ppc_interrupt_get_disable_mask();
644  }
645  else {
646    msr &= ~ppc_interrupt_get_disable_mask();
647  }
648  _CPU_MSR_SET(msr);
649}
650
651void BSP_panic(char *);
652
653/* Fatal Error manager macros */
654
655/*
656 *  This routine copies _error into a known place -- typically a stack
657 *  location or a register, optionally disables interrupts, and
658 *  halts/stops the CPU.
659 */
660
661void _BSP_Fatal_error(unsigned int);
662
663#endif /* ASM */
664
665#define _CPU_Fatal_halt( _source, _error ) \
666  _BSP_Fatal_error(_error)
667
668/* end of Fatal Error manager macros */
669
670/*
671 *  Should be large enough to run all RTEMS tests.  This ensures
672 *  that a "reasonable" small application should not have any problems.
673 */
674
675#define CPU_STACK_MINIMUM_SIZE          (1024*8)
676
677#define CPU_SIZEOF_POINTER 4
678
679/*
680 *  CPU's worst alignment requirement for data types on a byte boundary.  This
681 *  alignment does not take into account the requirements for the stack.
682 */
683
684#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
685
686/*
687 *  This number corresponds to the byte alignment requirement for the
688 *  heap handler.  This alignment requirement may be stricter than that
689 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
690 *  common for the heap to follow the same alignment requirement as
691 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
692 *  then this should be set to CPU_ALIGNMENT.
693 *
694 *  NOTE:  This does not have to be a power of 2.  It does have to
695 *         be greater or equal to than CPU_ALIGNMENT.
696 */
697
698#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
699
700/*
701 *  This number corresponds to the byte alignment requirement for memory
702 *  buffers allocated by the partition manager.  This alignment requirement
703 *  may be stricter than that for the data types alignment specified by
704 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
705 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
706 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
707 *
708 *  NOTE:  This does not have to be a power of 2.  It does have to
709 *         be greater or equal to than CPU_ALIGNMENT.
710 */
711
712#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
713
714/*
715 *  This number corresponds to the byte alignment requirement for the
716 *  stack.  This alignment requirement may be stricter than that for the
717 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
718 *  is strict enough for the stack, then this should be set to 0.
719 *
720 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
721 */
722
723#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
724
725#ifndef ASM
726/*  The following routine swaps the endian format of an unsigned int.
727 *  It must be static because it is referenced indirectly.
728 *
729 *  This version will work on any processor, but if there is a better
730 *  way for your CPU PLEASE use it.  The most common way to do this is to:
731 *
732 *     swap least significant two bytes with 16-bit rotate
733 *     swap upper and lower 16-bits
734 *     swap most significant two bytes with 16-bit rotate
735 *
736 *  Some CPUs have special instructions which swap a 32-bit quantity in
737 *  a single instruction (e.g. i486).  It is probably best to avoid
738 *  an "endian swapping control bit" in the CPU.  One good reason is
739 *  that interrupts would probably have to be disabled to ensure that
740 *  an interrupt does not try to access the same "chunk" with the wrong
741 *  endian.  Another good reason is that on some CPUs, the endian bit
742 *  endianness for ALL fetches -- both code and data -- so the code
743 *  will be fetched incorrectly.
744 */
745
746static inline uint32_t CPU_swap_u32(
747  uint32_t value
748)
749{
750  uint32_t   swapped;
751
752  __asm__ volatile("rlwimi %0,%1,8,24,31;"
753               "rlwimi %0,%1,24,16,23;"
754               "rlwimi %0,%1,8,8,15;"
755               "rlwimi %0,%1,24,0,7;" :
756               "=&r" ((swapped)) : "r" ((value)));
757
758  return( swapped );
759}
760
761#define CPU_swap_u16( value ) \
762  (((value&0xff) << 8) | ((value >> 8)&0xff))
763
764typedef uint32_t CPU_Counter_ticks;
765
766static inline CPU_Counter_ticks _CPU_Counter_read( void )
767{
768  CPU_Counter_ticks value;
769
770#if defined(__PPC_CPU_E6500__)
771  /* Use Alternate Time Base */
772  __asm__ volatile( "mfspr %0, 526" : "=r" (value) );
773#else
774  __asm__ volatile( "mfspr %0, 268" : "=r" (value) );
775#endif
776
777  return value;
778}
779
780static inline CPU_Counter_ticks _CPU_Counter_difference(
781  CPU_Counter_ticks second,
782  CPU_Counter_ticks first
783)
784{
785  return second - first;
786}
787
788#endif /* ASM */
789
790
791#ifndef ASM
792/* Context handler macros */
793
794/*
795 *  Initialize the context to a state suitable for starting a
796 *  task after a context restore operation.  Generally, this
797 *  involves:
798 *
799 *     - setting a starting address
800 *     - preparing the stack
801 *     - preparing the stack and frame pointers
802 *     - setting the proper interrupt level in the context
803 *     - initializing the floating point context
804 *
805 *  This routine generally does not set any unnecessary register
806 *  in the context.  The state of the "general data" registers is
807 *  undefined at task start time.
808 */
809
810void _CPU_Context_Initialize(
811  Context_Control  *the_context,
812  uint32_t         *stack_base,
813  uint32_t          size,
814  uint32_t          new_level,
815  void             *entry_point,
816  bool              is_fp,
817  void             *tls_area
818);
819
820/*
821 *  This routine is responsible for somehow restarting the currently
822 *  executing task.  If you are lucky, then all that is necessary
823 *  is restoring the context.  Otherwise, there will need to be
824 *  a special assembly routine which does something special in this
825 *  case.  Context_Restore should work most of the time.  It will
826 *  not work if restarting self conflicts with the stack frame
827 *  assumptions of restoring a context.
828 */
829
830#define _CPU_Context_Restart_self( _the_context ) \
831   _CPU_Context_restore( (_the_context) );
832
833/*
834 *  This routine initializes the FP context area passed to it to.
835 *  There are a few standard ways in which to initialize the
836 *  floating point context.  The code included for this macro assumes
837 *  that this is a CPU in which a "initial" FP context was saved into
838 *  _CPU_Null_fp_context and it simply copies it to the destination
839 *  context passed to it.
840 *
841 *  Other models include (1) not doing anything, and (2) putting
842 *  a "null FP status word" in the correct place in the FP context.
843 */
844
845#define _CPU_Context_Initialize_fp( _destination ) \
846  memset( *(_destination), 0, sizeof( **(_destination) ) )
847
848/* end of Context handler macros */
849#endif /* ASM */
850
851#ifndef ASM
852/* Bitfield handler macros */
853
854#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
855
856/*
857 *  This routine sets _output to the bit number of the first bit
858 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
859 *  This type may be either 16 or 32 bits wide although only the 16
860 *  least significant bits will be used.
861 *
862 *  There are a number of variables in using a "find first bit" type
863 *  instruction.
864 *
865 *    (1) What happens when run on a value of zero?
866 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
867 *    (3) The numbering may be zero or one based.
868 *    (4) The "find first bit" instruction may search from MSB or LSB.
869 *
870 *  RTEMS guarantees that (1) will never happen so it is not a concern.
871 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
872 *  _CPU_Priority_Bits_index().  These three form a set of routines
873 *  which must logically operate together.  Bits in the _value are
874 *  set and cleared based on masks built by _CPU_Priority_mask().
875 *  The basic major and minor values calculated by _Priority_Major()
876 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
877 *  to properly range between the values returned by the "find first bit"
878 *  instruction.  This makes it possible for _Priority_Get_highest() to
879 *  calculate the major and directly index into the minor table.
880 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
881 *  is the first bit found.
882 *
883 *  This entire "find first bit" and mapping process depends heavily
884 *  on the manner in which a priority is broken into a major and minor
885 *  components with the major being the 4 MSB of a priority and minor
886 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
887 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
888 *  to the lowest priority.
889 *
890 *  If your CPU does not have a "find first bit" instruction, then
891 *  there are ways to make do without it.  Here are a handful of ways
892 *  to implement this in software:
893 *
894 *    - a series of 16 bit test instructions
895 *    - a "binary search using if's"
896 *    - _number = 0
897 *      if _value > 0x00ff
898 *        _value >>=8
899 *        _number = 8;
900 *
901 *      if _value > 0x0000f
902 *        _value >=8
903 *        _number += 4
904 *
905 *      _number += bit_set_table[ _value ]
906 *
907 *    where bit_set_table[ 16 ] has values which indicate the first
908 *      bit set
909 */
910
911#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
912  { \
913    __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
914                  "1" ((_value))); \
915    (_output) = (_output) - 16; \
916  }
917
918/* end of Bitfield handler macros */
919
920/*
921 *  This routine builds the mask which corresponds to the bit fields
922 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
923 *  for that routine.
924 */
925
926#define _CPU_Priority_Mask( _bit_number ) \
927  ( 0x8000u >> (_bit_number) )
928
929/*
930 *  This routine translates the bit numbers returned by
931 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
932 *  a major or minor component of a priority.  See the discussion
933 *  for that routine.
934 */
935
936#define _CPU_Priority_bits_index( _priority ) \
937  (_priority)
938
939/* end of Priority handler macros */
940#endif /* ASM */
941
942/* functions */
943
944#ifndef ASM
945
946/*
947 *  _CPU_Initialize
948 *
949 *  This routine performs CPU dependent initialization.
950 */
951
952void _CPU_Initialize(void);
953
954/*
955 *  _CPU_ISR_install_vector
956 *
957 *  This routine installs an interrupt vector.
958 */
959
960void _CPU_ISR_install_vector(
961  uint32_t    vector,
962  proc_ptr    new_handler,
963  proc_ptr   *old_handler
964);
965
966/*
967 *  _CPU_Context_switch
968 *
969 *  This routine switches from the run context to the heir context.
970 */
971
972void _CPU_Context_switch(
973  Context_Control  *run,
974  Context_Control  *heir
975);
976
977/*
978 *  _CPU_Context_restore
979 *
980 *  This routine is generallu used only to restart self in an
981 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
982 *
983 *  NOTE: May be unnecessary to reload some registers.
984 */
985
986void _CPU_Context_restore(
987  Context_Control *new_context
988) RTEMS_NO_RETURN;
989
990/*
991 *  _CPU_Context_save_fp
992 *
993 *  This routine saves the floating point context passed to it.
994 */
995
996void _CPU_Context_save_fp(
997  Context_Control_fp **fp_context_ptr
998);
999
1000/*
1001 *  _CPU_Context_restore_fp
1002 *
1003 *  This routine restores the floating point context passed to it.
1004 */
1005
1006void _CPU_Context_restore_fp(
1007  Context_Control_fp **fp_context_ptr
1008);
1009
1010void _CPU_Context_volatile_clobber( uintptr_t pattern );
1011
1012void _CPU_Context_validate( uintptr_t pattern );
1013
1014#ifdef RTEMS_SMP
1015  uint32_t _CPU_SMP_Initialize( void );
1016
1017  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1018
1019  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1020
1021  void _CPU_SMP_Prepare_start_multitasking( void );
1022
1023  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1024  {
1025    uint32_t pir;
1026
1027    /* Use Book E Processor ID Register (PIR) */
1028    __asm__ volatile (
1029      "mfspr %[pir], 286"
1030      : [pir] "=&r" (pir)
1031    );
1032
1033    return pir;
1034  }
1035
1036  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1037
1038  static inline void _CPU_SMP_Processor_event_broadcast( void )
1039  {
1040    __asm__ volatile ( "" : : : "memory" );
1041  }
1042
1043  static inline void _CPU_SMP_Processor_event_receive( void )
1044  {
1045    __asm__ volatile ( "" : : : "memory" );
1046  }
1047#endif
1048
1049typedef struct {
1050  uint32_t EXC_SRR0;
1051  uint32_t EXC_SRR1;
1052  uint32_t _EXC_number;
1053  uint32_t EXC_CR;
1054  uint32_t EXC_CTR;
1055  uint32_t EXC_XER;
1056  uint32_t EXC_LR;
1057  #ifdef __SPE__
1058    uint32_t EXC_SPEFSCR;
1059    uint64_t EXC_ACC;
1060  #endif
1061  PPC_GPR_TYPE GPR0;
1062  PPC_GPR_TYPE GPR1;
1063  PPC_GPR_TYPE GPR2;
1064  PPC_GPR_TYPE GPR3;
1065  PPC_GPR_TYPE GPR4;
1066  PPC_GPR_TYPE GPR5;
1067  PPC_GPR_TYPE GPR6;
1068  PPC_GPR_TYPE GPR7;
1069  PPC_GPR_TYPE GPR8;
1070  PPC_GPR_TYPE GPR9;
1071  PPC_GPR_TYPE GPR10;
1072  PPC_GPR_TYPE GPR11;
1073  PPC_GPR_TYPE GPR12;
1074  PPC_GPR_TYPE GPR13;
1075  PPC_GPR_TYPE GPR14;
1076  PPC_GPR_TYPE GPR15;
1077  PPC_GPR_TYPE GPR16;
1078  PPC_GPR_TYPE GPR17;
1079  PPC_GPR_TYPE GPR18;
1080  PPC_GPR_TYPE GPR19;
1081  PPC_GPR_TYPE GPR20;
1082  PPC_GPR_TYPE GPR21;
1083  PPC_GPR_TYPE GPR22;
1084  PPC_GPR_TYPE GPR23;
1085  PPC_GPR_TYPE GPR24;
1086  PPC_GPR_TYPE GPR25;
1087  PPC_GPR_TYPE GPR26;
1088  PPC_GPR_TYPE GPR27;
1089  PPC_GPR_TYPE GPR28;
1090  PPC_GPR_TYPE GPR29;
1091  PPC_GPR_TYPE GPR30;
1092  PPC_GPR_TYPE GPR31;
1093  #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU)
1094    uint32_t reserved_for_alignment;
1095  #endif
1096  #ifdef PPC_MULTILIB_ALTIVEC
1097    uint32_t VRSAVE;
1098
1099    /* This field must take stvewx/lvewx requirements into account */
1100    uint32_t VSCR;
1101
1102    uint8_t V0[16];
1103    uint8_t V1[16];
1104    uint8_t V2[16];
1105    uint8_t V3[16];
1106    uint8_t V4[16];
1107    uint8_t V5[16];
1108    uint8_t V6[16];
1109    uint8_t V7[16];
1110    uint8_t V8[16];
1111    uint8_t V9[16];
1112    uint8_t V10[16];
1113    uint8_t V11[16];
1114    uint8_t V12[16];
1115    uint8_t V13[16];
1116    uint8_t V14[16];
1117    uint8_t V15[16];
1118    uint8_t V16[16];
1119    uint8_t V17[16];
1120    uint8_t V18[16];
1121    uint8_t V19[16];
1122    uint8_t V20[16];
1123    uint8_t V21[16];
1124    uint8_t V22[16];
1125    uint8_t V23[16];
1126    uint8_t V24[16];
1127    uint8_t V25[16];
1128    uint8_t V26[16];
1129    uint8_t V27[16];
1130    uint8_t V28[16];
1131    uint8_t V29[16];
1132    uint8_t V30[16];
1133    uint8_t V31[16];
1134  #endif
1135  #ifdef PPC_MULTILIB_FPU
1136    double F0;
1137    double F1;
1138    double F2;
1139    double F3;
1140    double F4;
1141    double F5;
1142    double F6;
1143    double F7;
1144    double F8;
1145    double F9;
1146    double F10;
1147    double F11;
1148    double F12;
1149    double F13;
1150    double F14;
1151    double F15;
1152    double F16;
1153    double F17;
1154    double F18;
1155    double F19;
1156    double F20;
1157    double F21;
1158    double F22;
1159    double F23;
1160    double F24;
1161    double F25;
1162    double F26;
1163    double F27;
1164    double F28;
1165    double F29;
1166    double F30;
1167    double F31;
1168    uint64_t FPSCR;
1169  #endif
1170} CPU_Exception_frame;
1171
1172void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1173
1174/*
1175 * _CPU_Initialize_altivec()
1176 *
1177 * Global altivec-related initialization.
1178 */
1179void
1180_CPU_Initialize_altivec(void);
1181
1182/*
1183 * _CPU_Context_switch_altivec
1184 *
1185 * This routine switches the altivec contexts passed to it.
1186 */
1187
1188void
1189_CPU_Context_switch_altivec(
1190  ppc_context *from,
1191  ppc_context *to
1192);
1193
1194/*
1195 * _CPU_Context_restore_altivec
1196 *
1197 * This routine restores the altivec context passed to it.
1198 */
1199
1200void
1201_CPU_Context_restore_altivec(
1202  ppc_context *ctxt
1203);
1204
1205/*
1206 * _CPU_Context_initialize_altivec
1207 *
1208 * This routine initializes the altivec context passed to it.
1209 */
1210
1211void
1212_CPU_Context_initialize_altivec(
1213  ppc_context *ctxt
1214);
1215
1216void _CPU_Fatal_error(
1217  uint32_t   _error
1218);
1219
1220#endif /* ASM */
1221
1222#ifdef __cplusplus
1223}
1224#endif
1225
1226#endif /* _RTEMS_SCORE_CPU_H */
Note: See TracBrowser for help on using the repository browser.