source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ 1869bb7

4.115
Last change on this file since 1869bb7 was 1869bb7, checked in by Sebastian Huber <sebastian.huber@…>, on May 18, 2012 at 1:47:23 PM

powerpc: Simplify context switch

PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the eabi() function).

The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.

The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.

  • Property mode set to 100644
File size: 32.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2012.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  COPYRIGHT (c) 1995 i-cubed ltd.
10 *
11 *  To anyone who acknowledges that this file is provided "AS IS"
12 *  without any express or implied warranty:
13 *      permission to use, copy, modify, and distribute this file
14 *      for any purpose is hereby granted without fee, provided that
15 *      the above copyright notice and this notice appears in all
16 *      copies, and that the name of i-cubed limited not be used in
17 *      advertising or publicity pertaining to distribution of the
18 *      software without specific, written prior permission.
19 *      i-cubed limited makes no representations about the suitability
20 *      of this software for any purpose.
21 *
22 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
23 *
24 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
25 *
26 *  Copyright (c) 2010-2012 embedded brains GmbH.
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
30 *  http://www.rtems.com/license/LICENSE.
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#include <rtems/score/types.h>
37#include <rtems/score/powerpc.h>
38#include <rtems/powerpc/registers.h>
39
40#ifndef ASM
41  #include <string.h> /* for memset() */
42#endif
43
44#ifdef __cplusplus
45extern "C" {
46#endif
47
48/* conditional compilation parameters */
49
50/*
51 *  Should the calls to _Thread_Enable_dispatch be inlined?
52 *
53 *  If TRUE, then they are inlined.
54 *  If FALSE, then a subroutine call is made.
55 *
56 *  Basically this is an example of the classic trade-off of size
57 *  versus speed.  Inlining the call (TRUE) typically increases the
58 *  size of RTEMS while speeding up the enabling of dispatching.
59 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
60 *  only be 0 or 1 unless you are in an interrupt handler and that
61 *  interrupt handler invokes the executive.]  When not inlined
62 *  something calls _Thread_Enable_dispatch which in turns calls
63 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
64 *  one subroutine call is avoided entirely.]
65 */
66
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/*
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 */
86
87#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
88
89/*
90 *  Does this port provide a CPU dependent IDLE task implementation?
91 *
92 *  If TRUE, then the routine _CPU_Thread_Idle_body
93 *  must be provided and is the default IDLE thread body instead of
94 *  _CPU_Thread_Idle_body.
95 *
96 *  If FALSE, then use the generic IDLE thread body if the BSP does
97 *  not provide one.
98 *
99 *  This is intended to allow for supporting processors which have
100 *  a low power or idle mode.  When the IDLE thread is executed, then
101 *  the CPU can be powered down.
102 *
103 *  The order of precedence for selecting the IDLE thread body is:
104 *
105 *    1.  BSP provided
106 *    2.  CPU dependent (if provided)
107 *    3.  generic (if no BSP and no CPU dependent)
108 */
109
110#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
111
112/*
113 *  Does the stack grow up (toward higher addresses) or down
114 *  (toward lower addresses)?
115 *
116 *  If TRUE, then the grows upward.
117 *  If FALSE, then the grows toward smaller addresses.
118 */
119
120#define CPU_STACK_GROWS_UP               FALSE
121
122/*
123 *  The following is the variable attribute used to force alignment
124 *  of critical RTEMS structures.  On some processors it may make
125 *  sense to have these aligned on tighter boundaries than
126 *  the minimum requirements of the compiler in order to have as
127 *  much of the critical data area as possible in a cache line.
128 *
129 *  The placement of this macro in the declaration of the variables
130 *  is based on the syntactically requirements of the GNU C
131 *  "__attribute__" extension.  For example with GNU C, use
132 *  the following to force a structures to a 32 byte boundary.
133 *
134 *      __attribute__ ((aligned (32)))
135 *
136 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
137 *         To benefit from using this, the data must be heavily
138 *         used so it will stay in the cache and used frequently enough
139 *         in the executive to justify turning this on.
140 */
141
142#define CPU_STRUCTURE_ALIGNMENT \
143  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
144
145#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
146
147/*
148 *  Define what is required to specify how the network to host conversion
149 *  routines are handled.
150 */
151
152#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
153#define CPU_BIG_ENDIAN                           TRUE
154#define CPU_LITTLE_ENDIAN                        FALSE
155#else
156#define CPU_BIG_ENDIAN                           FALSE
157#define CPU_LITTLE_ENDIAN                        TRUE
158#endif
159
160/*
161 *  Does the CPU have hardware floating point?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
165 *
166 *  If there is a FP coprocessor such as the i387 or mc68881, then
167 *  the answer is TRUE.
168 *
169 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
170 *  It indicates whether or not this CPU model has FP support.  For
171 *  example, it would be possible to have an i386_nofp CPU model
172 *  which set this to false to indicate that you have an i386 without
173 *  an i387 and wish to leave floating point support out of RTEMS.
174 */
175
176#if ( PPC_HAS_FPU == 1 )
177#define CPU_HARDWARE_FP     TRUE
178#define CPU_SOFTWARE_FP     FALSE
179#else
180#define CPU_HARDWARE_FP     FALSE
181#define CPU_SOFTWARE_FP     FALSE
182#endif
183
184/*
185 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
186 *
187 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
188 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
189 *
190 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
191 *
192 *  PowerPC Note: It appears the GCC can implicitly generate FPU
193 *  and Altivec instructions when you least expect them.  So make
194 *  all tasks floating point.
195 */
196
197#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
198
199/*
200 *  Should the IDLE task have a floating point context?
201 *
202 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
203 *  and it has a floating point context which is switched in and out.
204 *  If FALSE, then the IDLE task does not have a floating point context.
205 *
206 *  Setting this to TRUE negatively impacts the time required to preempt
207 *  the IDLE task from an interrupt because the floating point context
208 *  must be saved as part of the preemption.
209 */
210
211#define CPU_IDLE_TASK_IS_FP      FALSE
212
213/*
214 *  Processor defined structures required for cpukit/score.
215 */
216
217/*
218 * Contexts
219 *
220 *  Generally there are 2 types of context to save.
221 *     1. Interrupt registers to save
222 *     2. Task level registers to save
223 *
224 *  This means we have the following 3 context items:
225 *     1. task level context stuff::  Context_Control
226 *     2. floating point task stuff:: Context_Control_fp
227 *     3. special interrupt level context :: Context_Control_interrupt
228 *
229 *  On some processors, it is cost-effective to save only the callee
230 *  preserved registers during a task context switch.  This means
231 *  that the ISR code needs to save those registers which do not
232 *  persist across function calls.  It is not mandatory to make this
233 *  distinctions between the caller/callee saves registers for the
234 *  purpose of minimizing context saved during task switch and on interrupts.
235 *  If the cost of saving extra registers is minimal, simplicity is the
236 *  choice.  Save the same context on interrupt entry as for tasks in
237 *  this case.
238 *
239 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
240 *  care should be used in designing the context area.
241 *
242 *  On some CPUs with hardware floating point support, the Context_Control_fp
243 *  structure will not be used or it simply consist of an array of a
244 *  fixed number of bytes.   This is done when the floating point context
245 *  is dumped by a "FP save context" type instruction and the format
246 *  is not really defined by the CPU.  In this case, there is no need
247 *  to figure out the exact format -- only the size.  Of course, although
248 *  this is enough information for RTEMS, it is probably not enough for
249 *  a debugger such as gdb.  But that is another problem.
250 */
251
252#ifndef __SPE__
253  #define PPC_GPR_TYPE uint32_t
254  #define PPC_GPR_SIZE 4
255  #define PPC_GPR_LOAD lwz
256  #define PPC_GPR_STORE stw
257#else
258  #define PPC_GPR_TYPE uint64_t
259  #define PPC_GPR_SIZE 8
260  #define PPC_GPR_LOAD evldd
261  #define PPC_GPR_STORE evstdd
262#endif
263
264#define PPC_DEFAULT_CACHE_LINE_SIZE 32
265
266#ifndef ASM
267
268/* Non-volatile context according to E500ABIUG and EABI */
269typedef struct {
270  uint32_t gpr1;
271  uint32_t msr;
272  uint32_t lr;
273  uint32_t cr;
274  PPC_GPR_TYPE gpr14;
275  PPC_GPR_TYPE gpr15;
276  PPC_GPR_TYPE gpr16;
277  PPC_GPR_TYPE gpr17;
278  PPC_GPR_TYPE gpr18;
279  PPC_GPR_TYPE gpr19;
280  PPC_GPR_TYPE gpr20;
281  PPC_GPR_TYPE gpr21;
282  PPC_GPR_TYPE gpr22;
283  PPC_GPR_TYPE gpr23;
284  PPC_GPR_TYPE gpr24;
285  PPC_GPR_TYPE gpr25;
286  PPC_GPR_TYPE gpr26;
287  PPC_GPR_TYPE gpr27;
288  PPC_GPR_TYPE gpr28;
289  PPC_GPR_TYPE gpr29;
290  PPC_GPR_TYPE gpr30;
291  PPC_GPR_TYPE gpr31;
292  #ifdef __ALTIVEC__
293    /*
294     * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
295     * and padding to ensure cache-alignment.  Unfortunately, we can't verify
296     * the cache line size here in the cpukit but altivec support code will
297     * produce an error if this is ever different from 32 bytes.
298     *
299     * Note: it is the BSP/CPU-support's responsibility to save/restore
300     *       volatile vregs across interrupts and exceptions.
301     */
302    uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
303  #endif
304} ppc_context;
305
306typedef struct {
307  uint8_t context [
308    PPC_DEFAULT_CACHE_LINE_SIZE
309      + sizeof(ppc_context)
310      + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
311        ? 0
312          : PPC_DEFAULT_CACHE_LINE_SIZE
313            - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
314  ];
315} Context_Control;
316
317static inline ppc_context *ppc_get_context( Context_Control *context )
318{
319  uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
320  uintptr_t mask = clsz - 1;
321  uintptr_t addr = (uintptr_t) context;
322
323  return (ppc_context *) ((addr & ~mask) + clsz);
324}
325
326#define _CPU_Context_Get_SP( _context ) \
327  ppc_get_context(_context)->gpr1
328#endif /* ASM */
329
330#define PPC_CONTEXT_OFFSET_GPR1 32
331#define PPC_CONTEXT_OFFSET_MSR 36
332#define PPC_CONTEXT_OFFSET_LR 40
333#define PPC_CONTEXT_OFFSET_CR 44
334
335#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
336  (((gpr) - 14) * PPC_GPR_SIZE + 48)
337
338#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
339#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
340#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
341#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
342#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
343#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
344#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
345#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
346#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
347#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
348#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
349#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
350#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
351#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
352#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
353#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
354#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
355#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
356
357#ifndef ASM
358typedef struct {
359    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
360     * procedure calls.  However, this would mean that the interrupt
361     * frame had to hold f0-f13, and the fpscr.  And as the majority
362     * of tasks will not have an FP context, we will save the whole
363     * context here.
364     */
365#if (PPC_HAS_DOUBLE == 1)
366    double      f[32];
367    uint64_t    fpscr;
368#else
369    float       f[32];
370    uint32_t    fpscr;
371#endif
372} Context_Control_fp;
373
374typedef struct CPU_Interrupt_frame {
375    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
376    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
377
378    /* This is what is left out of the primary contexts */
379    uint32_t   gpr0;
380    uint32_t   gpr2;            /* play safe */
381    uint32_t   gpr3;
382    uint32_t   gpr4;
383    uint32_t   gpr5;
384    uint32_t   gpr6;
385    uint32_t   gpr7;
386    uint32_t   gpr8;
387    uint32_t   gpr9;
388    uint32_t   gpr10;
389    uint32_t   gpr11;
390    uint32_t   gpr12;
391    uint32_t   gpr13;   /* Play safe */
392    uint32_t   gpr28;   /* For internal use by the IRQ handler */
393    uint32_t   gpr29;   /* For internal use by the IRQ handler */
394    uint32_t   gpr30;   /* For internal use by the IRQ handler */
395    uint32_t   gpr31;   /* For internal use by the IRQ handler */
396    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
397    uint32_t   ctr;
398    uint32_t   xer;
399    uint32_t   lr;
400    uint32_t   pc;
401    uint32_t   msr;
402    uint32_t   pad[3];
403} CPU_Interrupt_frame;
404
405#endif /* ASM */
406
407/*
408 *  Does RTEMS manage a dedicated interrupt stack in software?
409 *
410 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
411 *  If FALSE, nothing is done.
412 *
413 *  If the CPU supports a dedicated interrupt stack in hardware,
414 *  then it is generally the responsibility of the BSP to allocate it
415 *  and set it up.
416 *
417 *  If the CPU does not support a dedicated interrupt stack, then
418 *  the porter has two options: (1) execute interrupts on the
419 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
420 *  interrupt stack.
421 *
422 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
423 *
424 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
425 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
426 *  possible that both are FALSE for a particular CPU.  Although it
427 *  is unclear what that would imply about the interrupt processing
428 *  procedure on that CPU.
429 */
430
431#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
432
433/*
434 *  Does this CPU have hardware support for a dedicated interrupt stack?
435 *
436 *  If TRUE, then it must be installed during initialization.
437 *  If FALSE, then no installation is performed.
438 *
439 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
440 *
441 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
442 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
443 *  possible that both are FALSE for a particular CPU.  Although it
444 *  is unclear what that would imply about the interrupt processing
445 *  procedure on that CPU.
446 */
447
448#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
449
450/*
451 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
452 *
453 *  If TRUE, then the memory is allocated during initialization.
454 *  If FALSE, then the memory is allocated during initialization.
455 *
456 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
457 */
458
459#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
460
461/*
462 *  Does the RTEMS invoke the user's ISR with the vector number and
463 *  a pointer to the saved interrupt frame (1) or just the vector
464 *  number (0)?
465 */
466
467#define CPU_ISR_PASSES_FRAME_POINTER 0
468
469/*
470 *  Should the saving of the floating point registers be deferred
471 *  until a context switch is made to another different floating point
472 *  task?
473 *
474 *  If TRUE, then the floating point context will not be stored until
475 *  necessary.  It will remain in the floating point registers and not
476 *  disturned until another floating point task is switched to.
477 *
478 *  If FALSE, then the floating point context is saved when a floating
479 *  point task is switched out and restored when the next floating point
480 *  task is restored.  The state of the floating point registers between
481 *  those two operations is not specified.
482 *
483 *  If the floating point context does NOT have to be saved as part of
484 *  interrupt dispatching, then it should be safe to set this to TRUE.
485 *
486 *  Setting this flag to TRUE results in using a different algorithm
487 *  for deciding when to save and restore the floating point context.
488 *  The deferred FP switch algorithm minimizes the number of times
489 *  the FP context is saved and restored.  The FP context is not saved
490 *  until a context switch is made to another, different FP task.
491 *  Thus in a system with only one FP task, the FP context will never
492 *  be saved or restored.
493 *
494 *  Note, however that compilers may use floating point registers/
495 *  instructions for optimization or they may save/restore FP registers
496 *  on the stack. You must not use deferred switching in these cases
497 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
498 *  exception.
499 */
500/*
501 *  ACB Note:  This could make debugging tricky..
502 */
503
504/* conservative setting (FALSE); probably doesn't affect performance too much */
505#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
506
507/*
508 *  Processor defined structures required for cpukit/score.
509 */
510
511#ifndef ASM
512
513/*
514 *  This variable is optional.  It is used on CPUs on which it is difficult
515 *  to generate an "uninitialized" FP context.  It is filled in by
516 *  _CPU_Initialize and copied into the task's FP context area during
517 *  _CPU_Context_Initialize.
518 */
519
520/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
521
522#endif /* ndef ASM */
523
524/*
525 *  This defines the number of levels and the mask used to pick those
526 *  bits out of a thread mode.
527 */
528
529#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
530#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
531
532/*
533 *  Nothing prevents the porter from declaring more CPU specific variables.
534 */
535
536#ifndef ASM
537
538SCORE_EXTERN struct {
539  uint32_t      *Disable_level;
540  void          *Stack;
541  volatile bool *Switch_necessary;
542  bool          *Signal;
543
544} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
545
546#endif /* ndef ASM */
547
548/*
549 *  The size of the floating point context area.  On some CPUs this
550 *  will not be a "sizeof" because the format of the floating point
551 *  area is not defined -- only the size is.  This is usually on
552 *  CPUs with a "floating point save context" instruction.
553 */
554
555#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
556
557/*
558 * (Optional) # of bytes for libmisc/stackchk to check
559 * If not specifed, then it defaults to something reasonable
560 * for most architectures.
561 */
562
563#define CPU_STACK_CHECK_SIZE    (128)
564
565/*
566 *  Amount of extra stack (above minimum stack size) required by
567 *  MPCI receive server thread.  Remember that in a multiprocessor
568 *  system this thread must exist and be able to process all directives.
569 */
570
571#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
572
573/*
574 *  This defines the number of entries in the ISR_Vector_table managed
575 *  by RTEMS.
576 *
577 *  NOTE: CPU_INTERRUPT_NUMBER_OF_VECTORS and
578 *        CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER are only used on
579 *        Simple Vectored Architectures and thus are not defined
580 *        for this architecture.
581 */
582
583/*
584 *  This is defined if the port has a special way to report the ISR nesting
585 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
586 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
587 *  being maintained (e.g. watchdog queues).
588 */
589
590#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
591
592/*
593 *  ISR handler macros
594 */
595
596#define _CPU_Initialize_vectors()
597
598/*
599 *  Disable all interrupts for an RTEMS critical section.  The previous
600 *  level is returned in _isr_cookie.
601 */
602
603#ifndef ASM
604
605static inline uint32_t   _CPU_ISR_Get_level( void )
606{
607  register unsigned int msr;
608  _CPU_MSR_GET(msr);
609  if (msr & MSR_EE) return 0;
610  else  return 1;
611}
612
613static inline void _CPU_ISR_Set_level( uint32_t   level )
614{
615  register unsigned int msr;
616  _CPU_MSR_GET(msr);
617  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
618    msr |= ppc_interrupt_get_disable_mask();
619  }
620  else {
621    msr &= ~ppc_interrupt_get_disable_mask();
622  }
623  _CPU_MSR_SET(msr);
624}
625
626void BSP_panic(char *);
627
628/* Fatal Error manager macros */
629
630/*
631 *  This routine copies _error into a known place -- typically a stack
632 *  location or a register, optionally disables interrupts, and
633 *  halts/stops the CPU.
634 */
635
636void _BSP_Fatal_error(unsigned int);
637
638#endif /* ASM */
639
640#define _CPU_Fatal_halt( _error ) \
641  _BSP_Fatal_error(_error)
642
643/* end of Fatal Error manager macros */
644
645/*
646 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
647 * Now SPRG0 is devoted to the interrupt disable mask.
648 */
649
650#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
651
652/*
653 *  Should be large enough to run all RTEMS tests.  This ensures
654 *  that a "reasonable" small application should not have any problems.
655 */
656
657#define CPU_STACK_MINIMUM_SIZE          (1024*8)
658
659/*
660 *  CPU's worst alignment requirement for data types on a byte boundary.  This
661 *  alignment does not take into account the requirements for the stack.
662 */
663
664#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
665
666/*
667 *  This number corresponds to the byte alignment requirement for the
668 *  heap handler.  This alignment requirement may be stricter than that
669 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
670 *  common for the heap to follow the same alignment requirement as
671 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
672 *  then this should be set to CPU_ALIGNMENT.
673 *
674 *  NOTE:  This does not have to be a power of 2.  It does have to
675 *         be greater or equal to than CPU_ALIGNMENT.
676 */
677
678#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
679
680/*
681 *  This number corresponds to the byte alignment requirement for memory
682 *  buffers allocated by the partition manager.  This alignment requirement
683 *  may be stricter than that for the data types alignment specified by
684 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
685 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
686 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
687 *
688 *  NOTE:  This does not have to be a power of 2.  It does have to
689 *         be greater or equal to than CPU_ALIGNMENT.
690 */
691
692#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
693
694/*
695 *  This number corresponds to the byte alignment requirement for the
696 *  stack.  This alignment requirement may be stricter than that for the
697 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
698 *  is strict enough for the stack, then this should be set to 0.
699 *
700 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
701 */
702
703#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
704
705#ifndef ASM
706/*  The following routine swaps the endian format of an unsigned int.
707 *  It must be static because it is referenced indirectly.
708 *
709 *  This version will work on any processor, but if there is a better
710 *  way for your CPU PLEASE use it.  The most common way to do this is to:
711 *
712 *     swap least significant two bytes with 16-bit rotate
713 *     swap upper and lower 16-bits
714 *     swap most significant two bytes with 16-bit rotate
715 *
716 *  Some CPUs have special instructions which swap a 32-bit quantity in
717 *  a single instruction (e.g. i486).  It is probably best to avoid
718 *  an "endian swapping control bit" in the CPU.  One good reason is
719 *  that interrupts would probably have to be disabled to ensure that
720 *  an interrupt does not try to access the same "chunk" with the wrong
721 *  endian.  Another good reason is that on some CPUs, the endian bit
722 *  endianness for ALL fetches -- both code and data -- so the code
723 *  will be fetched incorrectly.
724 */
725
726static inline uint32_t CPU_swap_u32(
727  uint32_t value
728)
729{
730  uint32_t   swapped;
731
732  __asm__ volatile("rlwimi %0,%1,8,24,31;"
733               "rlwimi %0,%1,24,16,23;"
734               "rlwimi %0,%1,8,8,15;"
735               "rlwimi %0,%1,24,0,7;" :
736               "=&r" ((swapped)) : "r" ((value)));
737
738  return( swapped );
739}
740
741#define CPU_swap_u16( value ) \
742  (((value&0xff) << 8) | ((value >> 8)&0xff))
743
744#endif /* ASM */
745
746
747#ifndef ASM
748/* Context handler macros */
749
750/*
751 *  Initialize the context to a state suitable for starting a
752 *  task after a context restore operation.  Generally, this
753 *  involves:
754 *
755 *     - setting a starting address
756 *     - preparing the stack
757 *     - preparing the stack and frame pointers
758 *     - setting the proper interrupt level in the context
759 *     - initializing the floating point context
760 *
761 *  This routine generally does not set any unnecessary register
762 *  in the context.  The state of the "general data" registers is
763 *  undefined at task start time.
764 */
765
766void _CPU_Context_Initialize(
767  Context_Control  *the_context,
768  uint32_t         *stack_base,
769  uint32_t          size,
770  uint32_t          new_level,
771  void             *entry_point,
772  bool              is_fp
773);
774
775/*
776 *  This routine is responsible for somehow restarting the currently
777 *  executing task.  If you are lucky, then all that is necessary
778 *  is restoring the context.  Otherwise, there will need to be
779 *  a special assembly routine which does something special in this
780 *  case.  Context_Restore should work most of the time.  It will
781 *  not work if restarting self conflicts with the stack frame
782 *  assumptions of restoring a context.
783 */
784
785#define _CPU_Context_Restart_self( _the_context ) \
786   _CPU_Context_restore( (_the_context) );
787
788/*
789 *  The purpose of this macro is to allow the initial pointer into
790 *  a floating point context area (used to save the floating point
791 *  context) to be at an arbitrary place in the floating point
792 *  context area.
793 *
794 *  This is necessary because some FP units are designed to have
795 *  their context saved as a stack which grows into lower addresses.
796 *  Other FP units can be saved by simply moving registers into offsets
797 *  from the base of the context area.  Finally some FP units provide
798 *  a "dump context" instruction which could fill in from high to low
799 *  or low to high based on the whim of the CPU designers.
800 */
801
802#define _CPU_Context_Fp_start( _base, _offset ) \
803   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
804
805/*
806 *  This routine initializes the FP context area passed to it to.
807 *  There are a few standard ways in which to initialize the
808 *  floating point context.  The code included for this macro assumes
809 *  that this is a CPU in which a "initial" FP context was saved into
810 *  _CPU_Null_fp_context and it simply copies it to the destination
811 *  context passed to it.
812 *
813 *  Other models include (1) not doing anything, and (2) putting
814 *  a "null FP status word" in the correct place in the FP context.
815 */
816
817#define _CPU_Context_Initialize_fp( _destination ) \
818  memset( *(_destination), 0, sizeof( **(_destination) ) )
819
820/* end of Context handler macros */
821#endif /* ASM */
822
823#ifndef ASM
824/* Bitfield handler macros */
825
826/*
827 *  This routine sets _output to the bit number of the first bit
828 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
829 *  This type may be either 16 or 32 bits wide although only the 16
830 *  least significant bits will be used.
831 *
832 *  There are a number of variables in using a "find first bit" type
833 *  instruction.
834 *
835 *    (1) What happens when run on a value of zero?
836 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
837 *    (3) The numbering may be zero or one based.
838 *    (4) The "find first bit" instruction may search from MSB or LSB.
839 *
840 *  RTEMS guarantees that (1) will never happen so it is not a concern.
841 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
842 *  _CPU_Priority_Bits_index().  These three form a set of routines
843 *  which must logically operate together.  Bits in the _value are
844 *  set and cleared based on masks built by _CPU_Priority_mask().
845 *  The basic major and minor values calculated by _Priority_Major()
846 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
847 *  to properly range between the values returned by the "find first bit"
848 *  instruction.  This makes it possible for _Priority_Get_highest() to
849 *  calculate the major and directly index into the minor table.
850 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
851 *  is the first bit found.
852 *
853 *  This entire "find first bit" and mapping process depends heavily
854 *  on the manner in which a priority is broken into a major and minor
855 *  components with the major being the 4 MSB of a priority and minor
856 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
857 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
858 *  to the lowest priority.
859 *
860 *  If your CPU does not have a "find first bit" instruction, then
861 *  there are ways to make do without it.  Here are a handful of ways
862 *  to implement this in software:
863 *
864 *    - a series of 16 bit test instructions
865 *    - a "binary search using if's"
866 *    - _number = 0
867 *      if _value > 0x00ff
868 *        _value >>=8
869 *        _number = 8;
870 *
871 *      if _value > 0x0000f
872 *        _value >=8
873 *        _number += 4
874 *
875 *      _number += bit_set_table[ _value ]
876 *
877 *    where bit_set_table[ 16 ] has values which indicate the first
878 *      bit set
879 */
880
881#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
882  { \
883    __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
884                  "1" ((_value))); \
885  }
886
887/* end of Bitfield handler macros */
888
889/*
890 *  This routine builds the mask which corresponds to the bit fields
891 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
892 *  for that routine.
893 */
894
895#define _CPU_Priority_Mask( _bit_number ) \
896  ( 0x80000000 >> (_bit_number) )
897
898/*
899 *  This routine translates the bit numbers returned by
900 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
901 *  a major or minor component of a priority.  See the discussion
902 *  for that routine.
903 */
904
905#define _CPU_Priority_bits_index( _priority ) \
906  (_priority)
907
908/* end of Priority handler macros */
909#endif /* ASM */
910
911/* functions */
912
913#ifndef ASM
914
915/*
916 *  _CPU_Initialize
917 *
918 *  This routine performs CPU dependent initialization.
919 */
920
921void _CPU_Initialize(void);
922
923/*
924 *  _CPU_ISR_install_vector
925 *
926 *  This routine installs an interrupt vector.
927 */
928
929void _CPU_ISR_install_vector(
930  uint32_t    vector,
931  proc_ptr    new_handler,
932  proc_ptr   *old_handler
933);
934
935/*
936 *  _CPU_Install_interrupt_stack
937 *
938 *  This routine installs the hardware interrupt stack pointer.
939 *
940 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
941 *         is TRUE.
942 */
943
944void _CPU_Install_interrupt_stack( void );
945
946/*
947 *  _CPU_Context_switch
948 *
949 *  This routine switches from the run context to the heir context.
950 */
951
952void _CPU_Context_switch(
953  Context_Control  *run,
954  Context_Control  *heir
955);
956
957/*
958 *  _CPU_Context_restore
959 *
960 *  This routine is generallu used only to restart self in an
961 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
962 *
963 *  NOTE: May be unnecessary to reload some registers.
964 */
965
966void _CPU_Context_restore(
967  Context_Control *new_context
968) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
969
970/*
971 *  _CPU_Context_save_fp
972 *
973 *  This routine saves the floating point context passed to it.
974 */
975
976void _CPU_Context_save_fp(
977  Context_Control_fp **fp_context_ptr
978);
979
980/*
981 *  _CPU_Context_restore_fp
982 *
983 *  This routine restores the floating point context passed to it.
984 */
985
986void _CPU_Context_restore_fp(
987  Context_Control_fp **fp_context_ptr
988);
989
990/*
991 * _CPU_Initialize_altivec()
992 *
993 * Global altivec-related initialization.
994 */
995void
996_CPU_Initialize_altivec(void);
997
998/*
999 * _CPU_Context_switch_altivec
1000 *
1001 * This routine switches the altivec contexts passed to it.
1002 */
1003
1004void
1005_CPU_Context_switch_altivec(
1006  Context_Control *from,
1007  Context_Control *to
1008);
1009
1010/*
1011 * _CPU_Context_restore_altivec
1012 *
1013 * This routine restores the altivec context passed to it.
1014 */
1015
1016void
1017_CPU_Context_restore_altivec(
1018  Context_Control *ctxt
1019);
1020
1021/*
1022 * _CPU_Context_initialize_altivec
1023 *
1024 * This routine initializes the altivec context passed to it.
1025 */
1026
1027void
1028_CPU_Context_initialize_altivec(
1029  Context_Control *ctxt
1030);
1031
1032void _CPU_Fatal_error(
1033  uint32_t   _error
1034);
1035
1036#endif /* ASM */
1037
1038#ifdef __cplusplus
1039}
1040#endif
1041
1042#endif /* _RTEMS_SCORE_CPU_H */
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