1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * COPYRIGHT (c) 1989-2007. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.com/license/LICENSE. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | #ifndef _RTEMS_SCORE_CPU_H |
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17 | #define _RTEMS_SCORE_CPU_H |
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18 | |
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19 | #include <rtems/score/powerpc.h> /* pick up machine definitions */ |
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20 | #ifndef ASM |
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21 | #include <rtems/score/types.h> |
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22 | #endif |
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23 | |
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24 | /* conditional compilation parameters */ |
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25 | |
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26 | /* |
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27 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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28 | * |
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29 | * If TRUE, then they are inlined. |
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30 | * If FALSE, then a subroutine call is made. |
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31 | * |
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32 | * Basically this is an example of the classic trade-off of size |
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33 | * versus speed. Inlining the call (TRUE) typically increases the |
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34 | * size of RTEMS while speeding up the enabling of dispatching. |
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35 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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36 | * only be 0 or 1 unless you are in an interrupt handler and that |
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37 | * interrupt handler invokes the executive.] When not inlined |
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38 | * something calls _Thread_Enable_dispatch which in turns calls |
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39 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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40 | * one subroutine call is avoided entirely.] |
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41 | */ |
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42 | |
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43 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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44 | |
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45 | /* |
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46 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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47 | * be unrolled one time? In unrolled each iteration of the loop examines |
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48 | * two "nodes" on the chain being searched. Otherwise, only one node |
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49 | * is examined per iteration. |
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50 | * |
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51 | * If TRUE, then the loops are unrolled. |
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52 | * If FALSE, then the loops are not unrolled. |
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53 | * |
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54 | * The primary factor in making this decision is the cost of disabling |
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55 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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56 | * body of the loop. On some CPUs, the flash is more expensive than |
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57 | * one iteration of the loop body. In this case, it might be desirable |
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58 | * to unroll the loop. It is important to note that on some CPUs, this |
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59 | * code is the longest interrupt disable period in RTEMS. So it is |
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60 | * necessary to strike a balance when setting this parameter. |
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61 | */ |
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62 | |
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63 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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64 | |
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65 | /* |
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66 | * Does this port provide a CPU dependent IDLE task implementation? |
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67 | * |
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68 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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69 | * must be provided and is the default IDLE thread body instead of |
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70 | * _CPU_Thread_Idle_body. |
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71 | * |
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72 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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73 | * not provide one. |
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74 | * |
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75 | * This is intended to allow for supporting processors which have |
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76 | * a low power or idle mode. When the IDLE thread is executed, then |
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77 | * the CPU can be powered down. |
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78 | * |
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79 | * The order of precedence for selecting the IDLE thread body is: |
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80 | * |
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81 | * 1. BSP provided |
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82 | * 2. CPU dependent (if provided) |
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83 | * 3. generic (if no BSP and no CPU dependent) |
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84 | */ |
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85 | |
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86 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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87 | |
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88 | /* |
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89 | * Does the stack grow up (toward higher addresses) or down |
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90 | * (toward lower addresses)? |
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91 | * |
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92 | * If TRUE, then the grows upward. |
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93 | * If FALSE, then the grows toward smaller addresses. |
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94 | */ |
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95 | |
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96 | #define CPU_STACK_GROWS_UP FALSE |
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97 | |
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98 | /* |
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99 | * The following is the variable attribute used to force alignment |
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100 | * of critical RTEMS structures. On some processors it may make |
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101 | * sense to have these aligned on tighter boundaries than |
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102 | * the minimum requirements of the compiler in order to have as |
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103 | * much of the critical data area as possible in a cache line. |
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104 | * |
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105 | * The placement of this macro in the declaration of the variables |
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106 | * is based on the syntactically requirements of the GNU C |
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107 | * "__attribute__" extension. For example with GNU C, use |
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108 | * the following to force a structures to a 32 byte boundary. |
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109 | * |
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110 | * __attribute__ ((aligned (32))) |
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111 | * |
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112 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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113 | * To benefit from using this, the data must be heavily |
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114 | * used so it will stay in the cache and used frequently enough |
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115 | * in the executive to justify turning this on. |
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116 | */ |
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117 | |
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118 | #define CPU_STRUCTURE_ALIGNMENT \ |
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119 | __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) |
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120 | |
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121 | /* |
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122 | * Define what is required to specify how the network to host conversion |
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123 | * routines are handled. |
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124 | */ |
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125 | |
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126 | #if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) |
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127 | #define CPU_BIG_ENDIAN TRUE |
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128 | #define CPU_LITTLE_ENDIAN FALSE |
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129 | #else |
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130 | #define CPU_BIG_ENDIAN FALSE |
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131 | #define CPU_LITTLE_ENDIAN TRUE |
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132 | #endif |
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133 | |
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134 | /* |
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135 | * Does the CPU have hardware floating point? |
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136 | * |
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137 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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138 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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139 | * |
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140 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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141 | * the answer is TRUE. |
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142 | * |
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143 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
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144 | * It indicates whether or not this CPU model has FP support. For |
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145 | * example, it would be possible to have an i386_nofp CPU model |
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146 | * which set this to false to indicate that you have an i386 without |
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147 | * an i387 and wish to leave floating point support out of RTEMS. |
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148 | */ |
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149 | |
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150 | #if ( PPC_HAS_FPU == 1 ) |
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151 | #define CPU_HARDWARE_FP TRUE |
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152 | #define CPU_SOFTWARE_FP FALSE |
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153 | #else |
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154 | #define CPU_HARDWARE_FP FALSE |
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155 | #define CPU_SOFTWARE_FP FALSE |
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156 | #endif |
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157 | |
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158 | /* |
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159 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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160 | * |
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161 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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162 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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163 | * |
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164 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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165 | * |
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166 | * PowerPC Note: It appears the GCC can implicitly generate FPU |
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167 | * and Altivec instructions when you least expect them. So make |
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168 | * all tasks floating point. |
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169 | */ |
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170 | |
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171 | #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
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172 | |
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173 | /* |
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174 | * Should the IDLE task have a floating point context? |
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175 | * |
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176 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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177 | * and it has a floating point context which is switched in and out. |
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178 | * If FALSE, then the IDLE task does not have a floating point context. |
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179 | * |
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180 | * Setting this to TRUE negatively impacts the time required to preempt |
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181 | * the IDLE task from an interrupt because the floating point context |
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182 | * must be saved as part of the preemption. |
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183 | */ |
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184 | |
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185 | #define CPU_IDLE_TASK_IS_FP FALSE |
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186 | |
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187 | /* |
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188 | * Processor defined structures required for cpukit/score. |
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189 | */ |
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190 | |
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191 | /* |
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192 | * Contexts |
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193 | * |
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194 | * Generally there are 2 types of context to save. |
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195 | * 1. Interrupt registers to save |
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196 | * 2. Task level registers to save |
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197 | * |
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198 | * This means we have the following 3 context items: |
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199 | * 1. task level context stuff:: Context_Control |
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200 | * 2. floating point task stuff:: Context_Control_fp |
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201 | * 3. special interrupt level context :: Context_Control_interrupt |
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202 | * |
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203 | * On some processors, it is cost-effective to save only the callee |
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204 | * preserved registers during a task context switch. This means |
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205 | * that the ISR code needs to save those registers which do not |
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206 | * persist across function calls. It is not mandatory to make this |
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207 | * distinctions between the caller/callee saves registers for the |
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208 | * purpose of minimizing context saved during task switch and on interrupts. |
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209 | * If the cost of saving extra registers is minimal, simplicity is the |
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210 | * choice. Save the same context on interrupt entry as for tasks in |
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211 | * this case. |
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212 | * |
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213 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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214 | * care should be used in designing the context area. |
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215 | * |
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216 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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217 | * structure will not be used or it simply consist of an array of a |
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218 | * fixed number of bytes. This is done when the floating point context |
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219 | * is dumped by a "FP save context" type instruction and the format |
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220 | * is not really defined by the CPU. In this case, there is no need |
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221 | * to figure out the exact format -- only the size. Of course, although |
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222 | * this is enough information for RTEMS, it is probably not enough for |
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223 | * a debugger such as gdb. But that is another problem. |
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224 | */ |
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225 | |
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226 | #ifndef ASM |
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227 | typedef struct { |
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228 | uint32_t gpr1; /* Stack pointer for all */ |
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229 | uint32_t gpr2; /* Reserved SVR4, section ptr EABI + */ |
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230 | uint32_t gpr13; /* Section ptr SVR4/EABI */ |
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231 | uint32_t gpr14; /* Non volatile for all */ |
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232 | uint32_t gpr15; /* Non volatile for all */ |
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233 | uint32_t gpr16; /* Non volatile for all */ |
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234 | uint32_t gpr17; /* Non volatile for all */ |
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235 | uint32_t gpr18; /* Non volatile for all */ |
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236 | uint32_t gpr19; /* Non volatile for all */ |
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237 | uint32_t gpr20; /* Non volatile for all */ |
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238 | uint32_t gpr21; /* Non volatile for all */ |
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239 | uint32_t gpr22; /* Non volatile for all */ |
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240 | uint32_t gpr23; /* Non volatile for all */ |
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241 | uint32_t gpr24; /* Non volatile for all */ |
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242 | uint32_t gpr25; /* Non volatile for all */ |
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243 | uint32_t gpr26; /* Non volatile for all */ |
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244 | uint32_t gpr27; /* Non volatile for all */ |
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245 | uint32_t gpr28; /* Non volatile for all */ |
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246 | uint32_t gpr29; /* Non volatile for all */ |
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247 | uint32_t gpr30; /* Non volatile for all */ |
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248 | uint32_t gpr31; /* Non volatile for all */ |
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249 | uint32_t cr; /* PART of the CR is non volatile for all */ |
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250 | uint32_t pc; /* Program counter/Link register */ |
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251 | uint32_t msr; /* Initial interrupt level */ |
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252 | } Context_Control; |
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253 | |
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254 | #define _CPU_Context_Get_SP( _context ) \ |
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255 | (_context)->gpr1 |
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256 | |
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257 | typedef struct { |
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258 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
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259 | * procedure calls. However, this would mean that the interrupt |
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260 | * frame had to hold f0-f13, and the fpscr. And as the majority |
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261 | * of tasks will not have an FP context, we will save the whole |
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262 | * context here. |
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263 | */ |
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264 | #if (PPC_HAS_DOUBLE == 1) |
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265 | double f[32]; |
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266 | double fpscr; |
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267 | #else |
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268 | float f[32]; |
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269 | float fpscr; |
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270 | #endif |
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271 | } Context_Control_fp; |
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272 | #endif /* ASM */ |
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273 | |
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274 | #ifndef ASM |
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275 | typedef struct CPU_Interrupt_frame { |
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276 | uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ |
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277 | uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ |
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278 | |
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279 | /* This is what is left out of the primary contexts */ |
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280 | uint32_t gpr0; |
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281 | uint32_t gpr2; /* play safe */ |
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282 | uint32_t gpr3; |
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283 | uint32_t gpr4; |
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284 | uint32_t gpr5; |
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285 | uint32_t gpr6; |
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286 | uint32_t gpr7; |
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287 | uint32_t gpr8; |
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288 | uint32_t gpr9; |
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289 | uint32_t gpr10; |
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290 | uint32_t gpr11; |
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291 | uint32_t gpr12; |
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292 | uint32_t gpr13; /* Play safe */ |
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293 | uint32_t gpr28; /* For internal use by the IRQ handler */ |
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294 | uint32_t gpr29; /* For internal use by the IRQ handler */ |
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295 | uint32_t gpr30; /* For internal use by the IRQ handler */ |
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296 | uint32_t gpr31; /* For internal use by the IRQ handler */ |
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297 | uint32_t cr; /* Bits of this are volatile, so no-one may save */ |
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298 | uint32_t ctr; |
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299 | uint32_t xer; |
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300 | uint32_t lr; |
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301 | uint32_t pc; |
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302 | uint32_t msr; |
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303 | uint32_t pad[3]; |
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304 | } CPU_Interrupt_frame; |
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305 | #endif /* ASM */ |
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306 | |
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307 | #include <rtems/new-exceptions/cpu.h> |
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308 | |
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309 | /* |
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310 | * Should be large enough to run all RTEMS tests. This ensures |
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311 | * that a "reasonable" small application should not have any problems. |
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312 | */ |
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313 | |
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314 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
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315 | |
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316 | /* |
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317 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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318 | * alignment does not take into account the requirements for the stack. |
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319 | */ |
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320 | |
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321 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
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322 | |
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323 | /* |
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324 | * This number corresponds to the byte alignment requirement for the |
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325 | * heap handler. This alignment requirement may be stricter than that |
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326 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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327 | * common for the heap to follow the same alignment requirement as |
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328 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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329 | * then this should be set to CPU_ALIGNMENT. |
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330 | * |
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331 | * NOTE: This does not have to be a power of 2. It does have to |
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332 | * be greater or equal to than CPU_ALIGNMENT. |
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333 | */ |
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334 | |
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335 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
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336 | |
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337 | /* |
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338 | * This number corresponds to the byte alignment requirement for memory |
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339 | * buffers allocated by the partition manager. This alignment requirement |
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340 | * may be stricter than that for the data types alignment specified by |
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341 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
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342 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
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343 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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344 | * |
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345 | * NOTE: This does not have to be a power of 2. It does have to |
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346 | * be greater or equal to than CPU_ALIGNMENT. |
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347 | */ |
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348 | |
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349 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
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350 | |
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351 | /* |
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352 | * This number corresponds to the byte alignment requirement for the |
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353 | * stack. This alignment requirement may be stricter than that for the |
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354 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
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355 | * is strict enough for the stack, then this should be set to 0. |
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356 | * |
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357 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
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358 | */ |
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359 | |
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360 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
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361 | |
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362 | #ifndef ASM |
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363 | /* The following routine swaps the endian format of an unsigned int. |
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364 | * It must be static because it is referenced indirectly. |
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365 | * |
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366 | * This version will work on any processor, but if there is a better |
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367 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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368 | * |
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369 | * swap least significant two bytes with 16-bit rotate |
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370 | * swap upper and lower 16-bits |
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371 | * swap most significant two bytes with 16-bit rotate |
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372 | * |
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373 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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374 | * a single instruction (e.g. i486). It is probably best to avoid |
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375 | * an "endian swapping control bit" in the CPU. One good reason is |
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376 | * that interrupts would probably have to be disabled to ensure that |
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377 | * an interrupt does not try to access the same "chunk" with the wrong |
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378 | * endian. Another good reason is that on some CPUs, the endian bit |
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379 | * endianness for ALL fetches -- both code and data -- so the code |
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380 | * will be fetched incorrectly. |
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381 | */ |
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382 | |
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383 | static inline uint32_t CPU_swap_u32( |
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384 | uint32_t value |
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385 | ) |
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386 | { |
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387 | uint32_t swapped; |
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388 | |
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389 | asm volatile("rlwimi %0,%1,8,24,31;" |
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390 | "rlwimi %0,%1,24,16,23;" |
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391 | "rlwimi %0,%1,8,8,15;" |
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392 | "rlwimi %0,%1,24,0,7;" : |
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393 | "=&r" ((swapped)) : "r" ((value))); |
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394 | |
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395 | return( swapped ); |
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396 | } |
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397 | |
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398 | #define CPU_swap_u16( value ) \ |
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399 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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400 | |
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401 | #endif /* ASM */ |
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402 | |
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403 | #ifndef ASM |
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404 | /* |
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405 | * Simple spin delay in microsecond units for device drivers. |
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406 | * This is very dependent on the clock speed of the target. |
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407 | */ |
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408 | |
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409 | #if 0 |
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410 | /* Wonderful bookE doesn't have mftb/mftbu; they only |
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411 | * define the TBRU/TBRL SPRs so we use these. Luckily, |
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412 | * we run in supervisory mode so that should work on |
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413 | * all CPUs. In user mode we'd have a problem... |
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414 | * 2007/11/30, T.S. |
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415 | * |
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416 | * OTOH, PSIM currently lacks support for reading |
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417 | * SPRs 268/269. You need GDB patch sim/2376 to avoid |
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418 | * a crash... |
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419 | */ |
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420 | #define CPU_Get_timebase_low( _value ) \ |
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421 | asm volatile( "mftb %0" : "=r" (_value) ) |
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422 | #else |
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423 | #define CPU_Get_timebase_low( _value ) \ |
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424 | asm volatile( "mfspr %0,268" : "=r" (_value) ) |
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425 | #endif |
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426 | |
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427 | #define rtems_bsp_delay( _microseconds ) \ |
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428 | do { \ |
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429 | uint32_t start, ticks, now; \ |
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430 | extern uint32_t bsp_clicks_per_usec; \ |
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431 | CPU_Get_timebase_low( start ) ; \ |
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432 | ticks = (_microseconds) * bsp_clicks_per_usec; \ |
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433 | do \ |
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434 | CPU_Get_timebase_low( now ) ; \ |
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435 | while (now - start < ticks); \ |
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436 | } while (0) |
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437 | |
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438 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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439 | do { \ |
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440 | uint32_t start, now; \ |
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441 | CPU_Get_timebase_low( start ); \ |
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442 | do \ |
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443 | CPU_Get_timebase_low( now ); \ |
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444 | while (now - start < (_cycles)); \ |
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445 | } while (0) |
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446 | |
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447 | #endif /* ASM */ |
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448 | |
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449 | #ifndef ASM |
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450 | /* |
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451 | * Routines to access the decrementer register |
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452 | */ |
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453 | |
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454 | #define PPC_Set_decrementer( _clicks ) \ |
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455 | do { \ |
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456 | asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ |
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457 | } while (0) |
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458 | |
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459 | #define PPC_Get_decrementer( _clicks ) \ |
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460 | asm volatile( "mfdec %0" : "=r" (_clicks) ) |
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461 | |
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462 | #endif /* ASM */ |
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463 | |
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464 | #ifndef ASM |
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465 | /* |
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466 | * Routines to access the time base register |
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467 | */ |
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468 | |
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469 | static inline uint64_t PPC_Get_timebase_register( void ) |
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470 | { |
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471 | uint32_t tbr_low; |
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472 | uint32_t tbr_high; |
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473 | uint32_t tbr_high_old; |
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474 | uint64_t tbr; |
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475 | |
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476 | do { |
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477 | #if 0 |
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478 | /* See comment above (CPU_Get_timebase_low) */ |
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479 | asm volatile( "mftbu %0" : "=r" (tbr_high_old)); |
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480 | asm volatile( "mftb %0" : "=r" (tbr_low)); |
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481 | asm volatile( "mftbu %0" : "=r" (tbr_high)); |
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482 | #else |
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483 | asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); |
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484 | asm volatile( "mfspr %0, 268" : "=r" (tbr_low)); |
---|
485 | asm volatile( "mfspr %0, 269" : "=r" (tbr_high)); |
---|
486 | #endif |
---|
487 | } while ( tbr_high_old != tbr_high ); |
---|
488 | |
---|
489 | tbr = tbr_high; |
---|
490 | tbr <<= 32; |
---|
491 | tbr |= tbr_low; |
---|
492 | return tbr; |
---|
493 | } |
---|
494 | |
---|
495 | static inline void PPC_Set_timebase_register (uint64_t tbr) |
---|
496 | { |
---|
497 | uint32_t tbr_low; |
---|
498 | uint32_t tbr_high; |
---|
499 | |
---|
500 | tbr_low = (tbr & 0xffffffff) ; |
---|
501 | tbr_high = (tbr >> 32) & 0xffffffff; |
---|
502 | asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); |
---|
503 | asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); |
---|
504 | |
---|
505 | } |
---|
506 | #endif /* ASM */ |
---|
507 | |
---|
508 | #ifndef ASM |
---|
509 | /* Context handler macros */ |
---|
510 | |
---|
511 | /* |
---|
512 | * Initialize the context to a state suitable for starting a |
---|
513 | * task after a context restore operation. Generally, this |
---|
514 | * involves: |
---|
515 | * |
---|
516 | * - setting a starting address |
---|
517 | * - preparing the stack |
---|
518 | * - preparing the stack and frame pointers |
---|
519 | * - setting the proper interrupt level in the context |
---|
520 | * - initializing the floating point context |
---|
521 | * |
---|
522 | * This routine generally does not set any unnecessary register |
---|
523 | * in the context. The state of the "general data" registers is |
---|
524 | * undefined at task start time. |
---|
525 | */ |
---|
526 | |
---|
527 | void _CPU_Context_Initialize( |
---|
528 | Context_Control *the_context, |
---|
529 | uint32_t *stack_base, |
---|
530 | uint32_t size, |
---|
531 | uint32_t new_level, |
---|
532 | void *entry_point, |
---|
533 | boolean is_fp |
---|
534 | ); |
---|
535 | |
---|
536 | /* |
---|
537 | * This routine is responsible for somehow restarting the currently |
---|
538 | * executing task. If you are lucky, then all that is necessary |
---|
539 | * is restoring the context. Otherwise, there will need to be |
---|
540 | * a special assembly routine which does something special in this |
---|
541 | * case. Context_Restore should work most of the time. It will |
---|
542 | * not work if restarting self conflicts with the stack frame |
---|
543 | * assumptions of restoring a context. |
---|
544 | */ |
---|
545 | |
---|
546 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
547 | _CPU_Context_restore( (_the_context) ); |
---|
548 | |
---|
549 | /* |
---|
550 | * The purpose of this macro is to allow the initial pointer into |
---|
551 | * a floating point context area (used to save the floating point |
---|
552 | * context) to be at an arbitrary place in the floating point |
---|
553 | * context area. |
---|
554 | * |
---|
555 | * This is necessary because some FP units are designed to have |
---|
556 | * their context saved as a stack which grows into lower addresses. |
---|
557 | * Other FP units can be saved by simply moving registers into offsets |
---|
558 | * from the base of the context area. Finally some FP units provide |
---|
559 | * a "dump context" instruction which could fill in from high to low |
---|
560 | * or low to high based on the whim of the CPU designers. |
---|
561 | */ |
---|
562 | |
---|
563 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
564 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
565 | |
---|
566 | /* |
---|
567 | * This routine initializes the FP context area passed to it to. |
---|
568 | * There are a few standard ways in which to initialize the |
---|
569 | * floating point context. The code included for this macro assumes |
---|
570 | * that this is a CPU in which a "initial" FP context was saved into |
---|
571 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
572 | * context passed to it. |
---|
573 | * |
---|
574 | * Other models include (1) not doing anything, and (2) putting |
---|
575 | * a "null FP status word" in the correct place in the FP context. |
---|
576 | */ |
---|
577 | |
---|
578 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
579 | { \ |
---|
580 | (*(_destination))->fpscr = PPC_INIT_FPSCR; \ |
---|
581 | } |
---|
582 | |
---|
583 | /* end of Context handler macros */ |
---|
584 | #endif /* ASM */ |
---|
585 | |
---|
586 | #ifndef ASM |
---|
587 | /* Bitfield handler macros */ |
---|
588 | |
---|
589 | /* |
---|
590 | * This routine sets _output to the bit number of the first bit |
---|
591 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
592 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
593 | * least significant bits will be used. |
---|
594 | * |
---|
595 | * There are a number of variables in using a "find first bit" type |
---|
596 | * instruction. |
---|
597 | * |
---|
598 | * (1) What happens when run on a value of zero? |
---|
599 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
600 | * (3) The numbering may be zero or one based. |
---|
601 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
602 | * |
---|
603 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
604 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
605 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
606 | * which must logically operate together. Bits in the _value are |
---|
607 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
608 | * The basic major and minor values calculated by _Priority_Major() |
---|
609 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
610 | * to properly range between the values returned by the "find first bit" |
---|
611 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
612 | * calculate the major and directly index into the minor table. |
---|
613 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
614 | * is the first bit found. |
---|
615 | * |
---|
616 | * This entire "find first bit" and mapping process depends heavily |
---|
617 | * on the manner in which a priority is broken into a major and minor |
---|
618 | * components with the major being the 4 MSB of a priority and minor |
---|
619 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
620 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
621 | * to the lowest priority. |
---|
622 | * |
---|
623 | * If your CPU does not have a "find first bit" instruction, then |
---|
624 | * there are ways to make do without it. Here are a handful of ways |
---|
625 | * to implement this in software: |
---|
626 | * |
---|
627 | * - a series of 16 bit test instructions |
---|
628 | * - a "binary search using if's" |
---|
629 | * - _number = 0 |
---|
630 | * if _value > 0x00ff |
---|
631 | * _value >>=8 |
---|
632 | * _number = 8; |
---|
633 | * |
---|
634 | * if _value > 0x0000f |
---|
635 | * _value >=8 |
---|
636 | * _number += 4 |
---|
637 | * |
---|
638 | * _number += bit_set_table[ _value ] |
---|
639 | * |
---|
640 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
641 | * bit set |
---|
642 | */ |
---|
643 | |
---|
644 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
645 | { \ |
---|
646 | asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
---|
647 | "1" ((_value))); \ |
---|
648 | } |
---|
649 | |
---|
650 | /* end of Bitfield handler macros */ |
---|
651 | |
---|
652 | /* |
---|
653 | * This routine builds the mask which corresponds to the bit fields |
---|
654 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
655 | * for that routine. |
---|
656 | */ |
---|
657 | |
---|
658 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
659 | ( 0x80000000 >> (_bit_number) ) |
---|
660 | |
---|
661 | /* |
---|
662 | * This routine translates the bit numbers returned by |
---|
663 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
664 | * a major or minor component of a priority. See the discussion |
---|
665 | * for that routine. |
---|
666 | */ |
---|
667 | |
---|
668 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
669 | (_priority) |
---|
670 | |
---|
671 | /* end of Priority handler macros */ |
---|
672 | #endif /* ASM */ |
---|
673 | |
---|
674 | /* functions */ |
---|
675 | |
---|
676 | #ifndef ASM |
---|
677 | |
---|
678 | /* |
---|
679 | * _CPU_Initialize |
---|
680 | * |
---|
681 | * This routine performs CPU dependent initialization. |
---|
682 | */ |
---|
683 | |
---|
684 | void _CPU_Initialize( |
---|
685 | void (*thread_dispatch) |
---|
686 | ); |
---|
687 | |
---|
688 | /* |
---|
689 | * _CPU_ISR_install_vector |
---|
690 | * |
---|
691 | * This routine installs an interrupt vector. |
---|
692 | */ |
---|
693 | |
---|
694 | void _CPU_ISR_install_vector( |
---|
695 | uint32_t vector, |
---|
696 | proc_ptr new_handler, |
---|
697 | proc_ptr *old_handler |
---|
698 | ); |
---|
699 | |
---|
700 | /* |
---|
701 | * _CPU_Install_interrupt_stack |
---|
702 | * |
---|
703 | * This routine installs the hardware interrupt stack pointer. |
---|
704 | * |
---|
705 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
706 | * is TRUE. |
---|
707 | */ |
---|
708 | |
---|
709 | void _CPU_Install_interrupt_stack( void ); |
---|
710 | |
---|
711 | /* |
---|
712 | * _CPU_Context_switch |
---|
713 | * |
---|
714 | * This routine switches from the run context to the heir context. |
---|
715 | */ |
---|
716 | |
---|
717 | void _CPU_Context_switch( |
---|
718 | Context_Control *run, |
---|
719 | Context_Control *heir |
---|
720 | ); |
---|
721 | |
---|
722 | /* |
---|
723 | * _CPU_Context_restore |
---|
724 | * |
---|
725 | * This routine is generallu used only to restart self in an |
---|
726 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
727 | * |
---|
728 | * NOTE: May be unnecessary to reload some registers. |
---|
729 | */ |
---|
730 | |
---|
731 | void _CPU_Context_restore( |
---|
732 | Context_Control *new_context |
---|
733 | ); |
---|
734 | |
---|
735 | /* |
---|
736 | * _CPU_Context_save_fp |
---|
737 | * |
---|
738 | * This routine saves the floating point context passed to it. |
---|
739 | */ |
---|
740 | |
---|
741 | void _CPU_Context_save_fp( |
---|
742 | Context_Control_fp **fp_context_ptr |
---|
743 | ); |
---|
744 | |
---|
745 | /* |
---|
746 | * _CPU_Context_restore_fp |
---|
747 | * |
---|
748 | * This routine restores the floating point context passed to it. |
---|
749 | */ |
---|
750 | |
---|
751 | void _CPU_Context_restore_fp( |
---|
752 | Context_Control_fp **fp_context_ptr |
---|
753 | ); |
---|
754 | |
---|
755 | void _CPU_Fatal_error( |
---|
756 | uint32_t _error |
---|
757 | ); |
---|
758 | |
---|
759 | #endif /* ASM */ |
---|
760 | |
---|
761 | #endif /* _RTEMS_SCORE_CPU_H */ |
---|