source: rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h @ 03b7789

4.11
Last change on this file since 03b7789 was 03b7789, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 26, 2014 at 1:09:10 PM

score: Statically initialize _ISR_Vector_table

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1/**
2 * @file
3 *
4 * @brief PowerPC CPU Department Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  COPYRIGHT (c) 1995 i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
25 *
26 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
27 *
28 *  Copyright (c) 2010-2013 embedded brains GmbH.
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.rtems.org/license/LICENSE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#include <rtems/score/types.h>
39#include <rtems/score/powerpc.h>
40#include <rtems/powerpc/registers.h>
41
42#ifndef ASM
43  #include <string.h> /* for memset() */
44#endif
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/* conditional compilation parameters */
51
52/*
53 *  Should the calls to _Thread_Enable_dispatch be inlined?
54 *
55 *  If TRUE, then they are inlined.
56 *  If FALSE, then a subroutine call is made.
57 *
58 *  Basically this is an example of the classic trade-off of size
59 *  versus speed.  Inlining the call (TRUE) typically increases the
60 *  size of RTEMS while speeding up the enabling of dispatching.
61 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
62 *  only be 0 or 1 unless you are in an interrupt handler and that
63 *  interrupt handler invokes the executive.]  When not inlined
64 *  something calls _Thread_Enable_dispatch which in turns calls
65 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
66 *  one subroutine call is avoided entirely.]
67 */
68
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/*
72 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
73 *  be unrolled one time?  In unrolled each iteration of the loop examines
74 *  two "nodes" on the chain being searched.  Otherwise, only one node
75 *  is examined per iteration.
76 *
77 *  If TRUE, then the loops are unrolled.
78 *  If FALSE, then the loops are not unrolled.
79 *
80 *  The primary factor in making this decision is the cost of disabling
81 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 *  body of the loop.  On some CPUs, the flash is more expensive than
83 *  one iteration of the loop body.  In this case, it might be desirable
84 *  to unroll the loop.  It is important to note that on some CPUs, this
85 *  code is the longest interrupt disable period in RTEMS.  So it is
86 *  necessary to strike a balance when setting this parameter.
87 */
88
89#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
90
91/*
92 *  Does this port provide a CPU dependent IDLE task implementation?
93 *
94 *  If TRUE, then the routine _CPU_Thread_Idle_body
95 *  must be provided and is the default IDLE thread body instead of
96 *  _CPU_Thread_Idle_body.
97 *
98 *  If FALSE, then use the generic IDLE thread body if the BSP does
99 *  not provide one.
100 *
101 *  This is intended to allow for supporting processors which have
102 *  a low power or idle mode.  When the IDLE thread is executed, then
103 *  the CPU can be powered down.
104 *
105 *  The order of precedence for selecting the IDLE thread body is:
106 *
107 *    1.  BSP provided
108 *    2.  CPU dependent (if provided)
109 *    3.  generic (if no BSP and no CPU dependent)
110 */
111
112#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
113
114/*
115 *  Does the stack grow up (toward higher addresses) or down
116 *  (toward lower addresses)?
117 *
118 *  If TRUE, then the grows upward.
119 *  If FALSE, then the grows toward smaller addresses.
120 */
121
122#define CPU_STACK_GROWS_UP               FALSE
123
124/*
125 *  The following is the variable attribute used to force alignment
126 *  of critical RTEMS structures.  On some processors it may make
127 *  sense to have these aligned on tighter boundaries than
128 *  the minimum requirements of the compiler in order to have as
129 *  much of the critical data area as possible in a cache line.
130 *
131 *  The placement of this macro in the declaration of the variables
132 *  is based on the syntactically requirements of the GNU C
133 *  "__attribute__" extension.  For example with GNU C, use
134 *  the following to force a structures to a 32 byte boundary.
135 *
136 *      __attribute__ ((aligned (32)))
137 *
138 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
139 *         To benefit from using this, the data must be heavily
140 *         used so it will stay in the cache and used frequently enough
141 *         in the executive to justify turning this on.
142 */
143
144#define CPU_STRUCTURE_ALIGNMENT \
145  __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT)))
146
147#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
148
149/*
150 *  Define what is required to specify how the network to host conversion
151 *  routines are handled.
152 */
153
154#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN)
155#define CPU_BIG_ENDIAN                           TRUE
156#define CPU_LITTLE_ENDIAN                        FALSE
157#else
158#define CPU_BIG_ENDIAN                           FALSE
159#define CPU_LITTLE_ENDIAN                        TRUE
160#endif
161
162/*
163 *  Does the CPU have hardware floating point?
164 *
165 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
166 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
167 *
168 *  If there is a FP coprocessor such as the i387 or mc68881, then
169 *  the answer is TRUE.
170 *
171 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
172 *  It indicates whether or not this CPU model has FP support.  For
173 *  example, it would be possible to have an i386_nofp CPU model
174 *  which set this to false to indicate that you have an i386 without
175 *  an i387 and wish to leave floating point support out of RTEMS.
176 */
177
178#if ( PPC_HAS_FPU == 1 )
179#define CPU_HARDWARE_FP     TRUE
180#define CPU_SOFTWARE_FP     FALSE
181#else
182#define CPU_HARDWARE_FP     FALSE
183#define CPU_SOFTWARE_FP     FALSE
184#endif
185
186/*
187 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
188 *
189 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
190 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
191 *
192 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
193 *
194 *  PowerPC Note: It appears the GCC can implicitly generate FPU
195 *  and Altivec instructions when you least expect them.  So make
196 *  all tasks floating point.
197 */
198
199#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
200
201/*
202 *  Should the IDLE task have a floating point context?
203 *
204 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
205 *  and it has a floating point context which is switched in and out.
206 *  If FALSE, then the IDLE task does not have a floating point context.
207 *
208 *  Setting this to TRUE negatively impacts the time required to preempt
209 *  the IDLE task from an interrupt because the floating point context
210 *  must be saved as part of the preemption.
211 */
212
213#define CPU_IDLE_TASK_IS_FP      FALSE
214
215#define CPU_PER_CPU_CONTROL_SIZE 0
216
217/*
218 *  Processor defined structures required for cpukit/score.
219 */
220
221/*
222 * Contexts
223 *
224 *  Generally there are 2 types of context to save.
225 *     1. Interrupt registers to save
226 *     2. Task level registers to save
227 *
228 *  This means we have the following 3 context items:
229 *     1. task level context stuff::  Context_Control
230 *     2. floating point task stuff:: Context_Control_fp
231 *     3. special interrupt level context :: Context_Control_interrupt
232 *
233 *  On some processors, it is cost-effective to save only the callee
234 *  preserved registers during a task context switch.  This means
235 *  that the ISR code needs to save those registers which do not
236 *  persist across function calls.  It is not mandatory to make this
237 *  distinctions between the caller/callee saves registers for the
238 *  purpose of minimizing context saved during task switch and on interrupts.
239 *  If the cost of saving extra registers is minimal, simplicity is the
240 *  choice.  Save the same context on interrupt entry as for tasks in
241 *  this case.
242 *
243 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
244 *  care should be used in designing the context area.
245 *
246 *  On some CPUs with hardware floating point support, the Context_Control_fp
247 *  structure will not be used or it simply consist of an array of a
248 *  fixed number of bytes.   This is done when the floating point context
249 *  is dumped by a "FP save context" type instruction and the format
250 *  is not really defined by the CPU.  In this case, there is no need
251 *  to figure out the exact format -- only the size.  Of course, although
252 *  this is enough information for RTEMS, it is probably not enough for
253 *  a debugger such as gdb.  But that is another problem.
254 */
255
256#ifndef __SPE__
257  #define PPC_GPR_TYPE uint32_t
258  #define PPC_GPR_SIZE 4
259  #define PPC_GPR_LOAD lwz
260  #define PPC_GPR_STORE stw
261#else
262  #define PPC_GPR_TYPE uint64_t
263  #define PPC_GPR_SIZE 8
264  #define PPC_GPR_LOAD evldd
265  #define PPC_GPR_STORE evstdd
266#endif
267
268#define PPC_DEFAULT_CACHE_LINE_SIZE 32
269
270#ifndef ASM
271
272typedef struct {
273  /* There is no CPU specific per-CPU state */
274} CPU_Per_CPU_control;
275
276/*
277 * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according
278 * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 -
279 * Linux and Embedded")
280 */
281typedef struct {
282  uint32_t gpr1;
283  uint32_t msr;
284  uint32_t lr;
285  uint32_t cr;
286  PPC_GPR_TYPE gpr14;
287  PPC_GPR_TYPE gpr15;
288  PPC_GPR_TYPE gpr16;
289  PPC_GPR_TYPE gpr17;
290  PPC_GPR_TYPE gpr18;
291  PPC_GPR_TYPE gpr19;
292  PPC_GPR_TYPE gpr20;
293  PPC_GPR_TYPE gpr21;
294  PPC_GPR_TYPE gpr22;
295  PPC_GPR_TYPE gpr23;
296  PPC_GPR_TYPE gpr24;
297  PPC_GPR_TYPE gpr25;
298  PPC_GPR_TYPE gpr26;
299  PPC_GPR_TYPE gpr27;
300  PPC_GPR_TYPE gpr28;
301  PPC_GPR_TYPE gpr29;
302  PPC_GPR_TYPE gpr30;
303  PPC_GPR_TYPE gpr31;
304  uint32_t gpr2;
305  #ifdef __ALTIVEC__
306    /*
307     * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
308     * and padding to ensure cache-alignment.  Unfortunately, we can't verify
309     * the cache line size here in the cpukit but altivec support code will
310     * produce an error if this is ever different from 32 bytes.
311     *
312     * Note: it is the BSP/CPU-support's responsibility to save/restore
313     *       volatile vregs across interrupts and exceptions.
314     */
315    uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
316  #endif
317} ppc_context;
318
319typedef struct {
320  uint8_t context [
321    PPC_DEFAULT_CACHE_LINE_SIZE
322      + sizeof(ppc_context)
323      + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
324        ? 0
325          : PPC_DEFAULT_CACHE_LINE_SIZE
326            - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
327  ];
328} Context_Control;
329
330static inline ppc_context *ppc_get_context( Context_Control *context )
331{
332  uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
333  uintptr_t mask = clsz - 1;
334  uintptr_t addr = (uintptr_t) context;
335
336  return (ppc_context *) ((addr & ~mask) + clsz);
337}
338
339#define _CPU_Context_Get_SP( _context ) \
340  ppc_get_context(_context)->gpr1
341#endif /* ASM */
342
343#define PPC_CONTEXT_OFFSET_GPR1 32
344#define PPC_CONTEXT_OFFSET_MSR 36
345#define PPC_CONTEXT_OFFSET_LR 40
346#define PPC_CONTEXT_OFFSET_CR 44
347
348#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
349  (((gpr) - 14) * PPC_GPR_SIZE + 48)
350
351#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
352#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
353#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
354#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
355#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
356#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
357#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
358#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
359#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
360#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
361#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
362#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
363#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
364#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
365#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
366#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
367#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
368#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
369#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 )
370
371#ifndef ASM
372typedef struct {
373    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
374     * procedure calls.  However, this would mean that the interrupt
375     * frame had to hold f0-f13, and the fpscr.  And as the majority
376     * of tasks will not have an FP context, we will save the whole
377     * context here.
378     */
379#if (PPC_HAS_DOUBLE == 1)
380    double      f[32];
381    uint64_t    fpscr;
382#else
383    float       f[32];
384    uint32_t    fpscr;
385#endif
386} Context_Control_fp;
387
388typedef struct CPU_Interrupt_frame {
389    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
390    uint32_t   calleeLr;        /* link register used by callees: SVR4/EABI */
391
392    /* This is what is left out of the primary contexts */
393    uint32_t   gpr0;
394    uint32_t   gpr2;            /* play safe */
395    uint32_t   gpr3;
396    uint32_t   gpr4;
397    uint32_t   gpr5;
398    uint32_t   gpr6;
399    uint32_t   gpr7;
400    uint32_t   gpr8;
401    uint32_t   gpr9;
402    uint32_t   gpr10;
403    uint32_t   gpr11;
404    uint32_t   gpr12;
405    uint32_t   gpr13;   /* Play safe */
406    uint32_t   gpr28;   /* For internal use by the IRQ handler */
407    uint32_t   gpr29;   /* For internal use by the IRQ handler */
408    uint32_t   gpr30;   /* For internal use by the IRQ handler */
409    uint32_t   gpr31;   /* For internal use by the IRQ handler */
410    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
411    uint32_t   ctr;
412    uint32_t   xer;
413    uint32_t   lr;
414    uint32_t   pc;
415    uint32_t   msr;
416    uint32_t   pad[3];
417} CPU_Interrupt_frame;
418
419#endif /* ASM */
420
421/*
422 *  Does the CPU follow the simple vectored interrupt model?
423 *
424 *  If TRUE, then RTEMS allocates the vector table it internally manages.
425 *  If FALSE, then the BSP is assumed to allocate and manage the vector
426 *  table
427 *
428 *  PowerPC Specific Information:
429 *
430 *  The PowerPC and x86 were the first to use the PIC interrupt model.
431 *  They do not use the simple vectored interrupt model.
432 */
433#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
434
435/*
436 *  Does RTEMS manage a dedicated interrupt stack in software?
437 *
438 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
439 *  If FALSE, nothing is done.
440 *
441 *  If the CPU supports a dedicated interrupt stack in hardware,
442 *  then it is generally the responsibility of the BSP to allocate it
443 *  and set it up.
444 *
445 *  If the CPU does not support a dedicated interrupt stack, then
446 *  the porter has two options: (1) execute interrupts on the
447 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
448 *  interrupt stack.
449 *
450 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
451 *
452 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
453 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
454 *  possible that both are FALSE for a particular CPU.  Although it
455 *  is unclear what that would imply about the interrupt processing
456 *  procedure on that CPU.
457 */
458
459#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
460
461/*
462 *  Does this CPU have hardware support for a dedicated interrupt stack?
463 *
464 *  If TRUE, then it must be installed during initialization.
465 *  If FALSE, then no installation is performed.
466 *
467 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
468 *
469 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
470 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
471 *  possible that both are FALSE for a particular CPU.  Although it
472 *  is unclear what that would imply about the interrupt processing
473 *  procedure on that CPU.
474 */
475
476#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
477
478/*
479 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
480 *
481 *  If TRUE, then the memory is allocated during initialization.
482 *  If FALSE, then the memory is allocated during initialization.
483 *
484 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
485 */
486
487#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
488
489/*
490 *  Does the RTEMS invoke the user's ISR with the vector number and
491 *  a pointer to the saved interrupt frame (1) or just the vector
492 *  number (0)?
493 */
494
495#define CPU_ISR_PASSES_FRAME_POINTER 0
496
497/*
498 *  Should the saving of the floating point registers be deferred
499 *  until a context switch is made to another different floating point
500 *  task?
501 *
502 *  If TRUE, then the floating point context will not be stored until
503 *  necessary.  It will remain in the floating point registers and not
504 *  disturned until another floating point task is switched to.
505 *
506 *  If FALSE, then the floating point context is saved when a floating
507 *  point task is switched out and restored when the next floating point
508 *  task is restored.  The state of the floating point registers between
509 *  those two operations is not specified.
510 *
511 *  If the floating point context does NOT have to be saved as part of
512 *  interrupt dispatching, then it should be safe to set this to TRUE.
513 *
514 *  Setting this flag to TRUE results in using a different algorithm
515 *  for deciding when to save and restore the floating point context.
516 *  The deferred FP switch algorithm minimizes the number of times
517 *  the FP context is saved and restored.  The FP context is not saved
518 *  until a context switch is made to another, different FP task.
519 *  Thus in a system with only one FP task, the FP context will never
520 *  be saved or restored.
521 *
522 *  Note, however that compilers may use floating point registers/
523 *  instructions for optimization or they may save/restore FP registers
524 *  on the stack. You must not use deferred switching in these cases
525 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
526 *  exception.
527 */
528/*
529 *  ACB Note:  This could make debugging tricky..
530 */
531
532/* conservative setting (FALSE); probably doesn't affect performance too much */
533#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
534
535/*
536 *  Processor defined structures required for cpukit/score.
537 */
538
539#ifndef ASM
540
541/*
542 *  This variable is optional.  It is used on CPUs on which it is difficult
543 *  to generate an "uninitialized" FP context.  It is filled in by
544 *  _CPU_Initialize and copied into the task's FP context area during
545 *  _CPU_Context_Initialize.
546 */
547
548/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
549
550#endif /* ndef ASM */
551
552/*
553 *  This defines the number of levels and the mask used to pick those
554 *  bits out of a thread mode.
555 */
556
557#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
558#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
559
560/*
561 *  Nothing prevents the porter from declaring more CPU specific variables.
562 */
563
564#ifndef ASM
565
566SCORE_EXTERN struct {
567  uint32_t      *Disable_level;
568  void          *Stack;
569  volatile bool *Switch_necessary;
570  bool          *Signal;
571
572} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
573
574#endif /* ndef ASM */
575
576/*
577 *  The size of the floating point context area.  On some CPUs this
578 *  will not be a "sizeof" because the format of the floating point
579 *  area is not defined -- only the size is.  This is usually on
580 *  CPUs with a "floating point save context" instruction.
581 */
582
583#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
584
585/*
586 * (Optional) # of bytes for libmisc/stackchk to check
587 * If not specifed, then it defaults to something reasonable
588 * for most architectures.
589 */
590
591#define CPU_STACK_CHECK_SIZE    (128)
592
593/*
594 *  Amount of extra stack (above minimum stack size) required by
595 *  MPCI receive server thread.  Remember that in a multiprocessor
596 *  system this thread must exist and be able to process all directives.
597 */
598
599#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
600
601/*
602 *  This is defined if the port has a special way to report the ISR nesting
603 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
604 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
605 *  being maintained (e.g. watchdog queues).
606 */
607
608#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
609
610/*
611 *  ISR handler macros
612 */
613
614/*
615 *  Disable all interrupts for an RTEMS critical section.  The previous
616 *  level is returned in _isr_cookie.
617 */
618
619#ifndef ASM
620
621static inline uint32_t   _CPU_ISR_Get_level( void )
622{
623  register unsigned int msr;
624  _CPU_MSR_GET(msr);
625  if (msr & MSR_EE) return 0;
626  else  return 1;
627}
628
629static inline void _CPU_ISR_Set_level( uint32_t   level )
630{
631  register unsigned int msr;
632  _CPU_MSR_GET(msr);
633  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
634    msr |= ppc_interrupt_get_disable_mask();
635  }
636  else {
637    msr &= ~ppc_interrupt_get_disable_mask();
638  }
639  _CPU_MSR_SET(msr);
640}
641
642void BSP_panic(char *);
643
644/* Fatal Error manager macros */
645
646/*
647 *  This routine copies _error into a known place -- typically a stack
648 *  location or a register, optionally disables interrupts, and
649 *  halts/stops the CPU.
650 */
651
652void _BSP_Fatal_error(unsigned int);
653
654#endif /* ASM */
655
656#define _CPU_Fatal_halt( _error ) \
657  _BSP_Fatal_error(_error)
658
659/* end of Fatal Error manager macros */
660
661/*
662 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
663 * Now SPRG0 is devoted to the interrupt disable mask.
664 */
665
666#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
667
668/*
669 *  Should be large enough to run all RTEMS tests.  This ensures
670 *  that a "reasonable" small application should not have any problems.
671 */
672
673#define CPU_STACK_MINIMUM_SIZE          (1024*8)
674
675#define CPU_SIZEOF_POINTER 4
676
677/*
678 *  CPU's worst alignment requirement for data types on a byte boundary.  This
679 *  alignment does not take into account the requirements for the stack.
680 */
681
682#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
683
684/*
685 *  This number corresponds to the byte alignment requirement for the
686 *  heap handler.  This alignment requirement may be stricter than that
687 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
688 *  common for the heap to follow the same alignment requirement as
689 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
690 *  then this should be set to CPU_ALIGNMENT.
691 *
692 *  NOTE:  This does not have to be a power of 2.  It does have to
693 *         be greater or equal to than CPU_ALIGNMENT.
694 */
695
696#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
697
698/*
699 *  This number corresponds to the byte alignment requirement for memory
700 *  buffers allocated by the partition manager.  This alignment requirement
701 *  may be stricter than that for the data types alignment specified by
702 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
703 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
704 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
705 *
706 *  NOTE:  This does not have to be a power of 2.  It does have to
707 *         be greater or equal to than CPU_ALIGNMENT.
708 */
709
710#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
711
712/*
713 *  This number corresponds to the byte alignment requirement for the
714 *  stack.  This alignment requirement may be stricter than that for the
715 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
716 *  is strict enough for the stack, then this should be set to 0.
717 *
718 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
719 */
720
721#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
722
723#ifndef ASM
724/*  The following routine swaps the endian format of an unsigned int.
725 *  It must be static because it is referenced indirectly.
726 *
727 *  This version will work on any processor, but if there is a better
728 *  way for your CPU PLEASE use it.  The most common way to do this is to:
729 *
730 *     swap least significant two bytes with 16-bit rotate
731 *     swap upper and lower 16-bits
732 *     swap most significant two bytes with 16-bit rotate
733 *
734 *  Some CPUs have special instructions which swap a 32-bit quantity in
735 *  a single instruction (e.g. i486).  It is probably best to avoid
736 *  an "endian swapping control bit" in the CPU.  One good reason is
737 *  that interrupts would probably have to be disabled to ensure that
738 *  an interrupt does not try to access the same "chunk" with the wrong
739 *  endian.  Another good reason is that on some CPUs, the endian bit
740 *  endianness for ALL fetches -- both code and data -- so the code
741 *  will be fetched incorrectly.
742 */
743
744static inline uint32_t CPU_swap_u32(
745  uint32_t value
746)
747{
748  uint32_t   swapped;
749
750  __asm__ volatile("rlwimi %0,%1,8,24,31;"
751               "rlwimi %0,%1,24,16,23;"
752               "rlwimi %0,%1,8,8,15;"
753               "rlwimi %0,%1,24,0,7;" :
754               "=&r" ((swapped)) : "r" ((value)));
755
756  return( swapped );
757}
758
759#define CPU_swap_u16( value ) \
760  (((value&0xff) << 8) | ((value >> 8)&0xff))
761
762typedef uint32_t CPU_Counter_ticks;
763
764static inline CPU_Counter_ticks _CPU_Counter_read( void )
765{
766  CPU_Counter_ticks value;
767
768#ifdef ppc8540
769  /* Book E has no mftb */
770  __asm__ volatile( "mfspr %0, 268" : "=r" (value) );
771#else
772  __asm__ volatile( "mftb %0" : "=r" (value) );
773#endif
774
775  return value;
776}
777
778static inline CPU_Counter_ticks _CPU_Counter_difference(
779  CPU_Counter_ticks second,
780  CPU_Counter_ticks first
781)
782{
783  return second - first;
784}
785
786#endif /* ASM */
787
788
789#ifndef ASM
790/* Context handler macros */
791
792/*
793 *  Initialize the context to a state suitable for starting a
794 *  task after a context restore operation.  Generally, this
795 *  involves:
796 *
797 *     - setting a starting address
798 *     - preparing the stack
799 *     - preparing the stack and frame pointers
800 *     - setting the proper interrupt level in the context
801 *     - initializing the floating point context
802 *
803 *  This routine generally does not set any unnecessary register
804 *  in the context.  The state of the "general data" registers is
805 *  undefined at task start time.
806 */
807
808void _CPU_Context_Initialize(
809  Context_Control  *the_context,
810  uint32_t         *stack_base,
811  uint32_t          size,
812  uint32_t          new_level,
813  void             *entry_point,
814  bool              is_fp,
815  void             *tls_area
816);
817
818/*
819 *  This routine is responsible for somehow restarting the currently
820 *  executing task.  If you are lucky, then all that is necessary
821 *  is restoring the context.  Otherwise, there will need to be
822 *  a special assembly routine which does something special in this
823 *  case.  Context_Restore should work most of the time.  It will
824 *  not work if restarting self conflicts with the stack frame
825 *  assumptions of restoring a context.
826 */
827
828#define _CPU_Context_Restart_self( _the_context ) \
829   _CPU_Context_restore( (_the_context) );
830
831/*
832 *  The purpose of this macro is to allow the initial pointer into
833 *  a floating point context area (used to save the floating point
834 *  context) to be at an arbitrary place in the floating point
835 *  context area.
836 *
837 *  This is necessary because some FP units are designed to have
838 *  their context saved as a stack which grows into lower addresses.
839 *  Other FP units can be saved by simply moving registers into offsets
840 *  from the base of the context area.  Finally some FP units provide
841 *  a "dump context" instruction which could fill in from high to low
842 *  or low to high based on the whim of the CPU designers.
843 */
844
845#define _CPU_Context_Fp_start( _base, _offset ) \
846   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
847
848/*
849 *  This routine initializes the FP context area passed to it to.
850 *  There are a few standard ways in which to initialize the
851 *  floating point context.  The code included for this macro assumes
852 *  that this is a CPU in which a "initial" FP context was saved into
853 *  _CPU_Null_fp_context and it simply copies it to the destination
854 *  context passed to it.
855 *
856 *  Other models include (1) not doing anything, and (2) putting
857 *  a "null FP status word" in the correct place in the FP context.
858 */
859
860#define _CPU_Context_Initialize_fp( _destination ) \
861  memset( *(_destination), 0, sizeof( **(_destination) ) )
862
863/* end of Context handler macros */
864#endif /* ASM */
865
866#ifndef ASM
867/* Bitfield handler macros */
868
869/*
870 *  This routine sets _output to the bit number of the first bit
871 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
872 *  This type may be either 16 or 32 bits wide although only the 16
873 *  least significant bits will be used.
874 *
875 *  There are a number of variables in using a "find first bit" type
876 *  instruction.
877 *
878 *    (1) What happens when run on a value of zero?
879 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
880 *    (3) The numbering may be zero or one based.
881 *    (4) The "find first bit" instruction may search from MSB or LSB.
882 *
883 *  RTEMS guarantees that (1) will never happen so it is not a concern.
884 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
885 *  _CPU_Priority_Bits_index().  These three form a set of routines
886 *  which must logically operate together.  Bits in the _value are
887 *  set and cleared based on masks built by _CPU_Priority_mask().
888 *  The basic major and minor values calculated by _Priority_Major()
889 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
890 *  to properly range between the values returned by the "find first bit"
891 *  instruction.  This makes it possible for _Priority_Get_highest() to
892 *  calculate the major and directly index into the minor table.
893 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
894 *  is the first bit found.
895 *
896 *  This entire "find first bit" and mapping process depends heavily
897 *  on the manner in which a priority is broken into a major and minor
898 *  components with the major being the 4 MSB of a priority and minor
899 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
900 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
901 *  to the lowest priority.
902 *
903 *  If your CPU does not have a "find first bit" instruction, then
904 *  there are ways to make do without it.  Here are a handful of ways
905 *  to implement this in software:
906 *
907 *    - a series of 16 bit test instructions
908 *    - a "binary search using if's"
909 *    - _number = 0
910 *      if _value > 0x00ff
911 *        _value >>=8
912 *        _number = 8;
913 *
914 *      if _value > 0x0000f
915 *        _value >=8
916 *        _number += 4
917 *
918 *      _number += bit_set_table[ _value ]
919 *
920 *    where bit_set_table[ 16 ] has values which indicate the first
921 *      bit set
922 */
923
924#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
925  { \
926    __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
927                  "1" ((_value))); \
928  }
929
930/* end of Bitfield handler macros */
931
932/*
933 *  This routine builds the mask which corresponds to the bit fields
934 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
935 *  for that routine.
936 */
937
938#define _CPU_Priority_Mask( _bit_number ) \
939  ( 0x80000000 >> (_bit_number) )
940
941/*
942 *  This routine translates the bit numbers returned by
943 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
944 *  a major or minor component of a priority.  See the discussion
945 *  for that routine.
946 */
947
948#define _CPU_Priority_bits_index( _priority ) \
949  (_priority)
950
951/* end of Priority handler macros */
952#endif /* ASM */
953
954/* functions */
955
956#ifndef ASM
957
958/*
959 *  _CPU_Initialize
960 *
961 *  This routine performs CPU dependent initialization.
962 */
963
964void _CPU_Initialize(void);
965
966/*
967 *  _CPU_ISR_install_vector
968 *
969 *  This routine installs an interrupt vector.
970 */
971
972void _CPU_ISR_install_vector(
973  uint32_t    vector,
974  proc_ptr    new_handler,
975  proc_ptr   *old_handler
976);
977
978/*
979 *  _CPU_Context_switch
980 *
981 *  This routine switches from the run context to the heir context.
982 */
983
984void _CPU_Context_switch(
985  Context_Control  *run,
986  Context_Control  *heir
987);
988
989/*
990 *  _CPU_Context_restore
991 *
992 *  This routine is generallu used only to restart self in an
993 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
994 *
995 *  NOTE: May be unnecessary to reload some registers.
996 */
997
998void _CPU_Context_restore(
999  Context_Control *new_context
1000) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1001
1002/*
1003 *  _CPU_Context_save_fp
1004 *
1005 *  This routine saves the floating point context passed to it.
1006 */
1007
1008void _CPU_Context_save_fp(
1009  Context_Control_fp **fp_context_ptr
1010);
1011
1012/*
1013 *  _CPU_Context_restore_fp
1014 *
1015 *  This routine restores the floating point context passed to it.
1016 */
1017
1018void _CPU_Context_restore_fp(
1019  Context_Control_fp **fp_context_ptr
1020);
1021
1022void _CPU_Context_volatile_clobber( uintptr_t pattern );
1023
1024void _CPU_Context_validate( uintptr_t pattern );
1025
1026#ifdef RTEMS_SMP
1027  uint32_t _CPU_SMP_Initialize( void );
1028
1029  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1030
1031  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1032
1033  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1034  {
1035    uint32_t pir;
1036
1037    /* Use Book E Processor ID Register (PIR) */
1038    __asm__ volatile (
1039      "mfspr %[pir], 286"
1040      : [pir] "=&r" (pir)
1041    );
1042
1043    return pir;
1044  }
1045
1046  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1047
1048  static inline void _CPU_SMP_Processor_event_broadcast( void )
1049  {
1050    __asm__ volatile ( "" : : : "memory" );
1051  }
1052
1053  static inline void _CPU_SMP_Processor_event_receive( void )
1054  {
1055    __asm__ volatile ( "" : : : "memory" );
1056  }
1057#endif
1058
1059typedef struct {
1060  uint32_t EXC_SRR0;
1061  uint32_t EXC_SRR1;
1062  uint32_t _EXC_number;
1063  uint32_t EXC_CR;
1064  uint32_t EXC_CTR;
1065  uint32_t EXC_XER;
1066  uint32_t EXC_LR;
1067  #ifdef __SPE__
1068    uint32_t EXC_SPEFSCR;
1069    uint64_t EXC_ACC;
1070  #endif
1071  PPC_GPR_TYPE GPR0;
1072  PPC_GPR_TYPE GPR1;
1073  PPC_GPR_TYPE GPR2;
1074  PPC_GPR_TYPE GPR3;
1075  PPC_GPR_TYPE GPR4;
1076  PPC_GPR_TYPE GPR5;
1077  PPC_GPR_TYPE GPR6;
1078  PPC_GPR_TYPE GPR7;
1079  PPC_GPR_TYPE GPR8;
1080  PPC_GPR_TYPE GPR9;
1081  PPC_GPR_TYPE GPR10;
1082  PPC_GPR_TYPE GPR11;
1083  PPC_GPR_TYPE GPR12;
1084  PPC_GPR_TYPE GPR13;
1085  PPC_GPR_TYPE GPR14;
1086  PPC_GPR_TYPE GPR15;
1087  PPC_GPR_TYPE GPR16;
1088  PPC_GPR_TYPE GPR17;
1089  PPC_GPR_TYPE GPR18;
1090  PPC_GPR_TYPE GPR19;
1091  PPC_GPR_TYPE GPR20;
1092  PPC_GPR_TYPE GPR21;
1093  PPC_GPR_TYPE GPR22;
1094  PPC_GPR_TYPE GPR23;
1095  PPC_GPR_TYPE GPR24;
1096  PPC_GPR_TYPE GPR25;
1097  PPC_GPR_TYPE GPR26;
1098  PPC_GPR_TYPE GPR27;
1099  PPC_GPR_TYPE GPR28;
1100  PPC_GPR_TYPE GPR29;
1101  PPC_GPR_TYPE GPR30;
1102  PPC_GPR_TYPE GPR31;
1103} CPU_Exception_frame;
1104
1105void _BSP_Exception_frame_print( const CPU_Exception_frame *frame );
1106
1107static inline void _CPU_Exception_frame_print(
1108  const CPU_Exception_frame *frame
1109)
1110{
1111  _BSP_Exception_frame_print( frame );
1112}
1113
1114/*
1115 * _CPU_Initialize_altivec()
1116 *
1117 * Global altivec-related initialization.
1118 */
1119void
1120_CPU_Initialize_altivec(void);
1121
1122/*
1123 * _CPU_Context_switch_altivec
1124 *
1125 * This routine switches the altivec contexts passed to it.
1126 */
1127
1128void
1129_CPU_Context_switch_altivec(
1130  ppc_context *from,
1131  ppc_context *to
1132);
1133
1134/*
1135 * _CPU_Context_restore_altivec
1136 *
1137 * This routine restores the altivec context passed to it.
1138 */
1139
1140void
1141_CPU_Context_restore_altivec(
1142  ppc_context *ctxt
1143);
1144
1145/*
1146 * _CPU_Context_initialize_altivec
1147 *
1148 * This routine initializes the altivec context passed to it.
1149 */
1150
1151void
1152_CPU_Context_initialize_altivec(
1153  ppc_context *ctxt
1154);
1155
1156void _CPU_Fatal_error(
1157  uint32_t   _error
1158);
1159
1160#endif /* ASM */
1161
1162#ifdef __cplusplus
1163}
1164#endif
1165
1166#endif /* _RTEMS_SCORE_CPU_H */
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