[d5607c5a] | 1 | /** |
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| 2 | * @file rtems/score/cpu.h |
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| 3 | */ |
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| 4 | |
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[4a0d87e] | 5 | /* |
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[826fa6b1] | 6 | * COPYRIGHT (c) 1989-2012. |
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[43b4c7a] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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[af16a7d2] | 9 | * COPYRIGHT (c) 1995 i-cubed ltd. |
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| 10 | * |
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| 11 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 12 | * without any express or implied warranty: |
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| 13 | * permission to use, copy, modify, and distribute this file |
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| 14 | * for any purpose is hereby granted without fee, provided that |
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| 15 | * the above copyright notice and this notice appears in all |
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| 16 | * copies, and that the name of i-cubed limited not be used in |
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| 17 | * advertising or publicity pertaining to distribution of the |
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| 18 | * software without specific, written prior permission. |
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| 19 | * i-cubed limited makes no representations about the suitability |
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| 20 | * of this software for any purpose. |
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| 21 | * |
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| 22 | * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. |
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| 23 | * |
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| 24 | * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). |
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| 25 | * |
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[1869bb7] | 26 | * Copyright (c) 2010-2012 embedded brains GmbH. |
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[af16a7d2] | 27 | * |
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[43b4c7a] | 28 | * The license and distribution terms for this file may be |
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| 29 | * found in the file LICENSE in this distribution or at |
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| 30 | * http://www.rtems.com/license/LICENSE. |
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[4a0d87e] | 31 | */ |
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[5bb38e15] | 32 | |
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[7f70d1b7] | 33 | #ifndef _RTEMS_SCORE_CPU_H |
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| 34 | #define _RTEMS_SCORE_CPU_H |
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[4a0d87e] | 35 | |
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[af16a7d2] | 36 | #include <rtems/score/types.h> |
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| 37 | #include <rtems/score/powerpc.h> |
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| 38 | #include <rtems/powerpc/registers.h> |
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[2067679] | 39 | |
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[4a0d87e] | 40 | #ifndef ASM |
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[2067679] | 41 | #include <string.h> /* for memset() */ |
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[af16a7d2] | 42 | #endif |
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| 43 | |
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| 44 | #ifdef __cplusplus |
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| 45 | extern "C" { |
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[4a0d87e] | 46 | #endif |
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| 47 | |
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[8ecc042a] | 48 | /* conditional compilation parameters */ |
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| 49 | |
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| 50 | /* |
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| 51 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 52 | * |
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| 53 | * If TRUE, then they are inlined. |
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| 54 | * If FALSE, then a subroutine call is made. |
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| 55 | * |
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| 56 | * Basically this is an example of the classic trade-off of size |
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| 57 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 58 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 59 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 60 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 61 | * interrupt handler invokes the executive.] When not inlined |
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| 62 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 63 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 64 | * one subroutine call is avoided entirely.] |
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| 65 | */ |
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| 66 | |
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| 67 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 68 | |
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| 69 | /* |
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| 70 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 71 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 72 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 73 | * is examined per iteration. |
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| 74 | * |
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| 75 | * If TRUE, then the loops are unrolled. |
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| 76 | * If FALSE, then the loops are not unrolled. |
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| 77 | * |
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| 78 | * The primary factor in making this decision is the cost of disabling |
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| 79 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 80 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 81 | * one iteration of the loop body. In this case, it might be desirable |
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| 82 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 83 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 84 | * necessary to strike a balance when setting this parameter. |
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| 85 | */ |
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| 86 | |
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| 87 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 88 | |
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[10c66191] | 89 | /* |
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| 90 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 91 | * |
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| 92 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 93 | * must be provided and is the default IDLE thread body instead of |
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| 94 | * _CPU_Thread_Idle_body. |
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| 95 | * |
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| 96 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 97 | * not provide one. |
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| 98 | * |
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| 99 | * This is intended to allow for supporting processors which have |
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| 100 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 101 | * the CPU can be powered down. |
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| 102 | * |
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| 103 | * The order of precedence for selecting the IDLE thread body is: |
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| 104 | * |
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| 105 | * 1. BSP provided |
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| 106 | * 2. CPU dependent (if provided) |
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| 107 | * 3. generic (if no BSP and no CPU dependent) |
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| 108 | */ |
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| 109 | |
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| 110 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 111 | |
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| 112 | /* |
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| 113 | * Does the stack grow up (toward higher addresses) or down |
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| 114 | * (toward lower addresses)? |
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| 115 | * |
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| 116 | * If TRUE, then the grows upward. |
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| 117 | * If FALSE, then the grows toward smaller addresses. |
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| 118 | */ |
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| 119 | |
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| 120 | #define CPU_STACK_GROWS_UP FALSE |
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| 121 | |
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| 122 | /* |
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| 123 | * The following is the variable attribute used to force alignment |
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| 124 | * of critical RTEMS structures. On some processors it may make |
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| 125 | * sense to have these aligned on tighter boundaries than |
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| 126 | * the minimum requirements of the compiler in order to have as |
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| 127 | * much of the critical data area as possible in a cache line. |
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| 128 | * |
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| 129 | * The placement of this macro in the declaration of the variables |
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| 130 | * is based on the syntactically requirements of the GNU C |
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| 131 | * "__attribute__" extension. For example with GNU C, use |
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| 132 | * the following to force a structures to a 32 byte boundary. |
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| 133 | * |
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| 134 | * __attribute__ ((aligned (32))) |
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| 135 | * |
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| 136 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 137 | * To benefit from using this, the data must be heavily |
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| 138 | * used so it will stay in the cache and used frequently enough |
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| 139 | * in the executive to justify turning this on. |
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| 140 | */ |
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| 141 | |
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| 142 | #define CPU_STRUCTURE_ALIGNMENT \ |
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[06aab39] | 143 | __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) |
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[10c66191] | 144 | |
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[9c121991] | 145 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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| 146 | |
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[10c66191] | 147 | /* |
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| 148 | * Define what is required to specify how the network to host conversion |
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| 149 | * routines are handled. |
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| 150 | */ |
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| 151 | |
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[1f6dc36] | 152 | #if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) |
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[10c66191] | 153 | #define CPU_BIG_ENDIAN TRUE |
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| 154 | #define CPU_LITTLE_ENDIAN FALSE |
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[1f6dc36] | 155 | #else |
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| 156 | #define CPU_BIG_ENDIAN FALSE |
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| 157 | #define CPU_LITTLE_ENDIAN TRUE |
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| 158 | #endif |
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[10c66191] | 159 | |
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[56c5e091] | 160 | /* |
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| 161 | * Does the CPU have hardware floating point? |
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| 162 | * |
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| 163 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 164 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 165 | * |
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| 166 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 167 | * the answer is TRUE. |
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| 168 | * |
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| 169 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
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| 170 | * It indicates whether or not this CPU model has FP support. For |
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| 171 | * example, it would be possible to have an i386_nofp CPU model |
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| 172 | * which set this to false to indicate that you have an i386 without |
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| 173 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 174 | */ |
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| 175 | |
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| 176 | #if ( PPC_HAS_FPU == 1 ) |
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| 177 | #define CPU_HARDWARE_FP TRUE |
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| 178 | #define CPU_SOFTWARE_FP FALSE |
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| 179 | #else |
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| 180 | #define CPU_HARDWARE_FP FALSE |
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| 181 | #define CPU_SOFTWARE_FP FALSE |
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| 182 | #endif |
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| 183 | |
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| 184 | /* |
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| 185 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 186 | * |
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| 187 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 188 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 189 | * |
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| 190 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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[a19034d] | 191 | * |
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| 192 | * PowerPC Note: It appears the GCC can implicitly generate FPU |
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| 193 | * and Altivec instructions when you least expect them. So make |
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| 194 | * all tasks floating point. |
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[56c5e091] | 195 | */ |
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| 196 | |
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[a19034d] | 197 | #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
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[56c5e091] | 198 | |
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| 199 | /* |
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| 200 | * Should the IDLE task have a floating point context? |
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| 201 | * |
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| 202 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 203 | * and it has a floating point context which is switched in and out. |
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| 204 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 205 | * |
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| 206 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 207 | * the IDLE task from an interrupt because the floating point context |
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| 208 | * must be saved as part of the preemption. |
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| 209 | */ |
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| 210 | |
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| 211 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 212 | |
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[b7c7b75b] | 213 | /* |
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| 214 | * Processor defined structures required for cpukit/score. |
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| 215 | */ |
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| 216 | |
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| 217 | /* |
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| 218 | * Contexts |
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| 219 | * |
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| 220 | * Generally there are 2 types of context to save. |
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| 221 | * 1. Interrupt registers to save |
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| 222 | * 2. Task level registers to save |
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| 223 | * |
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| 224 | * This means we have the following 3 context items: |
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| 225 | * 1. task level context stuff:: Context_Control |
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| 226 | * 2. floating point task stuff:: Context_Control_fp |
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| 227 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 228 | * |
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| 229 | * On some processors, it is cost-effective to save only the callee |
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| 230 | * preserved registers during a task context switch. This means |
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| 231 | * that the ISR code needs to save those registers which do not |
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| 232 | * persist across function calls. It is not mandatory to make this |
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| 233 | * distinctions between the caller/callee saves registers for the |
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| 234 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 235 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 236 | * choice. Save the same context on interrupt entry as for tasks in |
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| 237 | * this case. |
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| 238 | * |
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| 239 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 240 | * care should be used in designing the context area. |
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| 241 | * |
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| 242 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 243 | * structure will not be used or it simply consist of an array of a |
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| 244 | * fixed number of bytes. This is done when the floating point context |
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| 245 | * is dumped by a "FP save context" type instruction and the format |
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| 246 | * is not really defined by the CPU. In this case, there is no need |
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| 247 | * to figure out the exact format -- only the size. Of course, although |
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| 248 | * this is enough information for RTEMS, it is probably not enough for |
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| 249 | * a debugger such as gdb. But that is another problem. |
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| 250 | */ |
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| 251 | |
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[c3ba11ac] | 252 | #ifndef __SPE__ |
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[1869bb7] | 253 | #define PPC_GPR_TYPE uint32_t |
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| 254 | #define PPC_GPR_SIZE 4 |
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| 255 | #define PPC_GPR_LOAD lwz |
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| 256 | #define PPC_GPR_STORE stw |
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| 257 | #else |
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| 258 | #define PPC_GPR_TYPE uint64_t |
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| 259 | #define PPC_GPR_SIZE 8 |
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| 260 | #define PPC_GPR_LOAD evldd |
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| 261 | #define PPC_GPR_STORE evstdd |
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| 262 | #endif |
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[c3ba11ac] | 263 | |
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[1869bb7] | 264 | #define PPC_DEFAULT_CACHE_LINE_SIZE 32 |
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[5be93c2] | 265 | |
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[1869bb7] | 266 | #ifndef ASM |
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[5be93c2] | 267 | |
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[1869bb7] | 268 | /* Non-volatile context according to E500ABIUG and EABI */ |
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| 269 | typedef struct { |
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| 270 | uint32_t gpr1; |
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| 271 | uint32_t msr; |
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| 272 | uint32_t lr; |
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| 273 | uint32_t cr; |
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| 274 | PPC_GPR_TYPE gpr14; |
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| 275 | PPC_GPR_TYPE gpr15; |
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| 276 | PPC_GPR_TYPE gpr16; |
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| 277 | PPC_GPR_TYPE gpr17; |
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| 278 | PPC_GPR_TYPE gpr18; |
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| 279 | PPC_GPR_TYPE gpr19; |
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| 280 | PPC_GPR_TYPE gpr20; |
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| 281 | PPC_GPR_TYPE gpr21; |
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| 282 | PPC_GPR_TYPE gpr22; |
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| 283 | PPC_GPR_TYPE gpr23; |
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| 284 | PPC_GPR_TYPE gpr24; |
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| 285 | PPC_GPR_TYPE gpr25; |
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| 286 | PPC_GPR_TYPE gpr26; |
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| 287 | PPC_GPR_TYPE gpr27; |
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| 288 | PPC_GPR_TYPE gpr28; |
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| 289 | PPC_GPR_TYPE gpr29; |
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| 290 | PPC_GPR_TYPE gpr30; |
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| 291 | PPC_GPR_TYPE gpr31; |
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| 292 | #ifdef __ALTIVEC__ |
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| 293 | /* |
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| 294 | * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave |
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| 295 | * and padding to ensure cache-alignment. Unfortunately, we can't verify |
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| 296 | * the cache line size here in the cpukit but altivec support code will |
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| 297 | * produce an error if this is ever different from 32 bytes. |
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| 298 | * |
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| 299 | * Note: it is the BSP/CPU-support's responsibility to save/restore |
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| 300 | * volatile vregs across interrupts and exceptions. |
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| 301 | */ |
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| 302 | uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; |
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| 303 | #endif |
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| 304 | } ppc_context; |
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[c3ba11ac] | 305 | |
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[1869bb7] | 306 | typedef struct { |
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| 307 | uint8_t context [ |
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| 308 | PPC_DEFAULT_CACHE_LINE_SIZE |
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| 309 | + sizeof(ppc_context) |
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| 310 | + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 |
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| 311 | ? 0 |
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| 312 | : PPC_DEFAULT_CACHE_LINE_SIZE |
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| 313 | - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) |
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| 314 | ]; |
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| 315 | } Context_Control; |
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[5be93c2] | 316 | |
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[1869bb7] | 317 | static inline ppc_context *ppc_get_context( Context_Control *context ) |
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| 318 | { |
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| 319 | uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; |
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| 320 | uintptr_t mask = clsz - 1; |
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| 321 | uintptr_t addr = (uintptr_t) context; |
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[5be93c2] | 322 | |
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[1869bb7] | 323 | return (ppc_context *) ((addr & ~mask) + clsz); |
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| 324 | } |
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[5be93c2] | 325 | |
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[1869bb7] | 326 | #define _CPU_Context_Get_SP( _context ) \ |
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| 327 | ppc_get_context(_context)->gpr1 |
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| 328 | #endif /* ASM */ |
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[c3ba11ac] | 329 | |
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[1869bb7] | 330 | #define PPC_CONTEXT_OFFSET_GPR1 32 |
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| 331 | #define PPC_CONTEXT_OFFSET_MSR 36 |
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| 332 | #define PPC_CONTEXT_OFFSET_LR 40 |
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| 333 | #define PPC_CONTEXT_OFFSET_CR 44 |
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| 334 | |
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| 335 | #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ |
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| 336 | (((gpr) - 14) * PPC_GPR_SIZE + 48) |
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| 337 | |
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| 338 | #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) |
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| 339 | #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) |
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| 340 | #define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) |
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| 341 | #define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) |
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| 342 | #define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) |
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| 343 | #define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) |
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| 344 | #define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) |
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| 345 | #define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) |
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| 346 | #define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) |
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| 347 | #define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) |
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| 348 | #define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) |
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| 349 | #define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) |
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| 350 | #define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) |
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| 351 | #define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) |
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| 352 | #define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) |
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| 353 | #define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) |
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| 354 | #define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) |
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| 355 | #define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) |
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[b7c7b75b] | 356 | |
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[c3ba11ac] | 357 | #ifndef ASM |
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[b7c7b75b] | 358 | typedef struct { |
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| 359 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
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| 360 | * procedure calls. However, this would mean that the interrupt |
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| 361 | * frame had to hold f0-f13, and the fpscr. And as the majority |
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| 362 | * of tasks will not have an FP context, we will save the whole |
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| 363 | * context here. |
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| 364 | */ |
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| 365 | #if (PPC_HAS_DOUBLE == 1) |
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| 366 | double f[32]; |
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[2067679] | 367 | uint64_t fpscr; |
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[b7c7b75b] | 368 | #else |
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| 369 | float f[32]; |
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[2067679] | 370 | uint32_t fpscr; |
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[b7c7b75b] | 371 | #endif |
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| 372 | } Context_Control_fp; |
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| 373 | |
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| 374 | typedef struct CPU_Interrupt_frame { |
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| 375 | uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ |
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| 376 | uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ |
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| 377 | |
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| 378 | /* This is what is left out of the primary contexts */ |
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| 379 | uint32_t gpr0; |
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| 380 | uint32_t gpr2; /* play safe */ |
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| 381 | uint32_t gpr3; |
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| 382 | uint32_t gpr4; |
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| 383 | uint32_t gpr5; |
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| 384 | uint32_t gpr6; |
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| 385 | uint32_t gpr7; |
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| 386 | uint32_t gpr8; |
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| 387 | uint32_t gpr9; |
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| 388 | uint32_t gpr10; |
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| 389 | uint32_t gpr11; |
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| 390 | uint32_t gpr12; |
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| 391 | uint32_t gpr13; /* Play safe */ |
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| 392 | uint32_t gpr28; /* For internal use by the IRQ handler */ |
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| 393 | uint32_t gpr29; /* For internal use by the IRQ handler */ |
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| 394 | uint32_t gpr30; /* For internal use by the IRQ handler */ |
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| 395 | uint32_t gpr31; /* For internal use by the IRQ handler */ |
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| 396 | uint32_t cr; /* Bits of this are volatile, so no-one may save */ |
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| 397 | uint32_t ctr; |
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| 398 | uint32_t xer; |
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| 399 | uint32_t lr; |
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| 400 | uint32_t pc; |
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| 401 | uint32_t msr; |
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| 402 | uint32_t pad[3]; |
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| 403 | } CPU_Interrupt_frame; |
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[2067679] | 404 | |
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[b7c7b75b] | 405 | #endif /* ASM */ |
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| 406 | |
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[9da42fb] | 407 | /* |
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| 408 | * Does the CPU follow the simple vectored interrupt model? |
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| 409 | * |
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| 410 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 411 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 412 | * table |
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| 413 | * |
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| 414 | * PowerPC Specific Information: |
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| 415 | * |
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| 416 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
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| 417 | * They do not use the simple vectored interrupt model. |
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| 418 | */ |
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| 419 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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| 420 | |
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[af16a7d2] | 421 | /* |
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| 422 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 423 | * |
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| 424 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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| 425 | * If FALSE, nothing is done. |
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| 426 | * |
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| 427 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 428 | * then it is generally the responsibility of the BSP to allocate it |
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| 429 | * and set it up. |
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| 430 | * |
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| 431 | * If the CPU does not support a dedicated interrupt stack, then |
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| 432 | * the porter has two options: (1) execute interrupts on the |
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| 433 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 434 | * interrupt stack. |
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| 435 | * |
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| 436 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 437 | * |
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| 438 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 439 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 440 | * possible that both are FALSE for a particular CPU. Although it |
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| 441 | * is unclear what that would imply about the interrupt processing |
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| 442 | * procedure on that CPU. |
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| 443 | */ |
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| 444 | |
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| 445 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 446 | |
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| 447 | /* |
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| 448 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 449 | * |
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| 450 | * If TRUE, then it must be installed during initialization. |
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| 451 | * If FALSE, then no installation is performed. |
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| 452 | * |
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| 453 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 454 | * |
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| 455 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 456 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 457 | * possible that both are FALSE for a particular CPU. Although it |
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| 458 | * is unclear what that would imply about the interrupt processing |
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| 459 | * procedure on that CPU. |
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| 460 | */ |
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| 461 | |
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| 462 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 463 | |
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| 464 | /* |
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| 465 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 466 | * |
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| 467 | * If TRUE, then the memory is allocated during initialization. |
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| 468 | * If FALSE, then the memory is allocated during initialization. |
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| 469 | * |
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| 470 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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| 471 | */ |
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| 472 | |
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| 473 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 474 | |
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| 475 | /* |
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| 476 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 477 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 478 | * number (0)? |
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| 479 | */ |
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| 480 | |
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| 481 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 482 | |
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| 483 | /* |
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| 484 | * Should the saving of the floating point registers be deferred |
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| 485 | * until a context switch is made to another different floating point |
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| 486 | * task? |
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| 487 | * |
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| 488 | * If TRUE, then the floating point context will not be stored until |
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| 489 | * necessary. It will remain in the floating point registers and not |
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| 490 | * disturned until another floating point task is switched to. |
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| 491 | * |
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| 492 | * If FALSE, then the floating point context is saved when a floating |
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| 493 | * point task is switched out and restored when the next floating point |
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| 494 | * task is restored. The state of the floating point registers between |
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| 495 | * those two operations is not specified. |
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| 496 | * |
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| 497 | * If the floating point context does NOT have to be saved as part of |
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| 498 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 499 | * |
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| 500 | * Setting this flag to TRUE results in using a different algorithm |
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| 501 | * for deciding when to save and restore the floating point context. |
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| 502 | * The deferred FP switch algorithm minimizes the number of times |
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| 503 | * the FP context is saved and restored. The FP context is not saved |
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| 504 | * until a context switch is made to another, different FP task. |
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| 505 | * Thus in a system with only one FP task, the FP context will never |
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| 506 | * be saved or restored. |
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| 507 | * |
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| 508 | * Note, however that compilers may use floating point registers/ |
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| 509 | * instructions for optimization or they may save/restore FP registers |
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| 510 | * on the stack. You must not use deferred switching in these cases |
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| 511 | * and on the PowerPC attempting to do so will raise a "FP unavailable" |
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| 512 | * exception. |
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| 513 | */ |
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| 514 | /* |
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| 515 | * ACB Note: This could make debugging tricky.. |
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| 516 | */ |
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| 517 | |
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| 518 | /* conservative setting (FALSE); probably doesn't affect performance too much */ |
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| 519 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 520 | |
---|
| 521 | /* |
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| 522 | * Processor defined structures required for cpukit/score. |
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| 523 | */ |
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| 524 | |
---|
| 525 | #ifndef ASM |
---|
| 526 | |
---|
| 527 | /* |
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| 528 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 529 | * to generate an "uninitialized" FP context. It is filled in by |
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| 530 | * _CPU_Initialize and copied into the task's FP context area during |
---|
| 531 | * _CPU_Context_Initialize. |
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| 532 | */ |
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| 533 | |
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| 534 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
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| 535 | |
---|
| 536 | #endif /* ndef ASM */ |
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| 537 | |
---|
| 538 | /* |
---|
| 539 | * This defines the number of levels and the mask used to pick those |
---|
| 540 | * bits out of a thread mode. |
---|
| 541 | */ |
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| 542 | |
---|
| 543 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
---|
| 544 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 545 | |
---|
| 546 | /* |
---|
| 547 | * Nothing prevents the porter from declaring more CPU specific variables. |
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| 548 | */ |
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| 549 | |
---|
| 550 | #ifndef ASM |
---|
| 551 | |
---|
| 552 | SCORE_EXTERN struct { |
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| 553 | uint32_t *Disable_level; |
---|
| 554 | void *Stack; |
---|
| 555 | volatile bool *Switch_necessary; |
---|
| 556 | bool *Signal; |
---|
| 557 | |
---|
| 558 | } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; |
---|
| 559 | |
---|
| 560 | #endif /* ndef ASM */ |
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| 561 | |
---|
| 562 | /* |
---|
| 563 | * The size of the floating point context area. On some CPUs this |
---|
| 564 | * will not be a "sizeof" because the format of the floating point |
---|
| 565 | * area is not defined -- only the size is. This is usually on |
---|
| 566 | * CPUs with a "floating point save context" instruction. |
---|
| 567 | */ |
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| 568 | |
---|
| 569 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 570 | |
---|
| 571 | /* |
---|
| 572 | * (Optional) # of bytes for libmisc/stackchk to check |
---|
| 573 | * If not specifed, then it defaults to something reasonable |
---|
| 574 | * for most architectures. |
---|
| 575 | */ |
---|
| 576 | |
---|
| 577 | #define CPU_STACK_CHECK_SIZE (128) |
---|
| 578 | |
---|
| 579 | /* |
---|
| 580 | * Amount of extra stack (above minimum stack size) required by |
---|
| 581 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 582 | * system this thread must exist and be able to process all directives. |
---|
| 583 | */ |
---|
| 584 | |
---|
| 585 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 586 | |
---|
| 587 | /* |
---|
| 588 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 589 | * by RTEMS. |
---|
[826fa6b1] | 590 | * |
---|
| 591 | * NOTE: CPU_INTERRUPT_NUMBER_OF_VECTORS and |
---|
| 592 | * CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER are only used on |
---|
| 593 | * Simple Vectored Architectures and thus are not defined |
---|
| 594 | * for this architecture. |
---|
[af16a7d2] | 595 | */ |
---|
| 596 | |
---|
| 597 | /* |
---|
| 598 | * This is defined if the port has a special way to report the ISR nesting |
---|
| 599 | * level. Most ports maintain the variable _ISR_Nest_level. Note that |
---|
| 600 | * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
---|
| 601 | * being maintained (e.g. watchdog queues). |
---|
| 602 | */ |
---|
| 603 | |
---|
| 604 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 605 | |
---|
| 606 | /* |
---|
| 607 | * ISR handler macros |
---|
| 608 | */ |
---|
| 609 | |
---|
| 610 | /* |
---|
| 611 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 612 | * level is returned in _isr_cookie. |
---|
| 613 | */ |
---|
| 614 | |
---|
| 615 | #ifndef ASM |
---|
| 616 | |
---|
| 617 | static inline uint32_t _CPU_ISR_Get_level( void ) |
---|
| 618 | { |
---|
| 619 | register unsigned int msr; |
---|
| 620 | _CPU_MSR_GET(msr); |
---|
| 621 | if (msr & MSR_EE) return 0; |
---|
| 622 | else return 1; |
---|
| 623 | } |
---|
| 624 | |
---|
| 625 | static inline void _CPU_ISR_Set_level( uint32_t level ) |
---|
| 626 | { |
---|
| 627 | register unsigned int msr; |
---|
| 628 | _CPU_MSR_GET(msr); |
---|
| 629 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
---|
| 630 | msr |= ppc_interrupt_get_disable_mask(); |
---|
| 631 | } |
---|
| 632 | else { |
---|
| 633 | msr &= ~ppc_interrupt_get_disable_mask(); |
---|
| 634 | } |
---|
| 635 | _CPU_MSR_SET(msr); |
---|
| 636 | } |
---|
| 637 | |
---|
| 638 | void BSP_panic(char *); |
---|
| 639 | |
---|
| 640 | /* Fatal Error manager macros */ |
---|
| 641 | |
---|
| 642 | /* |
---|
| 643 | * This routine copies _error into a known place -- typically a stack |
---|
| 644 | * location or a register, optionally disables interrupts, and |
---|
| 645 | * halts/stops the CPU. |
---|
| 646 | */ |
---|
| 647 | |
---|
| 648 | void _BSP_Fatal_error(unsigned int); |
---|
| 649 | |
---|
| 650 | #endif /* ASM */ |
---|
| 651 | |
---|
| 652 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 653 | _BSP_Fatal_error(_error) |
---|
| 654 | |
---|
| 655 | /* end of Fatal Error manager macros */ |
---|
| 656 | |
---|
| 657 | /* |
---|
| 658 | * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug. |
---|
| 659 | * Now SPRG0 is devoted to the interrupt disable mask. |
---|
| 660 | */ |
---|
| 661 | |
---|
| 662 | #define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask |
---|
[4a0d87e] | 663 | |
---|
[b4f43549] | 664 | /* |
---|
[5961b4c7] | 665 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[b4f43549] | 666 | * that a "reasonable" small application should not have any problems. |
---|
| 667 | */ |
---|
| 668 | |
---|
| 669 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
---|
| 670 | |
---|
| 671 | /* |
---|
| 672 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 673 | * alignment does not take into account the requirements for the stack. |
---|
| 674 | */ |
---|
| 675 | |
---|
| 676 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 677 | |
---|
| 678 | /* |
---|
| 679 | * This number corresponds to the byte alignment requirement for the |
---|
| 680 | * heap handler. This alignment requirement may be stricter than that |
---|
| 681 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 682 | * common for the heap to follow the same alignment requirement as |
---|
| 683 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 684 | * then this should be set to CPU_ALIGNMENT. |
---|
| 685 | * |
---|
| 686 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 687 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 688 | */ |
---|
| 689 | |
---|
| 690 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 691 | |
---|
| 692 | /* |
---|
| 693 | * This number corresponds to the byte alignment requirement for memory |
---|
| 694 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 695 | * may be stricter than that for the data types alignment specified by |
---|
| 696 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 697 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 698 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 699 | * |
---|
| 700 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 701 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 702 | */ |
---|
| 703 | |
---|
| 704 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 705 | |
---|
| 706 | /* |
---|
| 707 | * This number corresponds to the byte alignment requirement for the |
---|
| 708 | * stack. This alignment requirement may be stricter than that for the |
---|
| 709 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 710 | * is strict enough for the stack, then this should be set to 0. |
---|
| 711 | * |
---|
| 712 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 713 | */ |
---|
| 714 | |
---|
| 715 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
---|
| 716 | |
---|
[d4214b0] | 717 | #ifndef ASM |
---|
| 718 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 719 | * It must be static because it is referenced indirectly. |
---|
| 720 | * |
---|
| 721 | * This version will work on any processor, but if there is a better |
---|
| 722 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 723 | * |
---|
| 724 | * swap least significant two bytes with 16-bit rotate |
---|
| 725 | * swap upper and lower 16-bits |
---|
| 726 | * swap most significant two bytes with 16-bit rotate |
---|
| 727 | * |
---|
| 728 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 729 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 730 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[5961b4c7] | 731 | * that interrupts would probably have to be disabled to ensure that |
---|
[d4214b0] | 732 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 733 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 734 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 735 | * will be fetched incorrectly. |
---|
| 736 | */ |
---|
[5bb38e15] | 737 | |
---|
[d4214b0] | 738 | static inline uint32_t CPU_swap_u32( |
---|
| 739 | uint32_t value |
---|
| 740 | ) |
---|
| 741 | { |
---|
| 742 | uint32_t swapped; |
---|
[5bb38e15] | 743 | |
---|
[3631c234] | 744 | __asm__ volatile("rlwimi %0,%1,8,24,31;" |
---|
[d4214b0] | 745 | "rlwimi %0,%1,24,16,23;" |
---|
| 746 | "rlwimi %0,%1,8,8,15;" |
---|
| 747 | "rlwimi %0,%1,24,0,7;" : |
---|
| 748 | "=&r" ((swapped)) : "r" ((value))); |
---|
| 749 | |
---|
| 750 | return( swapped ); |
---|
| 751 | } |
---|
| 752 | |
---|
| 753 | #define CPU_swap_u16( value ) \ |
---|
| 754 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 755 | |
---|
| 756 | #endif /* ASM */ |
---|
| 757 | |
---|
[58847845] | 758 | |
---|
[6b25a47] | 759 | #ifndef ASM |
---|
| 760 | /* Context handler macros */ |
---|
| 761 | |
---|
| 762 | /* |
---|
| 763 | * Initialize the context to a state suitable for starting a |
---|
| 764 | * task after a context restore operation. Generally, this |
---|
| 765 | * involves: |
---|
| 766 | * |
---|
| 767 | * - setting a starting address |
---|
| 768 | * - preparing the stack |
---|
| 769 | * - preparing the stack and frame pointers |
---|
| 770 | * - setting the proper interrupt level in the context |
---|
| 771 | * - initializing the floating point context |
---|
| 772 | * |
---|
| 773 | * This routine generally does not set any unnecessary register |
---|
| 774 | * in the context. The state of the "general data" registers is |
---|
| 775 | * undefined at task start time. |
---|
| 776 | */ |
---|
[d4214b0] | 777 | |
---|
[6b25a47] | 778 | void _CPU_Context_Initialize( |
---|
| 779 | Context_Control *the_context, |
---|
| 780 | uint32_t *stack_base, |
---|
| 781 | uint32_t size, |
---|
| 782 | uint32_t new_level, |
---|
| 783 | void *entry_point, |
---|
[5d42c1b7] | 784 | bool is_fp |
---|
[6b25a47] | 785 | ); |
---|
| 786 | |
---|
| 787 | /* |
---|
| 788 | * This routine is responsible for somehow restarting the currently |
---|
| 789 | * executing task. If you are lucky, then all that is necessary |
---|
| 790 | * is restoring the context. Otherwise, there will need to be |
---|
| 791 | * a special assembly routine which does something special in this |
---|
| 792 | * case. Context_Restore should work most of the time. It will |
---|
| 793 | * not work if restarting self conflicts with the stack frame |
---|
| 794 | * assumptions of restoring a context. |
---|
| 795 | */ |
---|
| 796 | |
---|
| 797 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 798 | _CPU_Context_restore( (_the_context) ); |
---|
| 799 | |
---|
| 800 | /* |
---|
| 801 | * The purpose of this macro is to allow the initial pointer into |
---|
| 802 | * a floating point context area (used to save the floating point |
---|
| 803 | * context) to be at an arbitrary place in the floating point |
---|
| 804 | * context area. |
---|
| 805 | * |
---|
| 806 | * This is necessary because some FP units are designed to have |
---|
| 807 | * their context saved as a stack which grows into lower addresses. |
---|
| 808 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 809 | * from the base of the context area. Finally some FP units provide |
---|
| 810 | * a "dump context" instruction which could fill in from high to low |
---|
| 811 | * or low to high based on the whim of the CPU designers. |
---|
| 812 | */ |
---|
| 813 | |
---|
| 814 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 815 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 816 | |
---|
| 817 | /* |
---|
| 818 | * This routine initializes the FP context area passed to it to. |
---|
| 819 | * There are a few standard ways in which to initialize the |
---|
| 820 | * floating point context. The code included for this macro assumes |
---|
| 821 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 822 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 823 | * context passed to it. |
---|
| 824 | * |
---|
| 825 | * Other models include (1) not doing anything, and (2) putting |
---|
| 826 | * a "null FP status word" in the correct place in the FP context. |
---|
| 827 | */ |
---|
| 828 | |
---|
| 829 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
[2067679] | 830 | memset( *(_destination), 0, sizeof( **(_destination) ) ) |
---|
[6b25a47] | 831 | |
---|
| 832 | /* end of Context handler macros */ |
---|
| 833 | #endif /* ASM */ |
---|
| 834 | |
---|
[779939b2] | 835 | #ifndef ASM |
---|
| 836 | /* Bitfield handler macros */ |
---|
| 837 | |
---|
| 838 | /* |
---|
| 839 | * This routine sets _output to the bit number of the first bit |
---|
[4ef13360] | 840 | * set in _value. _value is of CPU dependent type Priority_bit_map_Control. |
---|
[779939b2] | 841 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 842 | * least significant bits will be used. |
---|
| 843 | * |
---|
| 844 | * There are a number of variables in using a "find first bit" type |
---|
| 845 | * instruction. |
---|
| 846 | * |
---|
| 847 | * (1) What happens when run on a value of zero? |
---|
| 848 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 849 | * (3) The numbering may be zero or one based. |
---|
| 850 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 851 | * |
---|
| 852 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 853 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 854 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
| 855 | * which must logically operate together. Bits in the _value are |
---|
| 856 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 857 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 858 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
| 859 | * to properly range between the values returned by the "find first bit" |
---|
| 860 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 861 | * calculate the major and directly index into the minor table. |
---|
| 862 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 863 | * is the first bit found. |
---|
| 864 | * |
---|
| 865 | * This entire "find first bit" and mapping process depends heavily |
---|
| 866 | * on the manner in which a priority is broken into a major and minor |
---|
| 867 | * components with the major being the 4 MSB of a priority and minor |
---|
| 868 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 869 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 870 | * to the lowest priority. |
---|
| 871 | * |
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| 872 | * If your CPU does not have a "find first bit" instruction, then |
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| 873 | * there are ways to make do without it. Here are a handful of ways |
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| 874 | * to implement this in software: |
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| 875 | * |
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| 876 | * - a series of 16 bit test instructions |
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| 877 | * - a "binary search using if's" |
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| 878 | * - _number = 0 |
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| 879 | * if _value > 0x00ff |
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| 880 | * _value >>=8 |
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| 881 | * _number = 8; |
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| 882 | * |
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| 883 | * if _value > 0x0000f |
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| 884 | * _value >=8 |
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| 885 | * _number += 4 |
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| 886 | * |
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| 887 | * _number += bit_set_table[ _value ] |
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| 888 | * |
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| 889 | * where bit_set_table[ 16 ] has values which indicate the first |
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| 890 | * bit set |
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| 891 | */ |
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| 892 | |
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| 893 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 894 | { \ |
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[3631c234] | 895 | __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
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[779939b2] | 896 | "1" ((_value))); \ |
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| 897 | } |
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| 898 | |
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| 899 | /* end of Bitfield handler macros */ |
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| 900 | |
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| 901 | /* |
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| 902 | * This routine builds the mask which corresponds to the bit fields |
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| 903 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
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| 904 | * for that routine. |
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| 905 | */ |
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| 906 | |
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| 907 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 908 | ( 0x80000000 >> (_bit_number) ) |
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| 909 | |
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| 910 | /* |
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| 911 | * This routine translates the bit numbers returned by |
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| 912 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
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| 913 | * a major or minor component of a priority. See the discussion |
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| 914 | * for that routine. |
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| 915 | */ |
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| 916 | |
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| 917 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 918 | (_priority) |
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| 919 | |
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| 920 | /* end of Priority handler macros */ |
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| 921 | #endif /* ASM */ |
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| 922 | |
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[8773879] | 923 | /* functions */ |
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| 924 | |
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| 925 | #ifndef ASM |
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| 926 | |
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| 927 | /* |
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| 928 | * _CPU_Initialize |
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| 929 | * |
---|
| 930 | * This routine performs CPU dependent initialization. |
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| 931 | */ |
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| 932 | |
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[ef1be69] | 933 | void _CPU_Initialize(void); |
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[8773879] | 934 | |
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| 935 | /* |
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| 936 | * _CPU_ISR_install_vector |
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| 937 | * |
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| 938 | * This routine installs an interrupt vector. |
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| 939 | */ |
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| 940 | |
---|
| 941 | void _CPU_ISR_install_vector( |
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| 942 | uint32_t vector, |
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| 943 | proc_ptr new_handler, |
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| 944 | proc_ptr *old_handler |
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| 945 | ); |
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| 946 | |
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| 947 | /* |
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| 948 | * _CPU_Install_interrupt_stack |
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| 949 | * |
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| 950 | * This routine installs the hardware interrupt stack pointer. |
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| 951 | * |
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| 952 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
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| 953 | * is TRUE. |
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| 954 | */ |
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| 955 | |
---|
| 956 | void _CPU_Install_interrupt_stack( void ); |
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| 957 | |
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| 958 | /* |
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| 959 | * _CPU_Context_switch |
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| 960 | * |
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| 961 | * This routine switches from the run context to the heir context. |
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| 962 | */ |
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| 963 | |
---|
| 964 | void _CPU_Context_switch( |
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| 965 | Context_Control *run, |
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| 966 | Context_Control *heir |
---|
| 967 | ); |
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| 968 | |
---|
| 969 | /* |
---|
| 970 | * _CPU_Context_restore |
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| 971 | * |
---|
| 972 | * This routine is generallu used only to restart self in an |
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| 973 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 974 | * |
---|
| 975 | * NOTE: May be unnecessary to reload some registers. |
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| 976 | */ |
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| 977 | |
---|
| 978 | void _CPU_Context_restore( |
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| 979 | Context_Control *new_context |
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[479cbaf8] | 980 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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[8773879] | 981 | |
---|
| 982 | /* |
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| 983 | * _CPU_Context_save_fp |
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| 984 | * |
---|
| 985 | * This routine saves the floating point context passed to it. |
---|
| 986 | */ |
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| 987 | |
---|
| 988 | void _CPU_Context_save_fp( |
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[b60dc893] | 989 | Context_Control_fp **fp_context_ptr |
---|
[8773879] | 990 | ); |
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| 991 | |
---|
| 992 | /* |
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| 993 | * _CPU_Context_restore_fp |
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| 994 | * |
---|
| 995 | * This routine restores the floating point context passed to it. |
---|
| 996 | */ |
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| 997 | |
---|
| 998 | void _CPU_Context_restore_fp( |
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[b60dc893] | 999 | Context_Control_fp **fp_context_ptr |
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[8773879] | 1000 | ); |
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| 1001 | |
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[6c28773e] | 1002 | /* |
---|
| 1003 | * _CPU_Initialize_altivec() |
---|
| 1004 | * |
---|
| 1005 | * Global altivec-related initialization. |
---|
| 1006 | */ |
---|
| 1007 | void |
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| 1008 | _CPU_Initialize_altivec(void); |
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| 1009 | |
---|
| 1010 | /* |
---|
| 1011 | * _CPU_Context_switch_altivec |
---|
| 1012 | * |
---|
| 1013 | * This routine switches the altivec contexts passed to it. |
---|
| 1014 | */ |
---|
| 1015 | |
---|
| 1016 | void |
---|
| 1017 | _CPU_Context_switch_altivec( |
---|
| 1018 | Context_Control *from, |
---|
| 1019 | Context_Control *to |
---|
| 1020 | ); |
---|
| 1021 | |
---|
| 1022 | /* |
---|
| 1023 | * _CPU_Context_restore_altivec |
---|
| 1024 | * |
---|
| 1025 | * This routine restores the altivec context passed to it. |
---|
| 1026 | */ |
---|
| 1027 | |
---|
| 1028 | void |
---|
| 1029 | _CPU_Context_restore_altivec( |
---|
| 1030 | Context_Control *ctxt |
---|
| 1031 | ); |
---|
| 1032 | |
---|
| 1033 | /* |
---|
| 1034 | * _CPU_Context_initialize_altivec |
---|
| 1035 | * |
---|
| 1036 | * This routine initializes the altivec context passed to it. |
---|
| 1037 | */ |
---|
| 1038 | |
---|
| 1039 | void |
---|
| 1040 | _CPU_Context_initialize_altivec( |
---|
| 1041 | Context_Control *ctxt |
---|
| 1042 | ); |
---|
| 1043 | |
---|
[8773879] | 1044 | void _CPU_Fatal_error( |
---|
| 1045 | uint32_t _error |
---|
| 1046 | ); |
---|
| 1047 | |
---|
| 1048 | #endif /* ASM */ |
---|
| 1049 | |
---|
[af16a7d2] | 1050 | #ifdef __cplusplus |
---|
| 1051 | } |
---|
| 1052 | #endif |
---|
| 1053 | |
---|
[6b25a47] | 1054 | #endif /* _RTEMS_SCORE_CPU_H */ |
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