[d5607c5a] | 1 | /** |
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[d9e0006] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief PowerPC CPU Department Source |
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[d5607c5a] | 5 | */ |
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| 6 | |
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[4a0d87e] | 7 | /* |
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[826fa6b1] | 8 | * COPYRIGHT (c) 1989-2012. |
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[43b4c7a] | 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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[af16a7d2] | 11 | * COPYRIGHT (c) 1995 i-cubed ltd. |
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| 12 | * |
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| 13 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 14 | * without any express or implied warranty: |
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| 15 | * permission to use, copy, modify, and distribute this file |
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| 16 | * for any purpose is hereby granted without fee, provided that |
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| 17 | * the above copyright notice and this notice appears in all |
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| 18 | * copies, and that the name of i-cubed limited not be used in |
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| 19 | * advertising or publicity pertaining to distribution of the |
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| 20 | * software without specific, written prior permission. |
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| 21 | * i-cubed limited makes no representations about the suitability |
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| 22 | * of this software for any purpose. |
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| 23 | * |
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| 24 | * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. |
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| 25 | * |
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| 26 | * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). |
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| 27 | * |
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[7ce60b3] | 28 | * Copyright (c) 2010, 2016 embedded brains GmbH. |
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[af16a7d2] | 29 | * |
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[43b4c7a] | 30 | * The license and distribution terms for this file may be |
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| 31 | * found in the file LICENSE in this distribution or at |
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[c499856] | 32 | * http://www.rtems.org/license/LICENSE. |
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[4a0d87e] | 33 | */ |
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[5bb38e15] | 34 | |
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[7f70d1b7] | 35 | #ifndef _RTEMS_SCORE_CPU_H |
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| 36 | #define _RTEMS_SCORE_CPU_H |
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[4a0d87e] | 37 | |
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[af16a7d2] | 38 | #include <rtems/score/types.h> |
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| 39 | #include <rtems/score/powerpc.h> |
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| 40 | #include <rtems/powerpc/registers.h> |
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[2067679] | 41 | |
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[4a0d87e] | 42 | #ifndef ASM |
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[2067679] | 43 | #include <string.h> /* for memset() */ |
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[af16a7d2] | 44 | #endif |
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| 45 | |
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| 46 | #ifdef __cplusplus |
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| 47 | extern "C" { |
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[4a0d87e] | 48 | #endif |
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| 49 | |
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[8ecc042a] | 50 | /* conditional compilation parameters */ |
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| 51 | |
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[10c66191] | 52 | /* |
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| 53 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 54 | * |
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| 55 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 56 | * must be provided and is the default IDLE thread body instead of |
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| 57 | * _CPU_Thread_Idle_body. |
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| 58 | * |
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| 59 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 60 | * not provide one. |
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| 61 | * |
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| 62 | * This is intended to allow for supporting processors which have |
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| 63 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 64 | * the CPU can be powered down. |
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| 65 | * |
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| 66 | * The order of precedence for selecting the IDLE thread body is: |
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| 67 | * |
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| 68 | * 1. BSP provided |
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| 69 | * 2. CPU dependent (if provided) |
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| 70 | * 3. generic (if no BSP and no CPU dependent) |
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| 71 | */ |
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| 72 | |
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| 73 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 74 | |
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| 75 | /* |
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| 76 | * Does the stack grow up (toward higher addresses) or down |
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| 77 | * (toward lower addresses)? |
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| 78 | * |
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| 79 | * If TRUE, then the grows upward. |
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| 80 | * If FALSE, then the grows toward smaller addresses. |
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| 81 | */ |
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| 82 | |
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| 83 | #define CPU_STACK_GROWS_UP FALSE |
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| 84 | |
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[a8865f8] | 85 | #define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT |
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[10c66191] | 86 | |
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[a8865f8] | 87 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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[10c66191] | 88 | |
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[56c5e091] | 89 | /* |
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| 90 | * Does the CPU have hardware floating point? |
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| 91 | * |
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| 92 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 93 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 94 | * |
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| 95 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 96 | * the answer is TRUE. |
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| 97 | * |
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| 98 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
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| 99 | * It indicates whether or not this CPU model has FP support. For |
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| 100 | * example, it would be possible to have an i386_nofp CPU model |
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| 101 | * which set this to false to indicate that you have an i386 without |
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| 102 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 103 | */ |
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| 104 | |
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| 105 | #if ( PPC_HAS_FPU == 1 ) |
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| 106 | #define CPU_HARDWARE_FP TRUE |
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| 107 | #define CPU_SOFTWARE_FP FALSE |
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| 108 | #else |
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| 109 | #define CPU_HARDWARE_FP FALSE |
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| 110 | #define CPU_SOFTWARE_FP FALSE |
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| 111 | #endif |
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| 112 | |
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| 113 | /* |
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| 114 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 115 | * |
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| 116 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 117 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 118 | * |
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| 119 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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[a19034d] | 120 | * |
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| 121 | * PowerPC Note: It appears the GCC can implicitly generate FPU |
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| 122 | * and Altivec instructions when you least expect them. So make |
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| 123 | * all tasks floating point. |
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[56c5e091] | 124 | */ |
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| 125 | |
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[a19034d] | 126 | #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
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[56c5e091] | 127 | |
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| 128 | /* |
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| 129 | * Should the IDLE task have a floating point context? |
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| 130 | * |
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| 131 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 132 | * and it has a floating point context which is switched in and out. |
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| 133 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 134 | * |
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| 135 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 136 | * the IDLE task from an interrupt because the floating point context |
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| 137 | * must be saved as part of the preemption. |
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| 138 | */ |
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| 139 | |
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| 140 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 141 | |
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[decff899] | 142 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 143 | |
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[b7c7b75b] | 144 | /* |
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| 145 | * Processor defined structures required for cpukit/score. |
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| 146 | */ |
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| 147 | |
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| 148 | /* |
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| 149 | * Contexts |
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| 150 | * |
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| 151 | * Generally there are 2 types of context to save. |
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| 152 | * 1. Interrupt registers to save |
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| 153 | * 2. Task level registers to save |
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| 154 | * |
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| 155 | * This means we have the following 3 context items: |
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| 156 | * 1. task level context stuff:: Context_Control |
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| 157 | * 2. floating point task stuff:: Context_Control_fp |
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| 158 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 159 | * |
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| 160 | * On some processors, it is cost-effective to save only the callee |
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| 161 | * preserved registers during a task context switch. This means |
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| 162 | * that the ISR code needs to save those registers which do not |
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| 163 | * persist across function calls. It is not mandatory to make this |
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| 164 | * distinctions between the caller/callee saves registers for the |
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| 165 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 166 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 167 | * choice. Save the same context on interrupt entry as for tasks in |
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| 168 | * this case. |
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| 169 | * |
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| 170 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 171 | * care should be used in designing the context area. |
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| 172 | * |
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| 173 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 174 | * structure will not be used or it simply consist of an array of a |
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| 175 | * fixed number of bytes. This is done when the floating point context |
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| 176 | * is dumped by a "FP save context" type instruction and the format |
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| 177 | * is not really defined by the CPU. In this case, there is no need |
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| 178 | * to figure out the exact format -- only the size. Of course, although |
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| 179 | * this is enough information for RTEMS, it is probably not enough for |
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| 180 | * a debugger such as gdb. But that is another problem. |
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| 181 | */ |
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| 182 | |
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[c3ba11ac] | 183 | #ifndef __SPE__ |
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[1869bb7] | 184 | #define PPC_GPR_TYPE uint32_t |
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| 185 | #define PPC_GPR_SIZE 4 |
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| 186 | #define PPC_GPR_LOAD lwz |
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| 187 | #define PPC_GPR_STORE stw |
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| 188 | #else |
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| 189 | #define PPC_GPR_TYPE uint64_t |
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| 190 | #define PPC_GPR_SIZE 8 |
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| 191 | #define PPC_GPR_LOAD evldd |
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| 192 | #define PPC_GPR_STORE evstdd |
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| 193 | #endif |
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[c3ba11ac] | 194 | |
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[1869bb7] | 195 | #ifndef ASM |
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[5be93c2] | 196 | |
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[39a4574] | 197 | /* |
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| 198 | * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according |
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| 199 | * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - |
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| 200 | * Linux and Embedded") |
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| 201 | */ |
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[1869bb7] | 202 | typedef struct { |
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| 203 | uint32_t gpr1; |
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| 204 | uint32_t msr; |
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| 205 | uint32_t lr; |
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| 206 | uint32_t cr; |
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| 207 | PPC_GPR_TYPE gpr14; |
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| 208 | PPC_GPR_TYPE gpr15; |
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| 209 | PPC_GPR_TYPE gpr16; |
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| 210 | PPC_GPR_TYPE gpr17; |
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| 211 | PPC_GPR_TYPE gpr18; |
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| 212 | PPC_GPR_TYPE gpr19; |
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| 213 | PPC_GPR_TYPE gpr20; |
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| 214 | PPC_GPR_TYPE gpr21; |
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| 215 | PPC_GPR_TYPE gpr22; |
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| 216 | PPC_GPR_TYPE gpr23; |
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| 217 | PPC_GPR_TYPE gpr24; |
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| 218 | PPC_GPR_TYPE gpr25; |
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| 219 | PPC_GPR_TYPE gpr26; |
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| 220 | PPC_GPR_TYPE gpr27; |
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| 221 | PPC_GPR_TYPE gpr28; |
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| 222 | PPC_GPR_TYPE gpr29; |
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| 223 | PPC_GPR_TYPE gpr30; |
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| 224 | PPC_GPR_TYPE gpr31; |
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[39a4574] | 225 | uint32_t gpr2; |
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[7ce60b3] | 226 | uint32_t isr_dispatch_disable; |
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[3e2647a7] | 227 | #if defined(PPC_MULTILIB_ALTIVEC) |
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| 228 | uint8_t v20[16]; |
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| 229 | uint8_t v21[16]; |
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| 230 | uint8_t v22[16]; |
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| 231 | uint8_t v23[16]; |
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| 232 | uint8_t v24[16]; |
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| 233 | uint8_t v25[16]; |
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| 234 | uint8_t v26[16]; |
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| 235 | uint8_t v27[16]; |
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| 236 | uint8_t v28[16]; |
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| 237 | uint8_t v29[16]; |
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| 238 | uint8_t v30[16]; |
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| 239 | uint8_t v31[16]; |
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| 240 | uint32_t vrsave; |
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| 241 | #elif defined(__ALTIVEC__) |
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[1869bb7] | 242 | /* |
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| 243 | * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave |
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| 244 | * and padding to ensure cache-alignment. Unfortunately, we can't verify |
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| 245 | * the cache line size here in the cpukit but altivec support code will |
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| 246 | * produce an error if this is ever different from 32 bytes. |
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| 247 | * |
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| 248 | * Note: it is the BSP/CPU-support's responsibility to save/restore |
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| 249 | * volatile vregs across interrupts and exceptions. |
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| 250 | */ |
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| 251 | uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; |
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| 252 | #endif |
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[3e2647a7] | 253 | #if defined(PPC_MULTILIB_FPU) |
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| 254 | double f14; |
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| 255 | double f15; |
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| 256 | double f16; |
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| 257 | double f17; |
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| 258 | double f18; |
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| 259 | double f19; |
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| 260 | double f20; |
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| 261 | double f21; |
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| 262 | double f22; |
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| 263 | double f23; |
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| 264 | double f24; |
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| 265 | double f25; |
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| 266 | double f26; |
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| 267 | double f27; |
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| 268 | double f28; |
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| 269 | double f29; |
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| 270 | double f30; |
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| 271 | double f31; |
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| 272 | #endif |
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| 273 | #if defined(RTEMS_SMP) |
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| 274 | /* |
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| 275 | * This item is at the structure end, so that we can use dcbz for the |
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| 276 | * previous items to optimize the context switch. We must not set this |
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| 277 | * item to zero via the dcbz. |
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| 278 | */ |
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| 279 | volatile uint32_t is_executing; |
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| 280 | #endif |
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[1869bb7] | 281 | } ppc_context; |
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[c3ba11ac] | 282 | |
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[1869bb7] | 283 | typedef struct { |
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| 284 | uint8_t context [ |
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| 285 | PPC_DEFAULT_CACHE_LINE_SIZE |
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| 286 | + sizeof(ppc_context) |
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| 287 | + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 |
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| 288 | ? 0 |
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| 289 | : PPC_DEFAULT_CACHE_LINE_SIZE |
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| 290 | - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) |
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| 291 | ]; |
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| 292 | } Context_Control; |
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[5be93c2] | 293 | |
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[38b59a6] | 294 | static inline ppc_context *ppc_get_context( const Context_Control *context ) |
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[1869bb7] | 295 | { |
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| 296 | uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; |
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| 297 | uintptr_t mask = clsz - 1; |
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| 298 | uintptr_t addr = (uintptr_t) context; |
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[5be93c2] | 299 | |
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[1869bb7] | 300 | return (ppc_context *) ((addr & ~mask) + clsz); |
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| 301 | } |
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[5be93c2] | 302 | |
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[1869bb7] | 303 | #define _CPU_Context_Get_SP( _context ) \ |
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| 304 | ppc_get_context(_context)->gpr1 |
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[38b59a6] | 305 | |
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| 306 | #ifdef RTEMS_SMP |
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[11b05f1] | 307 | static inline bool _CPU_Context_Get_is_executing( |
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| 308 | const Context_Control *context |
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| 309 | ) |
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| 310 | { |
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| 311 | return ppc_get_context(context)->is_executing; |
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| 312 | } |
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| 313 | |
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| 314 | static inline void _CPU_Context_Set_is_executing( |
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| 315 | Context_Control *context, |
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| 316 | bool is_executing |
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| 317 | ) |
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| 318 | { |
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| 319 | ppc_get_context(context)->is_executing = is_executing; |
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| 320 | } |
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[38b59a6] | 321 | #endif |
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[1869bb7] | 322 | #endif /* ASM */ |
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[c3ba11ac] | 323 | |
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[7c16e1a5] | 324 | #define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0) |
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| 325 | #define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) |
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| 326 | #define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8) |
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| 327 | #define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12) |
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[1869bb7] | 328 | |
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| 329 | #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ |
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[7c16e1a5] | 330 | (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16) |
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[1869bb7] | 331 | |
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| 332 | #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) |
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| 333 | #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) |
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| 334 | #define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) |
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| 335 | #define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) |
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| 336 | #define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) |
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| 337 | #define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) |
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| 338 | #define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) |
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| 339 | #define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) |
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| 340 | #define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) |
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| 341 | #define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) |
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| 342 | #define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) |
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| 343 | #define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) |
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| 344 | #define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) |
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| 345 | #define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) |
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| 346 | #define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) |
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| 347 | #define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) |
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| 348 | #define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) |
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| 349 | #define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) |
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[39a4574] | 350 | #define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 ) |
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[7ce60b3] | 351 | #define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE \ |
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| 352 | ( PPC_CONTEXT_GPR_OFFSET( 32 ) + 4 ) |
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[b7c7b75b] | 353 | |
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[3e2647a7] | 354 | #ifdef PPC_MULTILIB_ALTIVEC |
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| 355 | #define PPC_CONTEXT_OFFSET_V( v ) \ |
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| 356 | ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) |
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| 357 | #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) |
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| 358 | #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) |
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| 359 | #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) |
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| 360 | #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) |
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| 361 | #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) |
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| 362 | #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) |
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| 363 | #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) |
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| 364 | #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) |
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| 365 | #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) |
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| 366 | #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) |
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| 367 | #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) |
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| 368 | #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) |
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| 369 | #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) |
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| 370 | #define PPC_CONTEXT_OFFSET_F( f ) \ |
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| 371 | ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 ) |
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| 372 | #else |
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| 373 | #define PPC_CONTEXT_OFFSET_F( f ) \ |
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| 374 | ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) |
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| 375 | #endif |
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| 376 | |
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| 377 | #ifdef PPC_MULTILIB_FPU |
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| 378 | #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) |
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| 379 | #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) |
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| 380 | #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) |
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| 381 | #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) |
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| 382 | #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) |
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| 383 | #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) |
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| 384 | #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) |
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| 385 | #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) |
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| 386 | #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) |
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| 387 | #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) |
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| 388 | #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) |
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| 389 | #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) |
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| 390 | #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) |
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| 391 | #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) |
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| 392 | #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) |
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| 393 | #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) |
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| 394 | #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) |
---|
| 395 | #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) |
---|
| 396 | #endif |
---|
| 397 | |
---|
| 398 | #if defined(PPC_MULTILIB_FPU) |
---|
| 399 | #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) |
---|
| 400 | #elif defined(PPC_MULTILIB_ALTIVEC) |
---|
| 401 | #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) |
---|
| 402 | #else |
---|
| 403 | #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4) |
---|
| 404 | #endif |
---|
| 405 | |
---|
[38b59a6] | 406 | #ifdef RTEMS_SMP |
---|
[3e2647a7] | 407 | #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE |
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[38b59a6] | 408 | #endif |
---|
| 409 | |
---|
[c3ba11ac] | 410 | #ifndef ASM |
---|
[b7c7b75b] | 411 | typedef struct { |
---|
[2e19bfd] | 412 | #if (PPC_HAS_FPU == 1) |
---|
[b7c7b75b] | 413 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
---|
| 414 | * procedure calls. However, this would mean that the interrupt |
---|
| 415 | * frame had to hold f0-f13, and the fpscr. And as the majority |
---|
| 416 | * of tasks will not have an FP context, we will save the whole |
---|
| 417 | * context here. |
---|
| 418 | */ |
---|
| 419 | #if (PPC_HAS_DOUBLE == 1) |
---|
| 420 | double f[32]; |
---|
[2067679] | 421 | uint64_t fpscr; |
---|
[b7c7b75b] | 422 | #else |
---|
| 423 | float f[32]; |
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[2067679] | 424 | uint32_t fpscr; |
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[b7c7b75b] | 425 | #endif |
---|
[2e19bfd] | 426 | #endif /* (PPC_HAS_FPU == 1) */ |
---|
[b7c7b75b] | 427 | } Context_Control_fp; |
---|
| 428 | |
---|
| 429 | #endif /* ASM */ |
---|
| 430 | |
---|
[9da42fb] | 431 | /* |
---|
| 432 | * Does the CPU follow the simple vectored interrupt model? |
---|
| 433 | * |
---|
| 434 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
---|
| 435 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
---|
| 436 | * table |
---|
| 437 | * |
---|
| 438 | * PowerPC Specific Information: |
---|
| 439 | * |
---|
| 440 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
---|
| 441 | * They do not use the simple vectored interrupt model. |
---|
| 442 | */ |
---|
| 443 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
---|
| 444 | |
---|
[af16a7d2] | 445 | /* |
---|
| 446 | * Does RTEMS manage a dedicated interrupt stack in software? |
---|
| 447 | * |
---|
| 448 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
---|
| 449 | * If FALSE, nothing is done. |
---|
| 450 | * |
---|
| 451 | * If the CPU supports a dedicated interrupt stack in hardware, |
---|
| 452 | * then it is generally the responsibility of the BSP to allocate it |
---|
| 453 | * and set it up. |
---|
| 454 | * |
---|
| 455 | * If the CPU does not support a dedicated interrupt stack, then |
---|
| 456 | * the porter has two options: (1) execute interrupts on the |
---|
| 457 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
---|
| 458 | * interrupt stack. |
---|
| 459 | * |
---|
| 460 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
| 461 | * |
---|
| 462 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 463 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
| 464 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 465 | * is unclear what that would imply about the interrupt processing |
---|
| 466 | * procedure on that CPU. |
---|
| 467 | */ |
---|
| 468 | |
---|
| 469 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
---|
| 470 | |
---|
| 471 | /* |
---|
| 472 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
| 473 | * |
---|
| 474 | * If TRUE, then it must be installed during initialization. |
---|
| 475 | * If FALSE, then no installation is performed. |
---|
| 476 | * |
---|
| 477 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
| 478 | * |
---|
| 479 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 480 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
| 481 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 482 | * is unclear what that would imply about the interrupt processing |
---|
| 483 | * procedure on that CPU. |
---|
| 484 | */ |
---|
| 485 | |
---|
| 486 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
---|
| 487 | |
---|
| 488 | /* |
---|
| 489 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
| 490 | * |
---|
| 491 | * If TRUE, then the memory is allocated during initialization. |
---|
| 492 | * If FALSE, then the memory is allocated during initialization. |
---|
| 493 | * |
---|
| 494 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
---|
| 495 | */ |
---|
| 496 | |
---|
[ffbeb6f] | 497 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
---|
[af16a7d2] | 498 | |
---|
| 499 | /* |
---|
| 500 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
| 501 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
| 502 | * number (0)? |
---|
| 503 | */ |
---|
| 504 | |
---|
[141e16d] | 505 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
---|
[af16a7d2] | 506 | |
---|
| 507 | /* |
---|
| 508 | * Should the saving of the floating point registers be deferred |
---|
| 509 | * until a context switch is made to another different floating point |
---|
| 510 | * task? |
---|
| 511 | * |
---|
| 512 | * If TRUE, then the floating point context will not be stored until |
---|
| 513 | * necessary. It will remain in the floating point registers and not |
---|
| 514 | * disturned until another floating point task is switched to. |
---|
| 515 | * |
---|
| 516 | * If FALSE, then the floating point context is saved when a floating |
---|
| 517 | * point task is switched out and restored when the next floating point |
---|
| 518 | * task is restored. The state of the floating point registers between |
---|
| 519 | * those two operations is not specified. |
---|
| 520 | * |
---|
| 521 | * If the floating point context does NOT have to be saved as part of |
---|
| 522 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
| 523 | * |
---|
| 524 | * Setting this flag to TRUE results in using a different algorithm |
---|
| 525 | * for deciding when to save and restore the floating point context. |
---|
| 526 | * The deferred FP switch algorithm minimizes the number of times |
---|
| 527 | * the FP context is saved and restored. The FP context is not saved |
---|
| 528 | * until a context switch is made to another, different FP task. |
---|
| 529 | * Thus in a system with only one FP task, the FP context will never |
---|
| 530 | * be saved or restored. |
---|
| 531 | * |
---|
| 532 | * Note, however that compilers may use floating point registers/ |
---|
| 533 | * instructions for optimization or they may save/restore FP registers |
---|
| 534 | * on the stack. You must not use deferred switching in these cases |
---|
| 535 | * and on the PowerPC attempting to do so will raise a "FP unavailable" |
---|
| 536 | * exception. |
---|
| 537 | */ |
---|
| 538 | /* |
---|
| 539 | * ACB Note: This could make debugging tricky.. |
---|
| 540 | */ |
---|
| 541 | |
---|
| 542 | /* conservative setting (FALSE); probably doesn't affect performance too much */ |
---|
| 543 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
---|
| 544 | |
---|
[84e6f15] | 545 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
---|
| 546 | |
---|
[af16a7d2] | 547 | /* |
---|
| 548 | * Processor defined structures required for cpukit/score. |
---|
| 549 | */ |
---|
| 550 | |
---|
| 551 | #ifndef ASM |
---|
| 552 | |
---|
| 553 | /* |
---|
| 554 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 555 | * to generate an "uninitialized" FP context. It is filled in by |
---|
| 556 | * _CPU_Initialize and copied into the task's FP context area during |
---|
| 557 | * _CPU_Context_Initialize. |
---|
| 558 | */ |
---|
| 559 | |
---|
| 560 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
---|
| 561 | |
---|
| 562 | #endif /* ndef ASM */ |
---|
| 563 | |
---|
| 564 | /* |
---|
| 565 | * This defines the number of levels and the mask used to pick those |
---|
| 566 | * bits out of a thread mode. |
---|
| 567 | */ |
---|
| 568 | |
---|
| 569 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
---|
| 570 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
---|
| 571 | |
---|
| 572 | /* |
---|
| 573 | * The size of the floating point context area. On some CPUs this |
---|
| 574 | * will not be a "sizeof" because the format of the floating point |
---|
| 575 | * area is not defined -- only the size is. This is usually on |
---|
| 576 | * CPUs with a "floating point save context" instruction. |
---|
| 577 | */ |
---|
| 578 | |
---|
| 579 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 580 | |
---|
| 581 | /* |
---|
| 582 | * (Optional) # of bytes for libmisc/stackchk to check |
---|
| 583 | * If not specifed, then it defaults to something reasonable |
---|
| 584 | * for most architectures. |
---|
| 585 | */ |
---|
| 586 | |
---|
[8bb9d41] | 587 | #define CPU_STACK_CHECK_PATTERN_INITIALIZER \ |
---|
| 588 | { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 589 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 590 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 591 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 592 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 593 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 594 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 595 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 } |
---|
[af16a7d2] | 596 | |
---|
| 597 | /* |
---|
| 598 | * Amount of extra stack (above minimum stack size) required by |
---|
| 599 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 600 | * system this thread must exist and be able to process all directives. |
---|
| 601 | */ |
---|
| 602 | |
---|
| 603 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 604 | |
---|
| 605 | /* |
---|
| 606 | * This is defined if the port has a special way to report the ISR nesting |
---|
| 607 | * level. Most ports maintain the variable _ISR_Nest_level. Note that |
---|
| 608 | * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
---|
| 609 | * being maintained (e.g. watchdog queues). |
---|
| 610 | */ |
---|
| 611 | |
---|
| 612 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 613 | |
---|
| 614 | /* |
---|
| 615 | * ISR handler macros |
---|
| 616 | */ |
---|
| 617 | |
---|
| 618 | /* |
---|
| 619 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 620 | * level is returned in _isr_cookie. |
---|
| 621 | */ |
---|
| 622 | |
---|
| 623 | #ifndef ASM |
---|
| 624 | |
---|
[408609f6] | 625 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
| 626 | { |
---|
| 627 | return ( level & MSR_EE ) != 0; |
---|
| 628 | } |
---|
| 629 | |
---|
[af16a7d2] | 630 | static inline uint32_t _CPU_ISR_Get_level( void ) |
---|
| 631 | { |
---|
| 632 | register unsigned int msr; |
---|
| 633 | _CPU_MSR_GET(msr); |
---|
| 634 | if (msr & MSR_EE) return 0; |
---|
| 635 | else return 1; |
---|
| 636 | } |
---|
| 637 | |
---|
| 638 | static inline void _CPU_ISR_Set_level( uint32_t level ) |
---|
| 639 | { |
---|
| 640 | register unsigned int msr; |
---|
| 641 | _CPU_MSR_GET(msr); |
---|
| 642 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
---|
| 643 | msr |= ppc_interrupt_get_disable_mask(); |
---|
| 644 | } |
---|
| 645 | else { |
---|
| 646 | msr &= ~ppc_interrupt_get_disable_mask(); |
---|
| 647 | } |
---|
| 648 | _CPU_MSR_SET(msr); |
---|
| 649 | } |
---|
| 650 | |
---|
| 651 | void BSP_panic(char *); |
---|
| 652 | |
---|
| 653 | /* Fatal Error manager macros */ |
---|
| 654 | |
---|
| 655 | /* |
---|
| 656 | * This routine copies _error into a known place -- typically a stack |
---|
| 657 | * location or a register, optionally disables interrupts, and |
---|
| 658 | * halts/stops the CPU. |
---|
| 659 | */ |
---|
| 660 | |
---|
| 661 | void _BSP_Fatal_error(unsigned int); |
---|
| 662 | |
---|
| 663 | #endif /* ASM */ |
---|
| 664 | |
---|
[f82752a4] | 665 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
[af16a7d2] | 666 | _BSP_Fatal_error(_error) |
---|
| 667 | |
---|
| 668 | /* end of Fatal Error manager macros */ |
---|
| 669 | |
---|
[b4f43549] | 670 | /* |
---|
[5961b4c7] | 671 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[b4f43549] | 672 | * that a "reasonable" small application should not have any problems. |
---|
| 673 | */ |
---|
| 674 | |
---|
| 675 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
---|
| 676 | |
---|
[f1738ed] | 677 | #define CPU_SIZEOF_POINTER 4 |
---|
| 678 | |
---|
[b4f43549] | 679 | /* |
---|
| 680 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 681 | * alignment does not take into account the requirements for the stack. |
---|
| 682 | */ |
---|
| 683 | |
---|
| 684 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 685 | |
---|
| 686 | /* |
---|
| 687 | * This number corresponds to the byte alignment requirement for the |
---|
| 688 | * heap handler. This alignment requirement may be stricter than that |
---|
| 689 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 690 | * common for the heap to follow the same alignment requirement as |
---|
| 691 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 692 | * then this should be set to CPU_ALIGNMENT. |
---|
| 693 | * |
---|
| 694 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 695 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 696 | */ |
---|
| 697 | |
---|
| 698 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 699 | |
---|
| 700 | /* |
---|
| 701 | * This number corresponds to the byte alignment requirement for memory |
---|
| 702 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 703 | * may be stricter than that for the data types alignment specified by |
---|
| 704 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 705 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 706 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 707 | * |
---|
| 708 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 709 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 710 | */ |
---|
| 711 | |
---|
| 712 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 713 | |
---|
| 714 | /* |
---|
| 715 | * This number corresponds to the byte alignment requirement for the |
---|
| 716 | * stack. This alignment requirement may be stricter than that for the |
---|
| 717 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 718 | * is strict enough for the stack, then this should be set to 0. |
---|
| 719 | * |
---|
| 720 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 721 | */ |
---|
| 722 | |
---|
| 723 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
---|
| 724 | |
---|
[d4214b0] | 725 | #ifndef ASM |
---|
| 726 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 727 | * It must be static because it is referenced indirectly. |
---|
| 728 | * |
---|
| 729 | * This version will work on any processor, but if there is a better |
---|
| 730 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 731 | * |
---|
| 732 | * swap least significant two bytes with 16-bit rotate |
---|
| 733 | * swap upper and lower 16-bits |
---|
| 734 | * swap most significant two bytes with 16-bit rotate |
---|
| 735 | * |
---|
| 736 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 737 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 738 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[5961b4c7] | 739 | * that interrupts would probably have to be disabled to ensure that |
---|
[d4214b0] | 740 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 741 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 742 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 743 | * will be fetched incorrectly. |
---|
| 744 | */ |
---|
[5bb38e15] | 745 | |
---|
[d4214b0] | 746 | static inline uint32_t CPU_swap_u32( |
---|
| 747 | uint32_t value |
---|
| 748 | ) |
---|
| 749 | { |
---|
| 750 | uint32_t swapped; |
---|
[5bb38e15] | 751 | |
---|
[3631c234] | 752 | __asm__ volatile("rlwimi %0,%1,8,24,31;" |
---|
[d4214b0] | 753 | "rlwimi %0,%1,24,16,23;" |
---|
| 754 | "rlwimi %0,%1,8,8,15;" |
---|
| 755 | "rlwimi %0,%1,24,0,7;" : |
---|
| 756 | "=&r" ((swapped)) : "r" ((value))); |
---|
| 757 | |
---|
| 758 | return( swapped ); |
---|
| 759 | } |
---|
| 760 | |
---|
| 761 | #define CPU_swap_u16( value ) \ |
---|
| 762 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 763 | |
---|
[24bf11e] | 764 | typedef uint32_t CPU_Counter_ticks; |
---|
| 765 | |
---|
| 766 | static inline CPU_Counter_ticks _CPU_Counter_read( void ) |
---|
| 767 | { |
---|
| 768 | CPU_Counter_ticks value; |
---|
| 769 | |
---|
[93f5adb] | 770 | #if defined(__PPC_CPU_E6500__) |
---|
[bb7bd148] | 771 | /* Use Alternate Time Base */ |
---|
| 772 | __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); |
---|
[24bf11e] | 773 | #else |
---|
[e2fcb7d] | 774 | __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); |
---|
[24bf11e] | 775 | #endif |
---|
| 776 | |
---|
| 777 | return value; |
---|
| 778 | } |
---|
| 779 | |
---|
| 780 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 781 | CPU_Counter_ticks second, |
---|
| 782 | CPU_Counter_ticks first |
---|
| 783 | ) |
---|
| 784 | { |
---|
| 785 | return second - first; |
---|
| 786 | } |
---|
| 787 | |
---|
[d4214b0] | 788 | #endif /* ASM */ |
---|
| 789 | |
---|
[58847845] | 790 | |
---|
[6b25a47] | 791 | #ifndef ASM |
---|
| 792 | /* Context handler macros */ |
---|
| 793 | |
---|
| 794 | /* |
---|
| 795 | * Initialize the context to a state suitable for starting a |
---|
| 796 | * task after a context restore operation. Generally, this |
---|
| 797 | * involves: |
---|
| 798 | * |
---|
| 799 | * - setting a starting address |
---|
| 800 | * - preparing the stack |
---|
| 801 | * - preparing the stack and frame pointers |
---|
| 802 | * - setting the proper interrupt level in the context |
---|
| 803 | * - initializing the floating point context |
---|
| 804 | * |
---|
| 805 | * This routine generally does not set any unnecessary register |
---|
| 806 | * in the context. The state of the "general data" registers is |
---|
| 807 | * undefined at task start time. |
---|
| 808 | */ |
---|
[d4214b0] | 809 | |
---|
[6b25a47] | 810 | void _CPU_Context_Initialize( |
---|
| 811 | Context_Control *the_context, |
---|
| 812 | uint32_t *stack_base, |
---|
| 813 | uint32_t size, |
---|
| 814 | uint32_t new_level, |
---|
| 815 | void *entry_point, |
---|
[022851a] | 816 | bool is_fp, |
---|
| 817 | void *tls_area |
---|
[6b25a47] | 818 | ); |
---|
| 819 | |
---|
| 820 | /* |
---|
| 821 | * This routine is responsible for somehow restarting the currently |
---|
| 822 | * executing task. If you are lucky, then all that is necessary |
---|
| 823 | * is restoring the context. Otherwise, there will need to be |
---|
| 824 | * a special assembly routine which does something special in this |
---|
| 825 | * case. Context_Restore should work most of the time. It will |
---|
| 826 | * not work if restarting self conflicts with the stack frame |
---|
| 827 | * assumptions of restoring a context. |
---|
| 828 | */ |
---|
| 829 | |
---|
| 830 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 831 | _CPU_Context_restore( (_the_context) ); |
---|
| 832 | |
---|
| 833 | /* |
---|
| 834 | * This routine initializes the FP context area passed to it to. |
---|
| 835 | * There are a few standard ways in which to initialize the |
---|
| 836 | * floating point context. The code included for this macro assumes |
---|
| 837 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 838 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 839 | * context passed to it. |
---|
| 840 | * |
---|
| 841 | * Other models include (1) not doing anything, and (2) putting |
---|
| 842 | * a "null FP status word" in the correct place in the FP context. |
---|
| 843 | */ |
---|
| 844 | |
---|
| 845 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
[2067679] | 846 | memset( *(_destination), 0, sizeof( **(_destination) ) ) |
---|
[6b25a47] | 847 | |
---|
| 848 | /* end of Context handler macros */ |
---|
| 849 | #endif /* ASM */ |
---|
| 850 | |
---|
[779939b2] | 851 | #ifndef ASM |
---|
| 852 | /* Bitfield handler macros */ |
---|
| 853 | |
---|
[987ea1a] | 854 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
---|
| 855 | |
---|
[779939b2] | 856 | /* |
---|
| 857 | * This routine sets _output to the bit number of the first bit |
---|
[f570b071] | 858 | * set in _value. _value is of CPU dependent type Priority_bit_map_Word. |
---|
[779939b2] | 859 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 860 | * least significant bits will be used. |
---|
| 861 | * |
---|
| 862 | * There are a number of variables in using a "find first bit" type |
---|
| 863 | * instruction. |
---|
| 864 | * |
---|
| 865 | * (1) What happens when run on a value of zero? |
---|
| 866 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 867 | * (3) The numbering may be zero or one based. |
---|
| 868 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 869 | * |
---|
| 870 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 871 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 872 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
| 873 | * which must logically operate together. Bits in the _value are |
---|
| 874 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 875 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 876 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
| 877 | * to properly range between the values returned by the "find first bit" |
---|
| 878 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 879 | * calculate the major and directly index into the minor table. |
---|
| 880 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 881 | * is the first bit found. |
---|
| 882 | * |
---|
| 883 | * This entire "find first bit" and mapping process depends heavily |
---|
| 884 | * on the manner in which a priority is broken into a major and minor |
---|
| 885 | * components with the major being the 4 MSB of a priority and minor |
---|
| 886 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 887 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 888 | * to the lowest priority. |
---|
| 889 | * |
---|
| 890 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 891 | * there are ways to make do without it. Here are a handful of ways |
---|
| 892 | * to implement this in software: |
---|
| 893 | * |
---|
| 894 | * - a series of 16 bit test instructions |
---|
| 895 | * - a "binary search using if's" |
---|
| 896 | * - _number = 0 |
---|
| 897 | * if _value > 0x00ff |
---|
| 898 | * _value >>=8 |
---|
| 899 | * _number = 8; |
---|
| 900 | * |
---|
| 901 | * if _value > 0x0000f |
---|
| 902 | * _value >=8 |
---|
| 903 | * _number += 4 |
---|
| 904 | * |
---|
| 905 | * _number += bit_set_table[ _value ] |
---|
| 906 | * |
---|
| 907 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 908 | * bit set |
---|
| 909 | */ |
---|
| 910 | |
---|
| 911 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 912 | { \ |
---|
[3631c234] | 913 | __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
---|
[779939b2] | 914 | "1" ((_value))); \ |
---|
[b04b76c6] | 915 | (_output) = (_output) - 16; \ |
---|
[779939b2] | 916 | } |
---|
| 917 | |
---|
| 918 | /* end of Bitfield handler macros */ |
---|
| 919 | |
---|
| 920 | /* |
---|
| 921 | * This routine builds the mask which corresponds to the bit fields |
---|
| 922 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 923 | * for that routine. |
---|
| 924 | */ |
---|
| 925 | |
---|
| 926 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
[b04b76c6] | 927 | ( 0x8000u >> (_bit_number) ) |
---|
[779939b2] | 928 | |
---|
| 929 | /* |
---|
| 930 | * This routine translates the bit numbers returned by |
---|
| 931 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 932 | * a major or minor component of a priority. See the discussion |
---|
| 933 | * for that routine. |
---|
| 934 | */ |
---|
| 935 | |
---|
| 936 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 937 | (_priority) |
---|
| 938 | |
---|
| 939 | /* end of Priority handler macros */ |
---|
| 940 | #endif /* ASM */ |
---|
| 941 | |
---|
[8773879] | 942 | /* functions */ |
---|
| 943 | |
---|
| 944 | #ifndef ASM |
---|
| 945 | |
---|
| 946 | /* |
---|
| 947 | * _CPU_Initialize |
---|
| 948 | * |
---|
| 949 | * This routine performs CPU dependent initialization. |
---|
| 950 | */ |
---|
| 951 | |
---|
[ef1be69] | 952 | void _CPU_Initialize(void); |
---|
[8773879] | 953 | |
---|
| 954 | /* |
---|
| 955 | * _CPU_ISR_install_vector |
---|
| 956 | * |
---|
| 957 | * This routine installs an interrupt vector. |
---|
| 958 | */ |
---|
| 959 | |
---|
| 960 | void _CPU_ISR_install_vector( |
---|
| 961 | uint32_t vector, |
---|
| 962 | proc_ptr new_handler, |
---|
| 963 | proc_ptr *old_handler |
---|
| 964 | ); |
---|
| 965 | |
---|
| 966 | /* |
---|
| 967 | * _CPU_Context_switch |
---|
| 968 | * |
---|
| 969 | * This routine switches from the run context to the heir context. |
---|
| 970 | */ |
---|
| 971 | |
---|
| 972 | void _CPU_Context_switch( |
---|
| 973 | Context_Control *run, |
---|
| 974 | Context_Control *heir |
---|
| 975 | ); |
---|
| 976 | |
---|
| 977 | /* |
---|
| 978 | * _CPU_Context_restore |
---|
| 979 | * |
---|
| 980 | * This routine is generallu used only to restart self in an |
---|
| 981 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 982 | * |
---|
| 983 | * NOTE: May be unnecessary to reload some registers. |
---|
| 984 | */ |
---|
| 985 | |
---|
| 986 | void _CPU_Context_restore( |
---|
| 987 | Context_Control *new_context |
---|
[143696a] | 988 | ) RTEMS_NO_RETURN; |
---|
[8773879] | 989 | |
---|
| 990 | /* |
---|
| 991 | * _CPU_Context_save_fp |
---|
| 992 | * |
---|
| 993 | * This routine saves the floating point context passed to it. |
---|
| 994 | */ |
---|
| 995 | |
---|
| 996 | void _CPU_Context_save_fp( |
---|
[b60dc893] | 997 | Context_Control_fp **fp_context_ptr |
---|
[8773879] | 998 | ); |
---|
| 999 | |
---|
| 1000 | /* |
---|
| 1001 | * _CPU_Context_restore_fp |
---|
| 1002 | * |
---|
| 1003 | * This routine restores the floating point context passed to it. |
---|
| 1004 | */ |
---|
| 1005 | |
---|
| 1006 | void _CPU_Context_restore_fp( |
---|
[b60dc893] | 1007 | Context_Control_fp **fp_context_ptr |
---|
[8773879] | 1008 | ); |
---|
| 1009 | |
---|
[39993d6] | 1010 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
---|
| 1011 | |
---|
| 1012 | void _CPU_Context_validate( uintptr_t pattern ); |
---|
| 1013 | |
---|
[ffbeb6f] | 1014 | #ifdef RTEMS_SMP |
---|
[53e008b] | 1015 | uint32_t _CPU_SMP_Initialize( void ); |
---|
| 1016 | |
---|
| 1017 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
---|
| 1018 | |
---|
| 1019 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
---|
[4627fcd] | 1020 | |
---|
[c34f94f7] | 1021 | void _CPU_SMP_Prepare_start_multitasking( void ); |
---|
| 1022 | |
---|
[47d60134] | 1023 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
[39e51758] | 1024 | { |
---|
| 1025 | uint32_t pir; |
---|
| 1026 | |
---|
| 1027 | /* Use Book E Processor ID Register (PIR) */ |
---|
[47d60134] | 1028 | __asm__ volatile ( |
---|
[39e51758] | 1029 | "mfspr %[pir], 286" |
---|
| 1030 | : [pir] "=&r" (pir) |
---|
| 1031 | ); |
---|
| 1032 | |
---|
| 1033 | return pir; |
---|
| 1034 | } |
---|
| 1035 | |
---|
[ca63ae2] | 1036 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
[39e51758] | 1037 | |
---|
[07f6e419] | 1038 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
[ffbeb6f] | 1039 | { |
---|
| 1040 | __asm__ volatile ( "" : : : "memory" ); |
---|
| 1041 | } |
---|
| 1042 | |
---|
[f7740e97] | 1043 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
[ffbeb6f] | 1044 | { |
---|
| 1045 | __asm__ volatile ( "" : : : "memory" ); |
---|
| 1046 | } |
---|
| 1047 | #endif |
---|
| 1048 | |
---|
[d2202ac] | 1049 | typedef struct { |
---|
| 1050 | uint32_t EXC_SRR0; |
---|
| 1051 | uint32_t EXC_SRR1; |
---|
| 1052 | uint32_t _EXC_number; |
---|
| 1053 | uint32_t EXC_CR; |
---|
| 1054 | uint32_t EXC_CTR; |
---|
| 1055 | uint32_t EXC_XER; |
---|
| 1056 | uint32_t EXC_LR; |
---|
| 1057 | #ifdef __SPE__ |
---|
| 1058 | uint32_t EXC_SPEFSCR; |
---|
| 1059 | uint64_t EXC_ACC; |
---|
| 1060 | #endif |
---|
| 1061 | PPC_GPR_TYPE GPR0; |
---|
| 1062 | PPC_GPR_TYPE GPR1; |
---|
| 1063 | PPC_GPR_TYPE GPR2; |
---|
| 1064 | PPC_GPR_TYPE GPR3; |
---|
| 1065 | PPC_GPR_TYPE GPR4; |
---|
| 1066 | PPC_GPR_TYPE GPR5; |
---|
| 1067 | PPC_GPR_TYPE GPR6; |
---|
| 1068 | PPC_GPR_TYPE GPR7; |
---|
| 1069 | PPC_GPR_TYPE GPR8; |
---|
| 1070 | PPC_GPR_TYPE GPR9; |
---|
| 1071 | PPC_GPR_TYPE GPR10; |
---|
| 1072 | PPC_GPR_TYPE GPR11; |
---|
| 1073 | PPC_GPR_TYPE GPR12; |
---|
| 1074 | PPC_GPR_TYPE GPR13; |
---|
| 1075 | PPC_GPR_TYPE GPR14; |
---|
| 1076 | PPC_GPR_TYPE GPR15; |
---|
| 1077 | PPC_GPR_TYPE GPR16; |
---|
| 1078 | PPC_GPR_TYPE GPR17; |
---|
| 1079 | PPC_GPR_TYPE GPR18; |
---|
| 1080 | PPC_GPR_TYPE GPR19; |
---|
| 1081 | PPC_GPR_TYPE GPR20; |
---|
| 1082 | PPC_GPR_TYPE GPR21; |
---|
| 1083 | PPC_GPR_TYPE GPR22; |
---|
| 1084 | PPC_GPR_TYPE GPR23; |
---|
| 1085 | PPC_GPR_TYPE GPR24; |
---|
| 1086 | PPC_GPR_TYPE GPR25; |
---|
| 1087 | PPC_GPR_TYPE GPR26; |
---|
| 1088 | PPC_GPR_TYPE GPR27; |
---|
| 1089 | PPC_GPR_TYPE GPR28; |
---|
| 1090 | PPC_GPR_TYPE GPR29; |
---|
| 1091 | PPC_GPR_TYPE GPR30; |
---|
| 1092 | PPC_GPR_TYPE GPR31; |
---|
[3e2647a7] | 1093 | #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU) |
---|
| 1094 | uint32_t reserved_for_alignment; |
---|
| 1095 | #endif |
---|
| 1096 | #ifdef PPC_MULTILIB_ALTIVEC |
---|
| 1097 | uint32_t VRSAVE; |
---|
[60d39b66] | 1098 | |
---|
| 1099 | /* This field must take stvewx/lvewx requirements into account */ |
---|
| 1100 | uint32_t VSCR; |
---|
| 1101 | |
---|
[3e2647a7] | 1102 | uint8_t V0[16]; |
---|
| 1103 | uint8_t V1[16]; |
---|
| 1104 | uint8_t V2[16]; |
---|
| 1105 | uint8_t V3[16]; |
---|
| 1106 | uint8_t V4[16]; |
---|
| 1107 | uint8_t V5[16]; |
---|
| 1108 | uint8_t V6[16]; |
---|
| 1109 | uint8_t V7[16]; |
---|
| 1110 | uint8_t V8[16]; |
---|
| 1111 | uint8_t V9[16]; |
---|
| 1112 | uint8_t V10[16]; |
---|
| 1113 | uint8_t V11[16]; |
---|
| 1114 | uint8_t V12[16]; |
---|
| 1115 | uint8_t V13[16]; |
---|
| 1116 | uint8_t V14[16]; |
---|
| 1117 | uint8_t V15[16]; |
---|
| 1118 | uint8_t V16[16]; |
---|
| 1119 | uint8_t V17[16]; |
---|
| 1120 | uint8_t V18[16]; |
---|
| 1121 | uint8_t V19[16]; |
---|
| 1122 | uint8_t V20[16]; |
---|
| 1123 | uint8_t V21[16]; |
---|
| 1124 | uint8_t V22[16]; |
---|
| 1125 | uint8_t V23[16]; |
---|
| 1126 | uint8_t V24[16]; |
---|
| 1127 | uint8_t V25[16]; |
---|
| 1128 | uint8_t V26[16]; |
---|
| 1129 | uint8_t V27[16]; |
---|
| 1130 | uint8_t V28[16]; |
---|
| 1131 | uint8_t V29[16]; |
---|
| 1132 | uint8_t V30[16]; |
---|
| 1133 | uint8_t V31[16]; |
---|
| 1134 | #endif |
---|
| 1135 | #ifdef PPC_MULTILIB_FPU |
---|
| 1136 | double F0; |
---|
| 1137 | double F1; |
---|
| 1138 | double F2; |
---|
| 1139 | double F3; |
---|
| 1140 | double F4; |
---|
| 1141 | double F5; |
---|
| 1142 | double F6; |
---|
| 1143 | double F7; |
---|
| 1144 | double F8; |
---|
| 1145 | double F9; |
---|
| 1146 | double F10; |
---|
| 1147 | double F11; |
---|
| 1148 | double F12; |
---|
| 1149 | double F13; |
---|
| 1150 | double F14; |
---|
| 1151 | double F15; |
---|
| 1152 | double F16; |
---|
| 1153 | double F17; |
---|
| 1154 | double F18; |
---|
| 1155 | double F19; |
---|
| 1156 | double F20; |
---|
| 1157 | double F21; |
---|
| 1158 | double F22; |
---|
| 1159 | double F23; |
---|
| 1160 | double F24; |
---|
| 1161 | double F25; |
---|
| 1162 | double F26; |
---|
| 1163 | double F27; |
---|
| 1164 | double F28; |
---|
| 1165 | double F29; |
---|
| 1166 | double F30; |
---|
| 1167 | double F31; |
---|
| 1168 | uint64_t FPSCR; |
---|
| 1169 | #endif |
---|
[d2202ac] | 1170 | } CPU_Exception_frame; |
---|
| 1171 | |
---|
[c48cf0bd] | 1172 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
[815994f] | 1173 | |
---|
[6c28773e] | 1174 | /* |
---|
| 1175 | * _CPU_Initialize_altivec() |
---|
| 1176 | * |
---|
| 1177 | * Global altivec-related initialization. |
---|
| 1178 | */ |
---|
| 1179 | void |
---|
| 1180 | _CPU_Initialize_altivec(void); |
---|
| 1181 | |
---|
| 1182 | /* |
---|
| 1183 | * _CPU_Context_switch_altivec |
---|
| 1184 | * |
---|
| 1185 | * This routine switches the altivec contexts passed to it. |
---|
| 1186 | */ |
---|
| 1187 | |
---|
| 1188 | void |
---|
| 1189 | _CPU_Context_switch_altivec( |
---|
[56435e6] | 1190 | ppc_context *from, |
---|
| 1191 | ppc_context *to |
---|
[6c28773e] | 1192 | ); |
---|
| 1193 | |
---|
| 1194 | /* |
---|
| 1195 | * _CPU_Context_restore_altivec |
---|
| 1196 | * |
---|
| 1197 | * This routine restores the altivec context passed to it. |
---|
| 1198 | */ |
---|
| 1199 | |
---|
| 1200 | void |
---|
| 1201 | _CPU_Context_restore_altivec( |
---|
[56435e6] | 1202 | ppc_context *ctxt |
---|
[6c28773e] | 1203 | ); |
---|
| 1204 | |
---|
| 1205 | /* |
---|
| 1206 | * _CPU_Context_initialize_altivec |
---|
| 1207 | * |
---|
| 1208 | * This routine initializes the altivec context passed to it. |
---|
| 1209 | */ |
---|
| 1210 | |
---|
| 1211 | void |
---|
| 1212 | _CPU_Context_initialize_altivec( |
---|
[56435e6] | 1213 | ppc_context *ctxt |
---|
[6c28773e] | 1214 | ); |
---|
| 1215 | |
---|
[8773879] | 1216 | void _CPU_Fatal_error( |
---|
| 1217 | uint32_t _error |
---|
| 1218 | ); |
---|
| 1219 | |
---|
| 1220 | #endif /* ASM */ |
---|
| 1221 | |
---|
[af16a7d2] | 1222 | #ifdef __cplusplus |
---|
| 1223 | } |
---|
| 1224 | #endif |
---|
| 1225 | |
---|
[6b25a47] | 1226 | #endif /* _RTEMS_SCORE_CPU_H */ |
---|