source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ cd228d76

4.104.114.84.95
Last change on this file since cd228d76 was cd228d76, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 20, 2003 at 10:11:46 PM

2003-02-20 Till Straumann <strauman@…>

PR 349/bsps

  • rtems/powerpc/registers.h: Add definitions for HID1 and DABR SPRs.
  • Property mode set to 100644
File size: 9.0 KB
Line 
1/*
2 * This file contains some powerpc MSR and registers access definitions.
3 *
4 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
5 *                     Canon Centre Recherche France.
6 *
7 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited
9 *
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  $Id$
16 */
17
18#ifndef __rtems_powerpc_registers_h
19#define __rtems_powerpc_registers_h
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/* Bit encodings for Machine State Register (MSR) */
26#define MSR_POW         (1<<18)         /* Enable Power Management */
27#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
28#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
29#define MSR_EE          (1<<15)         /* External Interrupt enable */
30#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
31#define MSR_FP          (1<<13)         /* Floating Point enable */
32#define MSR_ME          (1<<12)         /* Machine Check enable */
33#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
34#define MSR_SE          (1<<10)         /* Single Step */
35#define MSR_BE          (1<<9)          /* Branch Trace */
36#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
37#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
38#define MSR_IR          (1<<5)          /* Instruction MMU enable */
39#define MSR_DR          (1<<4)          /* Data MMU enable */
40#define MSR_RI          (1<<1)          /* Recoverable Exception */
41#define MSR_LE          (1<<0)          /* Little-Endian enable */
42
43#define MSR_            MSR_ME|MSR_RI
44#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
45#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
46
47/* Bit encodings for Hardware Implementation Register (HID0)
48   on PowerPC 603, 604, etc. processors (not 601). */
49#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
50#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
51#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
52#define HID0_SBCLK      (1<<27)
53#define HID0_EICE       (1<<26)
54#define HID0_ECLK       (1<<25)
55#define HID0_PAR        (1<<24)
56#define HID0_DOZE       (1<<23)
57#define HID0_NAP        (1<<22)
58#define HID0_SLEEP      (1<<21)
59#define HID0_DPM        (1<<20)
60#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
61#define HID0_DCE        (1<<14)         /* Data Cache Enable */
62#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
63#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
64#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
65#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
66#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
67#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
68#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
69#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
70
71/* fpscr settings */
72#define FPSCR_FX        (1<<31)
73#define FPSCR_FEX       (1<<30)
74
75#define _MACH_prep     1
76#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
77#define _MACH_chrp     4 /* chrp machine */
78#define _MACH_mbx      8 /* Motorola MBX board */
79#define _MACH_apus    16 /* amiga with phase5 powerup */
80#define _MACH_fads    32 /* Motorola FADS board */
81
82/* see residual.h for these */
83#define _PREP_Motorola 0x01  /* motorola prep */
84#define _PREP_Firm     0x02  /* firmworks prep */
85#define _PREP_IBM      0x00  /* ibm prep */
86#define _PREP_Bull     0x03  /* bull prep */
87
88/* these are arbitrary */
89#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
90#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
91
92#define _GLOBAL(n)\
93        .globl n;\
94n:
95
96#define TBRU    269     /* Time base Upper/Lower (Reading) */
97#define TBRL    268
98#define TBWU    284     /* Time base Upper/Lower (Writing) */
99#define TBWL    285
100#define XER     1
101#define LR      8
102#define CTR     9
103#define HID0    1008    /* Hardware Implementation */
104#define HID1    1009    /* Hardware Implementation */
105#define DABR    1013    /* Data Access Breakpoint  */
106#define PVR     287     /* Processor Version */
107#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
108#define IBAT0L  529
109#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
110#define IBAT1L  531
111#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
112#define IBAT2L  533
113#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
114#define IBAT3L  535
115#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
116#define DBAT0L  537
117#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
118#define DBAT1L  539
119#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
120#define DBAT2L  541
121#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
122#define DBAT3L  543
123#define DMISS   976     /* TLB Lookup/Refresh registers */
124#define DCMP    977
125#define HASH1   978
126#define HASH2   979
127#define IMISS   980
128#define ICMP    981
129#define RPA     982
130#define SDR1    25      /* MMU hash base register */
131#define DAR     19      /* Data Address Register */
132#define SPR0    272     /* Supervisor Private Registers */
133#define SPRG0   272
134#define SPR1    273
135#define SPRG1   273
136#define SPR2    274
137#define SPRG2   274
138#define SPR3    275
139#define SPRG3   275
140#define DSISR   18
141#define SRR0    26      /* Saved Registers (exception) */
142#define SRR1    27
143#define IABR    1010    /* Instruction Address Breakpoint */
144#define DEC     22      /* Decrementer */
145#define EAR     282     /* External Address Register */
146#define L2CR    1017    /* PPC 750 L2 control register */
147
148#define THRM1   1020
149#define THRM2   1021
150#define THRM3   1022
151#define THRM1_TIN 0x1
152#define THRM1_TIV 0x2
153#define THRM1_THRES (0x7f<<2)
154#define THRM1_TID (1<<29)
155#define THRM1_TIE (1<<30)
156#define THRM1_V   (1<<31)
157#define THRM3_E   (1<<31)
158
159/* Segment Registers */
160#define SR0     0
161#define SR1     1
162#define SR2     2
163#define SR3     3
164#define SR4     4
165#define SR5     5
166#define SR6     6
167#define SR7     7
168#define SR8     8
169#define SR9     9
170#define SR10    10
171#define SR11    11
172#define SR12    12
173#define SR13    13
174#define SR14    14
175#define SR15    15
176
177#ifndef ASM
178/*
179 *  Routines to access the time base register
180 */
181
182static inline unsigned long long PPC_Get_timebase_register( void )
183{
184  unsigned long tbr_low;
185  unsigned long tbr_high;
186  unsigned long tbr_high_old;
187  unsigned long long tbr;
188
189  do {
190    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
191    asm volatile( "mftb  %0" : "=r" (tbr_low));
192    asm volatile( "mftbu %0" : "=r" (tbr_high));
193  } while ( tbr_high_old != tbr_high );
194
195  tbr = tbr_high;
196  tbr <<= 32;
197  tbr |= tbr_low;
198  return tbr;
199}
200
201static inline  void PPC_Set_timebase_register (unsigned long long tbr)
202{
203  unsigned long tbr_low;
204  unsigned long tbr_high;
205
206  tbr_low = (tbr & 0xffffffff) ;
207  tbr_high = (tbr >> 32) & 0xffffffff;
208  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
209  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
210 
211}
212#endif
213
214#define _CPU_MSR_GET( _msr_value ) \
215  do { \
216    _msr_value = 0; \
217    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
218  } while (0)
219
220#define _CPU_MSR_SET( _msr_value ) \
221{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
222
223#define _CPU_ISR_Disable( _isr_cookie ) \
224  { register unsigned int _disable_mask = MSR_EE; \
225    _isr_cookie = 0; \
226    asm volatile ( \
227        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
228        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
229        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
230        ); \
231  }
232
233
234/*
235 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
236 *  This indicates the end of an RTEMS critical section.  The parameter
237 *  _isr_cookie is not modified.
238 */
239
240#define _CPU_ISR_Enable( _isr_cookie )  \
241  { \
242     asm volatile ( "mtmsr %0" : \
243                   "=r" ((_isr_cookie)) : \
244                   "0" ((_isr_cookie))); \
245  }
246
247/*
248 *  This temporarily restores the interrupt to _isr_cookie before immediately
249 *  disabling them again.  This is used to divide long RTEMS critical
250 *  sections into two or more parts.  The parameter _isr_cookie is not
251 *  modified.
252 *
253 *  NOTE:  The version being used is not very optimized but it does
254 *         not trip a problem in gcc where the disable mask does not
255 *         get loaded.  Check this for future (post 10/97 gcc versions.
256 */
257
258#define _CPU_ISR_Flash( _isr_cookie ) \
259  { register unsigned int _disable_mask = MSR_EE; \
260    asm volatile ( \
261      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
262      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
263      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
264    ); \
265  }
266
267
268/* end of ISR handler macros */
269
270/*
271 *  Simple spin delay in microsecond units for device drivers.
272 *  This is very dependent on the clock speed of the target.
273 */
274
275#define CPU_Get_timebase_low( _value ) \
276    asm volatile( "mftb  %0" : "=r" (_value) )
277
278#define rtems_bsp_delay( _microseconds ) \
279  do { \
280    unsigned32 start, ticks, now; \
281    CPU_Get_timebase_low( start ) ; \
282    ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
283    do \
284      CPU_Get_timebase_low( now ) ; \
285    while (now - start < ticks); \
286  } while (0)
287
288#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
289  do { \
290    unsigned32 start, now; \
291    CPU_Get_timebase_low( start ); \
292    do \
293      CPU_Get_timebase_low( now ); \
294    while (now - start < (_cycles)); \
295  } while (0)
296
297#define PPC_Set_decrementer( _clicks ) \
298  do { \
299    asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
300  } while (0)
301
302#define PPC_Get_decrementer( _clicks ) \
303    asm volatile( "mfdec  %0" : "=r" (_clicks) )
304
305#ifdef __cplusplus
306}
307#endif
308
309#endif /* __rtems_powerpc_registers_h */
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