source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ caa12270

5
Last change on this file since caa12270 was caa12270, checked in by Sebastian Huber <sebastian.huber@…>, on 07/31/17 at 13:08:06

powerpc: Add register defines

Update #3082.
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1/**
2 * @file
3 *
4 * @brief PowerPc MSR and Registers Access Definitions
5 *
6 * This file contains some powerpc MSR and registers access definitions.
7 */
8
9/*
10 * COPYRIGHT (C) 1999  Eric Valette (valette@crf.canon.fr)
11 *                     Canon Centre Recherche France.
12 *
13 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
14 *  Surrey Satellite Technology Limited
15 *
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *  http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef _RTEMS_POWERPC_REGISTERS_H
23#define _RTEMS_POWERPC_REGISTERS_H
24
25/* Bit encodings for Machine State Register (MSR) */
26#define MSR_CM          (1<<31)         /* Computation mode */
27#define MSR_GS          (1<<28)         /* Guest state */
28#define MSR_UCLE        (1<<26)         /* User-mode cache lock enable (e500) */
29#define MSR_VE          (1<<25)         /* Alti-Vec enable (7400+) */
30#define MSR_SPE         (1<<25)         /* SPE enable (e500) */
31#define MSR_AP          (1<<25)         /* Auxiliary processor available */
32#define MSR_APE         (1<<19)         /* APU exception enable */
33#define MSR_POW         (1<<18)         /* Enable Power Management */
34#define MSR_WE          (1<<18)         /* Wait state enable (e500, 4xx) */
35#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
36#define MSR_CE          (1<<17)         /* BookE critical interrupt */
37#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
38#define MSR_EE          (1<<15)         /* External Interrupt enable */
39#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
40#define MSR_FP          (1<<13)         /* Floating Point enable */
41#define MSR_ME          (1<<12)         /* Machine Check enable */
42#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
43#define MSR_SE          (1<<10)         /* Single Step */
44#define MSR_UBLE        (1<<10)         /* User-mode BTB lock enable (e500) */
45#define MSR_DWE         (1<<10)         /* Debug wait enable (4xx) */
46#define MSR_BE          (1<<9)          /* Branch Trace */
47#define MSR_DE          (1<<9)          /* BookE debug exception */
48#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
49#define MSR_E300_CE     (1<<7)          /* e300 critical interrupt */
50#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
51#define MSR_IR          (1<<5)          /* Instruction MMU enable */
52#define MSR_DR          (1<<4)          /* Data MMU enable */
53#define MSR_IS          (1<<5)          /* Instruction address space */
54#define MSR_DS          (1<<4)          /* Data address space */
55#define MSR_PMM         (1<<2)          /* Performance monitor mark */
56#define MSR_RI          (1<<1)          /* Recoverable Exception */
57#define MSR_LE          (1<<0)          /* Little-Endian enable */
58
59/* Bit encodings for Hardware Implementation Register (HID0)
60   on PowerPC 603, 604, etc. processors (not 601). */
61
62/* WARNING: HID0/HID1 are *truely* implementation dependent!
63 *          you *cannot* rely on the same bits to be present,
64 *          at the same place or even in the same register
65 *          on different CPU familys.
66 *          E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
67 *          on the 7450s. IFFT is XBSEN on 7450 and so on...
68 */
69#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
70#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
71#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
72#define HID0_SBCLK      (1<<27)
73#define HID0_TBEN       (1<<26)         /* 7455:this bit must be set
74                                         * and TBEN signal must be asserted
75                                         * to enable the time base and
76                                         * decrementer.
77                                         */
78#define HID0_EICE       (1<<26)
79#define HID0_ECLK       (1<<25)
80#define HID0_PAR        (1<<24)
81#define HID0_DOZE       (1<<23)
82/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !!          */
83#define HID0_7455_HIGH_BAT_EN (1<<23)
84
85#define HID0_NAP        (1<<22)
86#define HID0_SLEEP      (1<<21)
87#define HID0_DPM        (1<<20)
88#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
89#define HID0_DCE        (1<<14)         /* Data Cache Enable */
90#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
91#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
92#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
93#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
94/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
95#define HID0_7455_XBSEN       (1<<8)
96#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
97#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
98/* S.K. Feng 10/03, added for MPC7455 */
99#define HID0_LRSTK      (1<<4)          /* Link register stack enable (7455) */
100#define HID0_FOLD       (1<<3)          /* Branch folding enable (7455) */
101
102#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
103#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
104
105/* fpscr settings */
106#define FPSCR_FX        (1<<31)
107#define FPSCR_FEX       (1<<30)
108
109#define _MACH_prep     1
110#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
111#define _MACH_chrp     4 /* chrp machine */
112#define _MACH_mbx      8 /* Motorola MBX board */
113#define _MACH_apus    16 /* amiga with phase5 powerup */
114#define _MACH_fads    32 /* Motorola FADS board */
115
116/* see residual.h for these */
117#define _PREP_Motorola 0x01  /* motorola prep */
118#define _PREP_Firm     0x02  /* firmworks prep */
119#define _PREP_IBM      0x00  /* ibm prep */
120#define _PREP_Bull     0x03  /* bull prep */
121
122/* these are arbitrary */
123#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
124#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
125
126#define _GLOBAL(n)\
127        .globl n;\
128n:
129
130#define TBRU    269     /* Time base Upper/Lower (Reading) */
131#define TBRL    268
132#define TBWU    285     /* Time base Upper/Lower (Writing) */
133#define TBWL    284
134#define PPC_XER 1
135#define PPC_LR  8
136#define PPC_CTR 9
137#define HID0    1008    /* Hardware Implementation 0 */
138#define HID1    1009    /* Hardware Implementation 1 */
139#define HID2    1011    /* Hardware Implementation 2 */
140#define DABR    1013    /* Data Access Breakpoint  */
141#define PPC_PVR 287     /* Processor Version */
142#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
143#define IBAT0L  529
144#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
145#define IBAT1L  531
146#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
147#define IBAT2L  533
148#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
149#define IBAT3L  535
150
151/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
152#define IBAT4U  560     /* Instruction BAT #4 Upper/Lower */
153#define IBAT4L  561
154#define IBAT5U  562     /* Instruction BAT #5 Upper/Lower */
155#define IBAT5L  563
156#define IBAT6U  564     /* Instruction BAT #6 Upper/Lower */
157#define IBAT6L  565
158#define IBAT7U  566     /* Instruction BAT #7 Upper/Lower */
159#define IBAT7L  567
160
161#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
162#define DBAT0L  537
163#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
164#define DBAT1L  539
165#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
166#define DBAT2L  541
167#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
168#define DBAT3L  543
169
170/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
171#define DBAT4U  568     /* Instruction BAT #4 Upper/Lower */
172#define DBAT4L  569
173#define DBAT5U  570     /* Instruction BAT #5 Upper/Lower */
174#define DBAT5L  571
175#define DBAT6U  572     /* Instruction BAT #6 Upper/Lower */
176#define DBAT6L  573
177#define DBAT7U  574     /* Instruction BAT #7 Upper/Lower */
178#define DBAT7L  575
179
180#define DMISS   976     /* TLB Lookup/Refresh registers */
181#define DCMP    977
182#define HASH1   978
183#define HASH2   979
184#define IMISS   980
185#define ICMP    981
186#define PPC_RPA 982
187#define SDR1    25      /* MMU hash base register */
188#define PPC_DAR 19      /* Data Address Register */
189#define DEAR_BOOKE 61
190#define DEAR_405 981
191#define SPR0    272     /* Supervisor Private Registers */
192#define SPRG0   272
193#define SPR1    273
194#define SPRG1   273
195#define SPR2    274
196#define SPRG2   274
197#define SPR3    275
198#define SPRG3   275
199#define SPRG4   276
200#define SPRG5   277
201#define SPRG6   278
202#define SPRG7   279
203#define USPRG0  256
204#define DSISR   18
205#define SRR0    26      /* Saved Registers (exception) */
206#define SRR1    27
207#define IABR    1010    /* Instruction Address Breakpoint */
208#define PPC_DEC 22      /* Decrementer */
209#define PPC_EAR 282     /* External Address Register */
210
211#define MSSCR0   1014   /* Memory Subsystem Control Register */
212
213#define L2CR    1017    /* PPC 750 and 74xx L2 control register */
214
215#define L2CR_L2E   (1<<31)      /* enable */
216#define L2CR_L2I   (1<<21)      /* global invalidate */
217
218/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
219/* Oddly, the following L2CR bit defintions in 745x
220 * is different from that of 7400 and 7410.
221 * Though not used in 7400 and 7410, it is appeded with _745x just
222 * to be clarified.
223 */
224#define L2CR_L2IO_745x  0x100000  /* (1<<20) L2 Instruction-Only  */
225#define L2CR_L2DO_745x  0x10000   /* (1<<16) L2 Data-Only */
226#define L2CR_LOCK_745x  (L2CR_L2IO_745x|L2CR_L2DO_745x)
227#define L2CR_L3OH0      0x00080000 /* 12:L3 output hold 0 */
228
229#define L3CR    1018    /* PPC 7450/7455 L3 control register */
230#define L3CR_L3IO_745x  0x400000  /* (1<<22) L3 Instruction-Only */
231#define L3CR_L3DO_745x  0x40      /* (1<<6) L3 Data-Only */
232
233#define L3CR_LOCK_745x  (L3CR_L3IO_745x|L3CR_L3DO_745x)
234
235#define   L3CR_RESERVED           0x0438003a /* Reserved bits in L3CR */
236#define   L3CR_L3E                0x80000000 /* 0: L3 enable */
237#define   L3CR_L3PE               0x40000000 /* 1: L3 data parity checking enable */
238#define   L3CR_L3APE              0x20000000 /* 2: L3 address parity checking enable */
239#define   L3CR_L3SIZ              0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
240#define    L3SIZ_1M               0x00000000
241#define    L3SIZ_2M               0x10000000
242#define   L3CR_L3CLKEN            0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
243#define   L3CR_L3CLK              0x03800000 /* 6-8: L3 clock ratio */
244#define    L3CLK_60               0x00000000 /* core clock / 6   */
245#define    L3CLK_20               0x01000000 /*            / 2   */
246#define    L3CLK_25               0x01800000 /*            / 2.5 */
247#define    L3CLK_30               0x02000000 /*            / 3   */
248#define    L3CLK_35               0x02800000 /*            / 3.5 */
249#define    L3CLK_40               0x03000000 /*            / 4   */
250#define    L3CLK_50               0x03800000 /*            / 5   */
251#define   L3CR_L3IO               0x00400000 /* 9: L3 instruction-only mode */
252#define   L3CR_L3SPO              0x00040000 /* 13: L3 sample point override */
253#define   L3CR_L3CKSP             0x00030000 /* 14-15: L3 clock sample point */
254#define    L3CKSP_2               0x00000000 /* 2 clocks */
255#define    L3CKSP_3               0x00010000 /* 3 clocks */
256#define    L3CKSP_4               0x00020000 /* 4 clocks */
257#define    L3CKSP_5               0x00030000 /* 5 clocks */
258#define   L3CR_L3PSP              0x0000e000 /* 16-18: L3 P-clock sample point */
259#define    L3PSP_0                0x00000000 /* 0 clocks */
260#define    L3PSP_1                0x00002000 /* 1 clocks */
261#define    L3PSP_2                0x00004000 /* 2 clocks */
262#define    L3PSP_3                0x00006000 /* 3 clocks */
263#define    L3PSP_4                0x00008000 /* 4 clocks */
264#define    L3PSP_5                0x0000a000 /* 5 clocks */
265#define   L3CR_L3REP              0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
266#define   L3CR_L3HWF              0x00000800 /* 20: L3 hardware flush */
267#define   L3CR_L3I                0x00000400 /* 21: L3 global invaregisters.h.orig
268lidate */
269#define   L3CR_L3RT               0x00000300 /* 22-23: L3 SRAM type */
270#define    L3RT_MSUG2_DDR         0x00000000 /* MSUG2 DDR SRAM */
271#define    L3RT_PIPELINE_LATE     0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
272#define    L3RT_PB2_SRAM          0x00000300 /* PB2 SRAM */
273#define   L3CR_L3NIRCA            0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
274#define   L3CR_L3DO               0x00000040 /* 25: L3 data-only mode */
275#define   L3CR_PMEN               0x00000004 /* 29: Private memory enable */
276#define   L3CR_PMSIZ              0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
277
278#define THRM1   1020
279#define THRM2   1021
280#define THRM3   1022
281#define THRM1_TIN (1<<(31-0))
282#define THRM1_TIV (1<<(31-1))
283#define THRM1_THRES (0x7f<<(31-8))
284#define THRM1_TID (1<<(31-29))
285#define THRM1_TIE (1<<(31-30))
286#define THRM1_V   (1<<(31-31))
287#define THRM3_SITV (0x1fff << (31-30))
288#define THRM3_E   (1<<(31-31))
289
290/* Segment Registers */
291#define PPC_SR0 0
292#define PPC_SR1 1
293#define PPC_SR2 2
294#define PPC_SR3 3
295#define PPC_SR4 4
296#define PPC_SR5 5
297#define PPC_SR6 6
298#define PPC_SR7 7
299#define PPC_SR8 8
300#define PPC_SR9 9
301#define PPC_SR10        10
302#define PPC_SR11        11
303#define PPC_SR12        12
304#define PPC_SR13        13
305#define PPC_SR14        14
306#define PPC_SR15        15
307
308#define BOOKE_DECAR     54
309
310#define PPC405_MCSR     0x23C
311#define PPC405_ESR      0x3D4
312#define PPC405_DEAR     0x3D5
313#define BOOKE_DEAR      61
314
315#define PPC405_TSR      0x3D8
316#define BOOKE_TSR       336
317#define BOOKE_TSR_ENW           (1<<31)
318#define BOOKE_TSR_WIS           (1<<30)
319#define BOOKE_TSR_DIS           (1<<27)
320#define BOOKE_TSR_FIS           (1<<26)
321
322#define PPC405_TCR      0x3DA
323#define BOOKE_TCR       340
324#define BOOKE_TCR_WP(x)         (((x)&3)<<30)
325#define BOOKE_TCR_WP_MASK       (3<<30)
326#define BOOKE_TCR_WRC(x)        (((x)&3)<<28)
327#define BOOKE_TCR_WRC_MASK      (3<<28)
328#define BOOKE_TCR_WIE           (1<<27)
329#define BOOKE_TCR_DIE           (1<<26)
330#define BOOKE_TCR_FP(x)         (((x)&3)<<24)
331#define BOOKE_TCR_FIE           (1<<23)
332#define BOOKE_TCR_ARE           (1<<22)
333#define BOOKE_TCR_WPEXT(x)      (((x)&0xf)<<17)
334#define BOOKE_TCR_WPEXT_MASK    (0xf<<17)
335#define BOOKE_TCR_FPEXT(x)      (((x)&0xf)<<13)
336#define BOOKE_TCR_FPEXT_MASK    (0xf<<13)
337
338#define BOOKE_PID       48   /* Process ID                                */
339#define BOOKE_CSRR0     58   /* Critical Save/Restore Register 0          */
340#define BOOKE_CSRR1     59   /* Critical Save/Restore Register 1          */
341#define BOOKE_ESR       62   /* Exception Syndrome Register               */
342#define BOOKE_IVPR      63   /* Interrupt Vector Prefix Register          */
343#define BOOKE_SPRG4_W  260   /* Special Purpose Register General 4 (WO)   */
344#define BOOKE_SPRG5_W  261   /* Special Purpose Register General 5 (WO)   */
345#define BOOKE_SPRG6_W  262   /* Special Purpose Register General 6 (WO)   */
346#define BOOKE_SPRG7_W  263   /* Special Purpose Register General 7 (WO)   */
347#define BOOKE_PIR      286   /* Processor ID Register                     */
348#define BOOKE_DBSR     304   /* Debug Status Register                     */
349
350#define BOOKE_EPCR     307   /* Embedded Processor Control Register       */
351#define BOOKE_EPCR_EXTGS  (1 << 31)
352#define BOOKE_EPCR_DTLBGS (1 << 30)
353#define BOOKE_EPCR_ITLBGS (1 << 29)
354#define BOOKE_EPCR_DSIGS  (1 << 28)
355#define BOOKE_EPCR_ISIGS  (1 << 27)
356#define BOOKE_EPCR_DUVD   (1 << 26)
357#define BOOKE_EPCR_ICM    (1 << 25)
358#define BOOKE_EPCR_GICM   (1 << 24)
359#define BOOKE_EPCR_DGTMI  (1 << 23)
360#define BOOKE_EPCR_DMIUH  (1 << 22)
361#define BOOKE_EPCR_PMGS   (1 << 21)
362
363#define BOOKE_DBCR0    308   /* Debug Control Register 0                  */
364#define BOOKE_DBCR1    309   /* Debug Control Register 1                  */
365#define BOOKE_DBCR2    310   /* Debug Control Register 2                  */
366#define BOOKE_IAC1     312   /* Instruction Address Compare 1             */
367#define BOOKE_IAC2     313   /* Instruction Address Compare 2             */
368#define BOOKE_IAC3     314   /* Instruction Address Compare 3             */
369#define BOOKE_IAC4     315   /* Instruction Address Compare 4             */
370#define BOOKE_DAC1     316   /* Data Address Compare 1                    */
371#define BOOKE_DAC2     317   /* Data Address Compare 2                    */
372#define BOOKE_DVC1     318   /* Data Value Compare 1                      */
373#define BOOKE_DVC2     319   /* Data Value Compare 2                      */
374#define BOOKE_GSRR0    378   /* Guest Save/Restore Register 0             */
375#define BOOKE_GSRR1    379   /* Guest Save/Restore Register 1             */
376#define BOOKE_GEPR     380   /* Guest External Proxy Register             */
377#define BOOKE_GDEAR    381   /* Guest Data Exception Address Register     */
378#define BOOKE_GPIR     382   /* Guest Processor ID Register               */
379#define BOOKE_GESR     383   /* Guest Exception Syndrome Register         */
380#define BOOKE_IVOR0    400   /* Interrupt Vector Offset Register 0        */
381#define BOOKE_IVOR1    401   /* Interrupt Vector Offset Register 1        */
382#define BOOKE_IVOR2    402   /* Interrupt Vector Offset Register 2        */
383#define BOOKE_IVOR3    403   /* Interrupt Vector Offset Register 3        */
384#define BOOKE_IVOR4    404   /* Interrupt Vector Offset Register 4        */
385#define BOOKE_IVOR5    405   /* Interrupt Vector Offset Register 5        */
386#define BOOKE_IVOR6    406   /* Interrupt Vector Offset Register 6        */
387#define BOOKE_IVOR7    407   /* Interrupt Vector Offset Register 7        */
388#define BOOKE_IVOR8    408   /* Interrupt Vector Offset Register 8        */
389#define BOOKE_IVOR9    409   /* Interrupt Vector Offset Register 9        */
390#define BOOKE_IVOR10   410   /* Interrupt Vector Offset Register 10       */
391#define BOOKE_IVOR11   411   /* Interrupt Vector Offset Register 11       */
392#define BOOKE_IVOR12   412   /* Interrupt Vector Offset Register 12       */
393#define BOOKE_IVOR13   413   /* Interrupt Vector Offset Register 13       */
394#define BOOKE_IVOR14   414   /* Interrupt Vector Offset Register 14       */
395#define BOOKE_IVOR15   415   /* Interrupt Vector Offset Register 15       */
396#define BOOKE_IVOR42   436   /* Interrupt Vector Offset Register 42       */
397#define BOOKE_IVOR32   528   /* Interrupt Vector Offset Register 32       */
398#define BOOKE_IVOR33   529   /* Interrupt Vector Offset Register 33       */
399#define BOOKE_IVOR34   530   /* Interrupt Vector Offset Register 34       */
400#define BOOKE_IVOR35   531   /* Interrupt Vector Offset Register 35       */
401#define BOOKE_IVOR36   532   /* Interrupt Vector Offset Register 36       */
402#define BOOKE_IVOR37   533   /* Interrupt Vector Offset Register 37       */
403#define BOOKE_IVOR38   432   /* Interrupt Vector Offset Register 38       */
404#define BOOKE_IVOR39   433   /* Interrupt Vector Offset Register 39       */
405#define BOOKE_IVOR40   434   /* Interrupt Vector Offset Register 40       */
406#define BOOKE_IVOR41   435   /* Interrupt Vector Offset Register 41       */
407#define BOOKE_GIVOR2   440   /* Guest Interrupt Vector Offset Register 2  */
408#define BOOKE_GIVOR3   441   /* Guest Interrupt Vector Offset Register 3  */
409#define BOOKE_GIVOR4   442   /* Guest Interrupt Vector Offset Register 4  */
410#define BOOKE_GIVOR8   443   /* Guest Interrupt Vector Offset Register 8  */
411#define BOOKE_GIVOR13  444   /* Guest Interrupt Vector Offset Register 13 */
412#define BOOKE_GIVOR14  445   /* Guest Interrupt Vector Offset Register 14 */
413#define BOOKE_GIVPR    446   /* Guest Interrupt Vector Prefix Register    */
414#define BOOKE_MCSRR0   570   /* Machine Check Save/Restore Register 0     */
415#define BOOKE_MCSRR1   571   /* Machine Check Save/Restore Register 1     */
416#define BOOKE_MCSR     572   /* Machine Check Status Register             */
417#define BOOKE_DSRR0    574   /* Debug Save/Restore Register 0             */
418#define BOOKE_DSRR1    575   /* Debug Save/Restore Register 1             */
419
420#define PPC440_INV0    880   /* Instruction Cache Normal Victim 0         */
421#define PPC440_INV1    881   /* Instruction Cache Normal Victim 1         */
422#define PPC440_INV2    882   /* Instruction Cache Normal Victim 2         */
423#define PPC440_INV3    883   /* Instruction Cache Normal Victim 3         */
424#define PPC440_ITV0    884   /* Instruction Cache Transient Victim 0      */
425#define PPC440_ITV1    885   /* Instruction Cache Transient Victim 1      */
426#define PPC440_ITV2    886   /* Instruction Cache Transient Victim 2      */
427#define PPC440_ITV3    887   /* Instruction Cache Transient Victim 3      */
428#define PPC440_CCR1    888   /* Core Configuration Register 1             */
429#define PPC440_DNV0    912   /* Data Cache Normal Victim 0                */
430#define PPC440_DNV1    913   /* Data Cache Normal Victim 1                */
431#define PPC440_DNV2    914   /* Data Cache Normal Victim 2                */
432#define PPC440_DNV3    915   /* Data Cache Normal Victim 3                */
433#define PPC440_DTV0    916   /* Data Cache Transient Victim 0             */
434#define PPC440_DTV1    917   /* Data Cache Transient Victim 1             */
435#define PPC440_DTV2    918   /* Data Cache Transient Victim 2             */
436#define PPC440_DTV3    919   /* Data Cache Transient Victim 3             */
437#define PPC440_DVLIM   920   /* Data Cache Victim Limit                   */
438#define PPC440_IVLIM   921   /* Instruction Cache Victim Limit            */
439#define PPC440_RSTCFG  923   /* Reset Configuration                       */
440#define PPC440_DCDBTRL 924   /* Data Cache Debug Tag Register Low         */
441#define PPC440_DCDBTRH 925   /* Data Cache Debug Tag Register High        */
442#define PPC440_ICDBTRL 926   /* Instruction Cache Debug Tag Register Low  */
443#define PPC440_ICDBTRH 927   /* Instruction Cache Debug Tag Register High */
444#define PPC440_MMUCR   946   /* Memory Management Unit Control Register   */
445#define PPC440_CCR0    947   /* Core Configuration Register 0             */
446#define PPC440_ICDBDR  979   /* Instruction Cache Debug Data Register     */
447#define PPC440_DBDR   1011   /* Debug Data Register                       */
448
449#define PPC440_TLB0_EPN(n)       ( (((1<<22)-1)&(n)) << (31-21))  /* Etended Page Number    */
450#define PPC440_TLB0_EPN_GET(n)   (             ((n)  >> (31-21)) & ((1<<22)-1))
451#define PPC440_TLB0_V            (               1   << (31-22))  /* Entry valid            */
452#define PPC440_TLB0_TS           (               1   << (31-23))  /* Translation space      */
453#define PPC440_TLB0_TSIZE(n)     (       (0xf & (n)) << (31-27))  /* Page size              */
454#define PPC440_TLB0_TSIZE_GET(n) (           ((n)  >> (31-27)) & 0xf)
455#define PPC440_TLB0_TPAR(n)      (       (0xf & (n)) << (31-31))  /* Tag Parity             */
456#define PPC440_TLB0_TPAR_GET(n)  (            ((n)  >> (31-31)) & 0xf)
457
458#define PPC440_PID_TID(n)        (      (0xff & (n)) << (31-31))  /* Translation ID         */
459#define PPC440_PID_TID_GET(n)    (             ((n)  >> (31-31)) & 0xff)
460
461#define PPC440_TLB1_RPN(n)       ( (((1<<22)-1)&(n)) << (31-21))  /* Real Page Number       */
462#define PPC440_TLB1_RPN_GET(n)   (             ((n)  >> (31-21)) & ((1<<22)-1))
463#define PPC440_TLB1_PAR1(n)      (       (0x3 & (n)) << (31-23))  /* Parity for TLB word 1  */
464#define PPC440_TLB1_PAR1_GET(n)  (            ((n)  >> (31-23)) & 0x3)
465#define PPC440_TLB1_ERPN(n)      (       (0xf & (n)) << (31-31))  /* Extended Real Page No. */
466#define PPC440_TLB1_ERPN_GET(n)  (            ((n)  >> (31-31)) & 0xf)
467
468#define PPC440_TLB2_PAR2(n)      (       (0x3 & (n)) << (31- 1))  /* Parity for TLB word 2  */
469#define PPC440_TLB2_PAR2_GET(n)  (            ((n)  >> (31- 1)) & 0x3)
470#define PPC440_TLB2_U0           (               1   << (31-16))  /* User attr. 0           */
471#define PPC440_TLB2_U1           (               1   << (31-17))  /* User attr. 1           */
472#define PPC440_TLB2_U2           (               1   << (31-18))  /* User attr. 2           */
473#define PPC440_TLB2_U3           (               1   << (31-19))  /* User attr. 3           */
474#define PPC440_TLB2_W            (               1   << (31-20))  /* Write-through          */
475#define PPC440_TLB2_I            (               1   << (31-21))  /* Cache-inhibited        */
476#define PPC440_TLB2_M            (               1   << (31-22))  /* Memory-coherence req.  */
477#define PPC440_TLB2_G            (               1   << (31-23))  /* Guarded                */
478#define PPC440_TLB2_E            (               1   << (31-24))  /* Little-endian          */
479#define PPC440_TLB2_UX           (               1   << (31-26))  /* User  exec.            */
480#define PPC440_TLB2_UW           (               1   << (31-27))  /* User  write            */
481#define PPC440_TLB2_UR           (               1   << (31-28))  /* User  read             */
482#define PPC440_TLB2_SX           (               1   << (31-29))  /* Super exec.            */
483#define PPC440_TLB2_SW           (               1   << (31-30))  /* Super write            */
484#define PPC440_TLB2_SR           (               1   << (31-31))  /* Super read             */
485
486#define PPC440_TLB2_ATTR(x)      ( ((x) & 0x1ff) << 7 )
487#define PPC440_TLB2_ATTR_GET(x)  ( ((x) >> 7) & 0x1ff )
488
489#define PPC440_TLB2_PERM(n)      ( (n) & 0x3f )
490#define PPC440_TLB2_PERM_GET(n)  ( (n) & 0x3f )
491
492/* Freescale Book E Implementation Standards (EIS): Branch Operations */
493
494#define FSL_EIS_BUCSR 1013
495#define FSL_EIS_BUCSR_STAC_EN (1 << (63 - 39))
496#define FSL_EIS_BUCSR_LS_EN (1 << (63 - 41))
497#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54))
498#define FSL_EIS_BUCSR_BALLOC_ALL (0x0 << (63 - 59))
499#define FSL_EIS_BUCSR_BALLOC_FORWARD (0x1 << (63 - 59))
500#define FSL_EIS_BUCSR_BALLOC_BACKWARD (0x2 << (63 - 59))
501#define FSL_EIS_BUCSR_BALLOC_NONE (0x3 << (63 - 59))
502#define FSL_EIS_BUCSR_BPRED_TAKEN (0x0 << (63 - 61))
503#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_FORWARD (0x1 << (63 - 62))
504#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_BACKWARD (0x2 << (63 - 62))
505#define FSL_EIS_BUCSR_BPRED_NOT_TAKEN (0x3 << (63 - 62))
506#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63))
507
508/* Freescale Book E Implementation Standards (EIS): Hardware Implementation-Dependent Registers */
509
510#define FSL_EIS_SVR 1023
511
512/* Freescale Book E Implementation Standards (EIS): Thread Management and Control Registers */
513
514#define FSL_EIS_TENSR 437
515#define FSL_EIS_TENS 438
516#define FSL_EIS_TENC 439
517#define FSL_EIS_PPR32 898
518
519/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */
520
521#define FSL_EIS_MAS0 624
522#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35))
523#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47))
524#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf)
525#define FSL_EIS_MAS0_NV (1 << (63 - 63))
526
527#define FSL_EIS_MAS1 625
528#define FSL_EIS_MAS1_V (1 << (63 - 32))
529#define FSL_EIS_MAS1_IPROT (1 << (63 - 33))
530#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47))
531#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff)
532#define FSL_EIS_MAS1_TS (1 << (63 - 51))
533#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55))
534#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf)
535
536#define FSL_EIS_MAS2 626
537#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51))
538#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff)
539#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12)
540#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12)
541#define FSL_EIS_MAS2_X0 (1 << (63 - 57))
542#define FSL_EIS_MAS2_X1 (1 << (63 - 58))
543#define FSL_EIS_MAS2_W (1 << (63 - 59))
544#define FSL_EIS_MAS2_I (1 << (63 - 60))
545#define FSL_EIS_MAS2_M (1 << (63 - 61))
546#define FSL_EIS_MAS2_G (1 << (63 - 62))
547#define FSL_EIS_MAS2_E (1 << (63 - 63))
548#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f)
549#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f)
550
551#define FSL_EIS_MAS3 627
552#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51))
553#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff)
554#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12)
555#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12)
556#define FSL_EIS_MAS3_U0 (1 << (63 - 54))
557#define FSL_EIS_MAS3_U1 (1 << (63 - 55))
558#define FSL_EIS_MAS3_U2 (1 << (63 - 56))
559#define FSL_EIS_MAS3_U3 (1 << (63 - 57))
560#define FSL_EIS_MAS3_UX (1 << (63 - 58))
561#define FSL_EIS_MAS3_SX (1 << (63 - 59))
562#define FSL_EIS_MAS3_UW (1 << (63 - 60))
563#define FSL_EIS_MAS3_SW (1 << (63 - 61))
564#define FSL_EIS_MAS3_UR (1 << (63 - 62))
565#define FSL_EIS_MAS3_SR (1 << (63 - 63))
566#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff)
567#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff)
568
569#define FSL_EIS_MAS4 628
570#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35))
571#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47))
572#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55))
573#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0
574#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1
575#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W
576#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I
577#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M
578#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G
579#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E
580
581#define FSL_EIS_MAS5 629
582
583#define FSL_EIS_MAS6 630
584#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55))
585#define FSL_EIS_MAS6_SAS (1 << (63 - 63))
586
587#define FSL_EIS_MAS7 944
588
589#define FSL_EIS_MAS8 341
590
591#define FSL_EIS_MMUCFG 1015
592#define FSL_EIS_MMUCSR0 1012
593#define FSL_EIS_PID0 48
594#define FSL_EIS_PID1 633
595#define FSL_EIS_PID2 634
596#define FSL_EIS_TLB0CFG 688
597#define FSL_EIS_TLB1CFG 689
598
599/* Freescale Book E Implementation Standards (EIS): L1 Cache */
600
601#define FSL_EIS_L1CFG0 515
602#define FSL_EIS_L1CFG1 516
603#define FSL_EIS_L1CSR0 1010
604#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62))
605#define FSL_EIS_L1CSR1 1011
606#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62))
607
608/* Freescale Book E Implementation Standards (EIS): L2 Cache */
609
610#define FSL_EIS_L2CFG0 519
611#define FSL_EIS_L2CSR0 1017
612#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42))
613#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52))
614#define FSL_EIS_L2CSR1 1018
615
616/* Freescale Book E Implementation Standards (EIS): Timer */
617
618#define FSL_EIS_ATBL 526
619#define FSL_EIS_ATBU 527
620
621/* Freescale Book E Implementation Standards (EIS): Interrupt */
622
623#define FSL_EIS_MCAR 573
624#define FSL_EIS_DSRR0 574
625#define FSL_EIS_DSRR1 575
626
627/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */
628
629#define FSL_EIS_SPEFSCR 512
630
631/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */
632
633#define FSL_EIS_SPRG8 604
634#define FSL_EIS_SPRG9 605
635
636/* Freescale Book E Implementation Standards (EIS): Debug */
637
638#define FSL_EIS_DBCR3 561
639#define FSL_EIS_DBCR4 563
640#define FSL_EIS_DBCR5 564
641#define FSL_EIS_DBCR6 603
642#define FSL_EIS_DBCNT 562
643
644/**
645 * @brief Default value for the interrupt disable mask.
646 *
647 * The interrupt disable mask is stored in the global symbol
648 * _PPC_INTERRUPT_DISABLE_MASK.
649 */
650#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
651
652#ifndef ASM
653
654#include <stdint.h>
655
656#ifdef __cplusplus
657extern "C" {
658#endif /* __cplusplus */
659
660#define _CPU_MSR_GET( _msr_value ) \
661  do { \
662    _msr_value = 0; \
663    __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
664  } while (0)
665
666#define _CPU_MSR_SET( _msr_value ) \
667{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
668
669/**
670 * @brief A global symbol used to disable interrupts in the MSR.
671 *
672 * A one bit means that this bit should be cleared.
673 */
674extern char _PPC_INTERRUPT_DISABLE_MASK[];
675
676static inline uint32_t ppc_interrupt_get_disable_mask( void )
677{
678  return (uint32_t) _PPC_INTERRUPT_DISABLE_MASK;
679}
680
681static inline uint32_t ppc_interrupt_disable( void )
682{
683  uint32_t level;
684
685#if defined(__PPC_CPU_E6500__)
686  __asm__ volatile (
687    "mfmsr %0;"
688    "wrteei 0"
689    : "=r" (level)
690  );
691#else
692  uint32_t mask;
693
694  __asm__ volatile (
695    "mfmsr %0;"
696    "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;"
697    "ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;"
698    "andc %1, %0, %1;"
699    "mtmsr %1"
700    : "=r" (level), "=r" (mask)
701  );
702#endif
703
704  return level;
705}
706
707static inline void ppc_interrupt_enable( uint32_t level )
708{
709#if defined(__PPC_CPU_E6500__)
710  __asm__ volatile (
711    "wrtee %0"
712    :
713    : "r" (level)
714  );
715#else
716  __asm__ volatile (
717    "mtmsr %0"
718    :
719    : "r" (level)
720  );
721#endif
722}
723
724static inline void ppc_interrupt_flash( uint32_t level )
725{
726  uint32_t current_level;
727
728  __asm__ volatile (
729    "mfmsr %0;"
730    "mtmsr %1;"
731    "mtmsr %0"
732    : "=&r" (current_level)
733    : "r" (level)
734  );
735}
736
737#define _CPU_ISR_Disable( _isr_cookie ) \
738  do { \
739    _isr_cookie = ppc_interrupt_disable(); \
740  } while (0)
741
742/*
743 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
744 *  This indicates the end of an RTEMS critical section.  The parameter
745 *  _isr_cookie is not modified.
746 */
747
748#define _CPU_ISR_Enable( _isr_cookie )  \
749  ppc_interrupt_enable(_isr_cookie)
750
751/*
752 *  This temporarily restores the interrupt to _isr_cookie before immediately
753 *  disabling them again.  This is used to divide long RTEMS critical
754 *  sections into two or more parts.  The parameter _isr_cookie is not
755 *  modified.
756 *
757 *  NOTE:  The version being used is not very optimized but it does
758 *         not trip a problem in gcc where the disable mask does not
759 *         get loaded.  Check this for future (post 10/97 gcc versions.
760 */
761
762#define _CPU_ISR_Flash( _isr_cookie ) \
763  ppc_interrupt_flash(_isr_cookie)
764
765/* end of ISR handler macros */
766
767#ifdef __cplusplus
768}
769#endif /* __cplusplus */
770
771#endif /* ASM */
772
773#endif /* _RTEMS_POWERPC_REGISTERS_H */
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