| 1 | /* |
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| 2 | * This file contains some powerpc MSR and registers access definitions. |
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| 3 | * |
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| 4 | * COPYRIGHT (C) 1999 Eric Valette (valette@crf.canon.fr) |
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| 5 | * Canon Centre Recherche France. |
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| 6 | * |
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| 7 | * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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| 8 | * Surrey Satellite Technology Limited |
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| 9 | * |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in found in the file LICENSE in this distribution or at |
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| 13 | * http://www.rtems.com/license/LICENSE. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef _RTEMS_POWERPC_REGISTERS_H |
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| 19 | #define _RTEMS_POWERPC_REGISTERS_H |
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| 20 | |
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| 21 | /* Bit encodings for Machine State Register (MSR) */ |
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| 22 | #define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ |
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| 23 | #define MSR_POW (1<<18) /* Enable Power Management */ |
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| 24 | #define MSR_TGPR (1<<17) /* TLB Update registers in use */ |
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| 25 | #define MSR_CE (1<<17) /* BookE critical interrupt */ |
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| 26 | #define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ |
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| 27 | #define MSR_EE (1<<15) /* External Interrupt enable */ |
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| 28 | #define MSR_PR (1<<14) /* Supervisor/User privilege */ |
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| 29 | #define MSR_FP (1<<13) /* Floating Point enable */ |
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| 30 | #define MSR_ME (1<<12) /* Machine Check enable */ |
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| 31 | #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ |
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| 32 | #define MSR_SE (1<<10) /* Single Step */ |
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| 33 | #define MSR_BE (1<<9) /* Branch Trace */ |
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| 34 | #define MSR_DE (1<<9) /* BookE debug exception */ |
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| 35 | #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ |
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| 36 | #define MSR_E300_CE (1<<7) /* e300 critical interrupt */ |
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| 37 | #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ |
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| 38 | #define MSR_IR (1<<5) /* Instruction MMU enable */ |
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| 39 | #define MSR_DR (1<<4) /* Data MMU enable */ |
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| 40 | #define MSR_RI (1<<1) /* Recoverable Exception */ |
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| 41 | #define MSR_LE (1<<0) /* Little-Endian enable */ |
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| 42 | |
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| 43 | /* Bit encodings for Hardware Implementation Register (HID0) |
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| 44 | on PowerPC 603, 604, etc. processors (not 601). */ |
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| 45 | |
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| 46 | /* WARNING: HID0/HID1 are *truely* implementation dependent! |
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| 47 | * you *cannot* rely on the same bits to be present, |
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| 48 | * at the same place or even in the same register |
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| 49 | * on different CPU familys. |
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| 50 | * E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the |
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| 51 | * on the 7450s. IFFT is XBSEN on 7450 and so on... |
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| 52 | */ |
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| 53 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ |
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| 54 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ |
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| 55 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ |
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| 56 | #define HID0_SBCLK (1<<27) |
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| 57 | #define HID0_TBEN (1<<26) /* 7455:this bit must be set |
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| 58 | * and TBEN signal must be asserted |
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| 59 | * to enable the time base and |
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| 60 | * decrementer. |
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| 61 | */ |
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| 62 | #define HID0_EICE (1<<26) |
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| 63 | #define HID0_ECLK (1<<25) |
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| 64 | #define HID0_PAR (1<<24) |
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| 65 | #define HID0_DOZE (1<<23) |
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| 66 | /* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !! */ |
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| 67 | #define HID0_7455_HIGH_BAT_EN (1<<23) |
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| 68 | |
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| 69 | #define HID0_NAP (1<<22) |
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| 70 | #define HID0_SLEEP (1<<21) |
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| 71 | #define HID0_DPM (1<<20) |
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| 72 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ |
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| 73 | #define HID0_DCE (1<<14) /* Data Cache Enable */ |
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| 74 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ |
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| 75 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ |
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| 76 | #define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ |
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| 77 | #define HID0_DCI (1<<10) /* Data Cache Invalidate */ |
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| 78 | /* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */ |
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| 79 | #define HID0_7455_XBSEN (1<<8) |
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| 80 | #define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ |
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| 81 | #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ |
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| 82 | /* S.K. Feng 10/03, added for MPC7455 */ |
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| 83 | #define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ |
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| 84 | #define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ |
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| 85 | |
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| 86 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ |
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| 87 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ |
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| 88 | |
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| 89 | /* fpscr settings */ |
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| 90 | #define FPSCR_FX (1<<31) |
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| 91 | #define FPSCR_FEX (1<<30) |
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| 92 | |
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| 93 | #define _MACH_prep 1 |
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| 94 | #define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ |
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| 95 | #define _MACH_chrp 4 /* chrp machine */ |
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| 96 | #define _MACH_mbx 8 /* Motorola MBX board */ |
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| 97 | #define _MACH_apus 16 /* amiga with phase5 powerup */ |
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| 98 | #define _MACH_fads 32 /* Motorola FADS board */ |
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| 99 | |
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| 100 | /* see residual.h for these */ |
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| 101 | #define _PREP_Motorola 0x01 /* motorola prep */ |
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| 102 | #define _PREP_Firm 0x02 /* firmworks prep */ |
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| 103 | #define _PREP_IBM 0x00 /* ibm prep */ |
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| 104 | #define _PREP_Bull 0x03 /* bull prep */ |
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| 105 | |
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| 106 | /* these are arbitrary */ |
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| 107 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ |
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| 108 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ |
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| 109 | |
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| 110 | #define _GLOBAL(n)\ |
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| 111 | .globl n;\ |
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| 112 | n: |
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| 113 | |
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| 114 | #define TBRU 269 /* Time base Upper/Lower (Reading) */ |
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| 115 | #define TBRL 268 |
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| 116 | #define TBWU 285 /* Time base Upper/Lower (Writing) */ |
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| 117 | #define TBWL 284 |
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| 118 | #define XER 1 |
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| 119 | #define LR 8 |
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| 120 | #define CTR 9 |
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| 121 | #define HID0 1008 /* Hardware Implementation */ |
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| 122 | #define HID1 1009 /* Hardware Implementation */ |
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| 123 | #define DABR 1013 /* Data Access Breakpoint */ |
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| 124 | #define PVR 287 /* Processor Version */ |
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| 125 | #define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ |
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| 126 | #define IBAT0L 529 |
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| 127 | #define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ |
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| 128 | #define IBAT1L 531 |
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| 129 | #define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ |
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| 130 | #define IBAT2L 533 |
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| 131 | #define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ |
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| 132 | #define IBAT3L 535 |
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| 133 | |
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| 134 | /* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ |
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| 135 | #define IBAT4U 560 /* Instruction BAT #0 Upper/Lower */ |
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| 136 | #define IBAT4L 561 |
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| 137 | #define IBAT5U 562 /* Instruction BAT #1 Upper/Lower */ |
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| 138 | #define IBAT5L 563 |
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| 139 | #define IBAT6U 564 /* Instruction BAT #2 Upper/Lower */ |
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| 140 | #define IBAT6L 565 |
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| 141 | #define IBAT7U 566 /* Instruction BAT #3 Upper/Lower */ |
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| 142 | #define IBAT7L 567 |
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| 143 | |
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| 144 | #define DBAT0U 536 /* Data BAT #0 Upper/Lower */ |
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| 145 | #define DBAT0L 537 |
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| 146 | #define DBAT1U 538 /* Data BAT #1 Upper/Lower */ |
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| 147 | #define DBAT1L 539 |
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| 148 | #define DBAT2U 540 /* Data BAT #2 Upper/Lower */ |
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| 149 | #define DBAT2L 541 |
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| 150 | #define DBAT3U 542 /* Data BAT #3 Upper/Lower */ |
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| 151 | #define DBAT3L 543 |
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| 152 | |
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| 153 | /* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ |
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| 154 | #define DBAT4U 568 /* Instruction BAT #0 Upper/Lower */ |
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| 155 | #define DBAT4L 569 |
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| 156 | #define DBAT5U 570 /* Instruction BAT #1 Upper/Lower */ |
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| 157 | #define DBAT5L 571 |
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| 158 | #define DBAT6U 572 /* Instruction BAT #2 Upper/Lower */ |
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| 159 | #define DBAT6L 573 |
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| 160 | #define DBAT7U 574 /* Instruction BAT #3 Upper/Lower */ |
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| 161 | #define DBAT7L 575 |
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| 162 | |
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| 163 | #define DMISS 976 /* TLB Lookup/Refresh registers */ |
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| 164 | #define DCMP 977 |
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| 165 | #define HASH1 978 |
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| 166 | #define HASH2 979 |
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| 167 | #define IMISS 980 |
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| 168 | #define ICMP 981 |
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| 169 | #define RPA 982 |
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| 170 | #define SDR1 25 /* MMU hash base register */ |
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| 171 | #define DAR 19 /* Data Address Register */ |
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| 172 | #define SPR0 272 /* Supervisor Private Registers */ |
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| 173 | #define SPRG0 272 |
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| 174 | #define SPR1 273 |
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| 175 | #define SPRG1 273 |
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| 176 | #define SPR2 274 |
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| 177 | #define SPRG2 274 |
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| 178 | #define SPR3 275 |
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| 179 | #define SPRG3 275 |
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| 180 | #define SPRG4 276 |
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| 181 | #define SPRG5 277 |
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| 182 | #define SPRG6 278 |
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| 183 | #define SPRG7 279 |
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| 184 | #define USPRG0 256 |
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| 185 | #define DSISR 18 |
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| 186 | #define SRR0 26 /* Saved Registers (exception) */ |
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| 187 | #define SRR1 27 |
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| 188 | #define IABR 1010 /* Instruction Address Breakpoint */ |
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| 189 | #define DEC 22 /* Decrementer */ |
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| 190 | #define EAR 282 /* External Address Register */ |
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| 191 | |
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| 192 | #define MSSCR0 1014 /* Memory Subsystem Control Register */ |
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| 193 | |
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| 194 | #define L2CR 1017 /* PPC 750 and 74xx L2 control register */ |
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| 195 | |
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| 196 | #define L2CR_L2E (1<<31) /* enable */ |
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| 197 | #define L2CR_L2I (1<<21) /* global invalidate */ |
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| 198 | |
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| 199 | /* watch out L2IO and L2DO are different between 745x and 7400/7410 */ |
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| 200 | /* Oddly, the following L2CR bit defintions in 745x |
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| 201 | * is different from that of 7400 and 7410. |
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| 202 | * Though not used in 7400 and 7410, it is appeded with _745x just |
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| 203 | * to be clarified. |
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| 204 | */ |
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| 205 | #define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ |
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| 206 | #define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ |
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| 207 | #define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) |
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| 208 | #define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ |
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| 209 | |
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| 210 | #define L3CR 1018 /* PPC 7450/7455 L3 control register */ |
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| 211 | #define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ |
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| 212 | #define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ |
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| 213 | |
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| 214 | #define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) |
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| 215 | |
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| 216 | #define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ |
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| 217 | #define L3CR_L3E 0x80000000 /* 0: L3 enable */ |
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| 218 | #define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ |
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| 219 | #define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ |
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| 220 | #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ |
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| 221 | #define L3SIZ_1M 0x00000000 |
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| 222 | #define L3SIZ_2M 0x10000000 |
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| 223 | #define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ |
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| 224 | #define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ |
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| 225 | #define L3CLK_60 0x00000000 /* core clock / 6 */ |
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| 226 | #define L3CLK_20 0x01000000 /* / 2 */ |
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| 227 | #define L3CLK_25 0x01800000 /* / 2.5 */ |
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| 228 | #define L3CLK_30 0x02000000 /* / 3 */ |
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| 229 | #define L3CLK_35 0x02800000 /* / 3.5 */ |
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| 230 | #define L3CLK_40 0x03000000 /* / 4 */ |
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| 231 | #define L3CLK_50 0x03800000 /* / 5 */ |
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| 232 | #define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ |
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| 233 | #define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ |
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| 234 | #define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ |
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| 235 | #define L3CKSP_2 0x00000000 /* 2 clocks */ |
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| 236 | #define L3CKSP_3 0x00010000 /* 3 clocks */ |
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| 237 | #define L3CKSP_4 0x00020000 /* 4 clocks */ |
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| 238 | #define L3CKSP_5 0x00030000 /* 5 clocks */ |
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| 239 | #define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ |
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| 240 | #define L3PSP_0 0x00000000 /* 0 clocks */ |
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| 241 | #define L3PSP_1 0x00002000 /* 1 clocks */ |
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| 242 | #define L3PSP_2 0x00004000 /* 2 clocks */ |
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| 243 | #define L3PSP_3 0x00006000 /* 3 clocks */ |
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| 244 | #define L3PSP_4 0x00008000 /* 4 clocks */ |
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| 245 | #define L3PSP_5 0x0000a000 /* 5 clocks */ |
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| 246 | #define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ |
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| 247 | #define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ |
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| 248 | #define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig |
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| 249 | lidate */ |
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| 250 | #define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ |
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| 251 | #define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ |
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| 252 | #define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ |
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| 253 | #define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ |
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| 254 | #define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ |
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| 255 | #define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ |
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| 256 | #define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ |
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| 257 | #define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ |
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| 258 | |
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| 259 | #define THRM1 1020 |
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| 260 | #define THRM2 1021 |
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| 261 | #define THRM3 1022 |
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| 262 | #define THRM1_TIN (1<<(31-0)) |
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| 263 | #define THRM1_TIV (1<<(31-1)) |
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| 264 | #define THRM1_THRES (0x7f<<(31-8)) |
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| 265 | #define THRM1_TID (1<<(31-29)) |
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| 266 | #define THRM1_TIE (1<<(31-30)) |
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| 267 | #define THRM1_V (1<<(31-31)) |
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| 268 | #define THRM3_SITV (0x1fff << (31-30)) |
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| 269 | #define THRM3_E (1<<(31-31)) |
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| 270 | |
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| 271 | /* Segment Registers */ |
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| 272 | #define SR0 0 |
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| 273 | #define SR1 1 |
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| 274 | #define SR2 2 |
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| 275 | #define SR3 3 |
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| 276 | #define SR4 4 |
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| 277 | #define SR5 5 |
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| 278 | #define SR6 6 |
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| 279 | #define SR7 7 |
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| 280 | #define SR8 8 |
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| 281 | #define SR9 9 |
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| 282 | #define SR10 10 |
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| 283 | #define SR11 11 |
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| 284 | #define SR12 12 |
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| 285 | #define SR13 13 |
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| 286 | #define SR14 14 |
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| 287 | #define SR15 15 |
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| 288 | |
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| 289 | #define BOOKE_DECAR 54 |
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| 290 | |
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| 291 | #define PPC405_TSR 0x3D8 |
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| 292 | #define BOOKE_TSR 336 |
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| 293 | #define BOOKE_TSR_ENW (1<<31) |
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| 294 | #define BOOKE_TSR_WIS (1<<30) |
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| 295 | #define BOOKE_TSR_DIS (1<<27) |
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| 296 | #define BOOKE_TSR_FIS (1<<26) |
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| 297 | |
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| 298 | #define PPC405_TCR 0x3DA |
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| 299 | #define BOOKE_TCR 340 |
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| 300 | #define BOOKE_TCR_WP(x) (((x)&3)<<30) |
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| 301 | #define BOOKE_TCR_WP_MASK (3<<30) |
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| 302 | #define BOOKE_TCR_WRC(x) (((x)&3)<<28) |
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| 303 | #define BOOKE_TCR_WRC_MASK (3<<28) |
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| 304 | #define BOOKE_TCR_WIE (1<<27) |
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| 305 | #define BOOKE_TCR_DIE (1<<26) |
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| 306 | #define BOOKE_TCR_FP(x) (((x)&3)<<24) |
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| 307 | #define BOOKE_TCR_FIE (1<<23) |
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| 308 | #define BOOKE_TCR_ARE (1<<22) |
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| 309 | #define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17) |
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| 310 | #define BOOKE_TCR_WPEXT_MASK (0xf<<17) |
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| 311 | #define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13) |
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| 312 | #define BOOKE_TCR_FPEXT_MASK (0xf<<13) |
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| 313 | |
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| 314 | /** |
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| 315 | * @brief Default value for the interrupt disable mask. |
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| 316 | * |
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| 317 | * The interrupt disable mask is stored in the SPRG0 (= special purpose |
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| 318 | * register 272). |
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| 319 | */ |
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| 320 | #define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE |
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| 321 | |
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| 322 | #ifndef ASM |
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| 323 | |
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| 324 | #include <stdint.h> |
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| 325 | |
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| 326 | #ifdef __cplusplus |
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| 327 | extern "C" { |
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| 328 | #endif /* __cplusplus */ |
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| 329 | |
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| 330 | #define _CPU_MSR_GET( _msr_value ) \ |
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| 331 | do { \ |
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| 332 | _msr_value = 0; \ |
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| 333 | asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ |
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| 334 | } while (0) |
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| 335 | |
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| 336 | #define _CPU_MSR_SET( _msr_value ) \ |
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| 337 | { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } |
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| 338 | |
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| 339 | static inline void ppc_interrupt_set_disable_mask( uint32_t mask) |
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| 340 | { |
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| 341 | asm volatile ( |
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| 342 | "mtspr 272, %0" |
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| 343 | : |
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| 344 | : "r" (mask) |
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| 345 | ); |
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| 346 | } |
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| 347 | |
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| 348 | static inline uint32_t ppc_interrupt_get_disable_mask( void) |
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| 349 | { |
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| 350 | uint32_t mask; |
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| 351 | |
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| 352 | asm volatile ( |
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| 353 | "mfspr %0, 272" |
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| 354 | : "=r" (mask) |
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| 355 | ); |
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| 356 | |
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| 357 | return mask; |
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| 358 | } |
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| 359 | |
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| 360 | static inline uint32_t ppc_interrupt_disable( void) |
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| 361 | { |
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| 362 | uint32_t level; |
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| 363 | uint32_t mask; |
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| 364 | |
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| 365 | asm volatile ( |
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| 366 | "mfmsr %0;" |
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| 367 | "mfspr %1, 272;" |
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| 368 | "andc %1, %0, %1;" |
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| 369 | "mtmsr %1" |
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| 370 | : "=r" (level), "=r" (mask) |
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| 371 | ); |
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| 372 | |
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| 373 | return level; |
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| 374 | } |
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| 375 | |
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| 376 | static inline void ppc_interrupt_enable( uint32_t level) |
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| 377 | { |
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| 378 | asm volatile ( |
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| 379 | "mtmsr %0" |
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| 380 | : |
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| 381 | : "r" (level) |
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| 382 | ); |
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| 383 | } |
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| 384 | |
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| 385 | static inline void ppc_interrupt_flash( uint32_t level) |
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| 386 | { |
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| 387 | uint32_t current_level; |
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| 388 | |
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| 389 | asm volatile ( |
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| 390 | "mfmsr %0;" |
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| 391 | "mtmsr %1;" |
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| 392 | "mtmsr %0" |
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| 393 | : "=&r" (current_level) |
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| 394 | : "r" (level) |
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| 395 | ); |
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| 396 | } |
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| 397 | |
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| 398 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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| 399 | do { \ |
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| 400 | _isr_cookie = ppc_interrupt_disable(); \ |
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| 401 | } while (0) |
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| 402 | |
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| 403 | /* |
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| 404 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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| 405 | * This indicates the end of an RTEMS critical section. The parameter |
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| 406 | * _isr_cookie is not modified. |
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| 407 | */ |
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| 408 | |
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| 409 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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| 410 | ppc_interrupt_enable( _isr_cookie) |
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| 411 | |
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| 412 | /* |
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| 413 | * This temporarily restores the interrupt to _isr_cookie before immediately |
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| 414 | * disabling them again. This is used to divide long RTEMS critical |
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| 415 | * sections into two or more parts. The parameter _isr_cookie is not |
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| 416 | * modified. |
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| 417 | * |
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| 418 | * NOTE: The version being used is not very optimized but it does |
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| 419 | * not trip a problem in gcc where the disable mask does not |
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| 420 | * get loaded. Check this for future (post 10/97 gcc versions. |
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| 421 | */ |
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| 422 | |
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| 423 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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| 424 | ppc_interrupt_flash( _isr_cookie) |
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| 425 | |
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| 426 | /* end of ISR handler macros */ |
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| 427 | |
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| 428 | #ifdef __cplusplus |
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| 429 | } |
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| 430 | #endif /* __cplusplus */ |
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| 431 | |
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| 432 | #endif /* ASM */ |
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| 433 | |
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| 434 | #endif /* _RTEMS_POWERPC_REGISTERS_H */ |
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