1 | /* |
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2 | * This file contains some powerpc MSR and registers access definitions. |
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3 | * |
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4 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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5 | * Canon Centre Recherche France. |
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6 | * |
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7 | * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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8 | * Surrey Satellite Technology Limited |
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9 | * |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.com/license/LICENSE. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | #ifndef _RTEMS_POWERPC_REGISTERS_H |
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19 | #define _RTEMS_POWERPC_REGISTERS_H |
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20 | |
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21 | #ifdef __cplusplus |
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22 | extern "C" { |
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23 | #endif |
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24 | |
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25 | /* Bit encodings for Machine State Register (MSR) */ |
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26 | #define MSR_POW (1<<18) /* Enable Power Management */ |
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27 | #define MSR_TGPR (1<<17) /* TLB Update registers in use */ |
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28 | #define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ |
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29 | #define MSR_EE (1<<15) /* External Interrupt enable */ |
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30 | #define MSR_PR (1<<14) /* Supervisor/User privilege */ |
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31 | #define MSR_FP (1<<13) /* Floating Point enable */ |
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32 | #define MSR_ME (1<<12) /* Machine Check enable */ |
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33 | #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ |
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34 | #define MSR_SE (1<<10) /* Single Step */ |
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35 | #define MSR_BE (1<<9) /* Branch Trace */ |
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36 | #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ |
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37 | #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ |
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38 | #define MSR_IR (1<<5) /* Instruction MMU enable */ |
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39 | #define MSR_DR (1<<4) /* Data MMU enable */ |
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40 | #define MSR_RI (1<<1) /* Recoverable Exception */ |
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41 | #define MSR_LE (1<<0) /* Little-Endian enable */ |
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42 | |
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43 | #define MSR_ MSR_ME|MSR_RI |
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44 | #define MSR_KERNEL MSR_|MSR_IR|MSR_DR |
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45 | #define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE |
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46 | |
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47 | /* Bit encodings for Hardware Implementation Register (HID0) |
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48 | on PowerPC 603, 604, etc. processors (not 601). */ |
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49 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ |
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50 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ |
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51 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ |
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52 | #define HID0_SBCLK (1<<27) |
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53 | #define HID0_TBEN (1<<26) /* 7455:this bit must be set |
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54 | * and TBEN signal must be asserted |
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55 | * to enable the time base and |
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56 | * decrementer. |
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57 | */ |
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58 | #define HID0_EICE (1<<26) |
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59 | #define HID0_ECLK (1<<25) |
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60 | #define HID0_PAR (1<<24) |
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61 | #define HID0_DOZE (1<<23) |
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62 | #define HID0_NAP (1<<22) |
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63 | #define HID0_SLEEP (1<<21) |
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64 | #define HID0_DPM (1<<20) |
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65 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ |
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66 | #define HID0_DCE (1<<14) /* Data Cache Enable */ |
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67 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ |
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68 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ |
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69 | #define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ |
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70 | #define HID0_DCI (1<<10) /* Data Cache Invalidate */ |
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71 | #define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ |
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72 | #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ |
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73 | /* S.K. Feng 10/03, added for MPC7455 */ |
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74 | #define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ |
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75 | #define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ |
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76 | |
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77 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ |
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78 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ |
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79 | |
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80 | /* fpscr settings */ |
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81 | #define FPSCR_FX (1<<31) |
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82 | #define FPSCR_FEX (1<<30) |
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83 | |
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84 | #define _MACH_prep 1 |
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85 | #define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ |
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86 | #define _MACH_chrp 4 /* chrp machine */ |
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87 | #define _MACH_mbx 8 /* Motorola MBX board */ |
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88 | #define _MACH_apus 16 /* amiga with phase5 powerup */ |
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89 | #define _MACH_fads 32 /* Motorola FADS board */ |
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90 | |
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91 | /* see residual.h for these */ |
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92 | #define _PREP_Motorola 0x01 /* motorola prep */ |
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93 | #define _PREP_Firm 0x02 /* firmworks prep */ |
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94 | #define _PREP_IBM 0x00 /* ibm prep */ |
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95 | #define _PREP_Bull 0x03 /* bull prep */ |
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96 | |
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97 | /* these are arbitrary */ |
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98 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ |
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99 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ |
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100 | |
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101 | #define _GLOBAL(n)\ |
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102 | .globl n;\ |
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103 | n: |
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104 | |
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105 | #define TBRU 269 /* Time base Upper/Lower (Reading) */ |
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106 | #define TBRL 268 |
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107 | #define TBWU 284 /* Time base Upper/Lower (Writing) */ |
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108 | #define TBWL 285 |
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109 | #define XER 1 |
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110 | #define LR 8 |
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111 | #define CTR 9 |
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112 | #define HID0 1008 /* Hardware Implementation */ |
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113 | #define HID1 1009 /* Hardware Implementation */ |
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114 | #define DABR 1013 /* Data Access Breakpoint */ |
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115 | #define PVR 287 /* Processor Version */ |
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116 | #define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ |
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117 | #define IBAT0L 529 |
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118 | #define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ |
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119 | #define IBAT1L 531 |
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120 | #define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ |
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121 | #define IBAT2L 533 |
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122 | #define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ |
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123 | #define IBAT3L 535 |
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124 | #define DBAT0U 536 /* Data BAT #0 Upper/Lower */ |
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125 | #define DBAT0L 537 |
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126 | #define DBAT1U 538 /* Data BAT #1 Upper/Lower */ |
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127 | #define DBAT1L 539 |
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128 | #define DBAT2U 540 /* Data BAT #2 Upper/Lower */ |
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129 | #define DBAT2L 541 |
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130 | #define DBAT3U 542 /* Data BAT #3 Upper/Lower */ |
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131 | #define DBAT3L 543 |
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132 | #define DMISS 976 /* TLB Lookup/Refresh registers */ |
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133 | #define DCMP 977 |
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134 | #define HASH1 978 |
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135 | #define HASH2 979 |
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136 | #define IMISS 980 |
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137 | #define ICMP 981 |
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138 | #define RPA 982 |
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139 | #define SDR1 25 /* MMU hash base register */ |
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140 | #define DAR 19 /* Data Address Register */ |
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141 | #define SPR0 272 /* Supervisor Private Registers */ |
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142 | #define SPRG0 272 |
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143 | #define SPR1 273 |
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144 | #define SPRG1 273 |
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145 | #define SPR2 274 |
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146 | #define SPRG2 274 |
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147 | #define SPR3 275 |
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148 | #define SPRG3 275 |
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149 | #define DSISR 18 |
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150 | #define SRR0 26 /* Saved Registers (exception) */ |
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151 | #define SRR1 27 |
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152 | #define IABR 1010 /* Instruction Address Breakpoint */ |
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153 | #define DEC 22 /* Decrementer */ |
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154 | #define EAR 282 /* External Address Register */ |
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155 | |
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156 | #define MSSCR0 1014 /* Memory Subsystem Control Register */ |
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157 | |
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158 | #define L2CR 1017 /* PPC 750 and 74xx L2 control register */ |
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159 | |
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160 | #define L2CR_L2E (1<<31) /* enable */ |
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161 | #define L2CR_L2I (1<<21) /* global invalidate */ |
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162 | |
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163 | /* watch out L2IO and L2DO are different between 745x and 7400/7410 */ |
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164 | /* Oddly, the following L2CR bit defintions in 745x |
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165 | * is different from that of 7400 and 7410. |
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166 | * Though not used in 7400 and 7410, it is appeded with _745x just |
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167 | * to be clarified. |
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168 | */ |
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169 | #define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ |
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170 | #define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ |
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171 | #define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) |
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172 | #define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ |
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173 | |
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174 | #define L3CR 1018 /* PPC 7450/7455 L3 control register */ |
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175 | #define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ |
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176 | #define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ |
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177 | |
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178 | #define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) |
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179 | |
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180 | #define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ |
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181 | #define L3CR_L3E 0x80000000 /* 0: L3 enable */ |
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182 | #define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ |
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183 | #define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ |
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184 | #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ |
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185 | #define L3SIZ_1M 0x00000000 |
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186 | #define L3SIZ_2M 0x10000000 |
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187 | #define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ |
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188 | #define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ |
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189 | #define L3CLK_60 0x00000000 /* core clock / 6 */ |
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190 | #define L3CLK_20 0x01000000 /* / 2 */ |
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191 | #define L3CLK_25 0x01800000 /* / 2.5 */ |
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192 | #define L3CLK_30 0x02000000 /* / 3 */ |
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193 | #define L3CLK_35 0x02800000 /* / 3.5 */ |
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194 | #define L3CLK_40 0x03000000 /* / 4 */ |
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195 | #define L3CLK_50 0x03800000 /* / 5 */ |
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196 | #define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ |
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197 | #define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ |
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198 | #define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ |
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199 | #define L3CKSP_2 0x00000000 /* 2 clocks */ |
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200 | #define L3CKSP_3 0x00010000 /* 3 clocks */ |
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201 | #define L3CKSP_4 0x00020000 /* 4 clocks */ |
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202 | #define L3CKSP_5 0x00030000 /* 5 clocks */ |
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203 | #define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ |
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204 | #define L3PSP_0 0x00000000 /* 0 clocks */ |
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205 | #define L3PSP_1 0x00002000 /* 1 clocks */ |
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206 | #define L3PSP_2 0x00004000 /* 2 clocks */ |
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207 | #define L3PSP_3 0x00006000 /* 3 clocks */ |
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208 | #define L3PSP_4 0x00008000 /* 4 clocks */ |
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209 | #define L3PSP_5 0x0000a000 /* 5 clocks */ |
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210 | #define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ |
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211 | #define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ |
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212 | #define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig |
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213 | lidate */ |
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214 | #define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ |
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215 | #define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ |
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216 | #define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ |
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217 | #define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ |
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218 | #define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ |
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219 | #define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ |
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220 | #define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ |
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221 | #define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ |
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222 | |
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223 | #define THRM1 1020 |
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224 | #define THRM2 1021 |
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225 | #define THRM3 1022 |
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226 | #define THRM1_TIN (1<<(31-0)) |
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227 | #define THRM1_TIV (1<<(31-1)) |
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228 | #define THRM1_THRES (0x7f<<(31-8)) |
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229 | #define THRM1_TID (1<<(31-29)) |
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230 | #define THRM1_TIE (1<<(31-30)) |
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231 | #define THRM1_V (1<<(31-31)) |
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232 | #define THRM3_SITV (0x1fff << (31-30)) |
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233 | #define THRM3_E (1<<(31-31)) |
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234 | |
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235 | /* Segment Registers */ |
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236 | #define SR0 0 |
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237 | #define SR1 1 |
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238 | #define SR2 2 |
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239 | #define SR3 3 |
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240 | #define SR4 4 |
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241 | #define SR5 5 |
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242 | #define SR6 6 |
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243 | #define SR7 7 |
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244 | #define SR8 8 |
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245 | #define SR9 9 |
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246 | #define SR10 10 |
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247 | #define SR11 11 |
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248 | #define SR12 12 |
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249 | #define SR13 13 |
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250 | #define SR14 14 |
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251 | #define SR15 15 |
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252 | |
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253 | #ifndef ASM |
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254 | /* |
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255 | * Routines to access the time base register |
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256 | */ |
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257 | |
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258 | static inline unsigned long long PPC_Get_timebase_register( void ) |
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259 | { |
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260 | unsigned long tbr_low; |
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261 | unsigned long tbr_high; |
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262 | unsigned long tbr_high_old; |
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263 | unsigned long long tbr; |
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264 | |
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265 | do { |
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266 | asm volatile( "mftbu %0" : "=r" (tbr_high_old)); |
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267 | asm volatile( "mftb %0" : "=r" (tbr_low)); |
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268 | asm volatile( "mftbu %0" : "=r" (tbr_high)); |
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269 | } while ( tbr_high_old != tbr_high ); |
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270 | |
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271 | tbr = tbr_high; |
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272 | tbr <<= 32; |
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273 | tbr |= tbr_low; |
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274 | return tbr; |
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275 | } |
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276 | |
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277 | static inline void PPC_Set_timebase_register (unsigned long long tbr) |
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278 | { |
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279 | unsigned long tbr_low; |
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280 | unsigned long tbr_high; |
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281 | |
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282 | tbr_low = (tbr & 0xffffffff) ; |
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283 | tbr_high = (tbr >> 32) & 0xffffffff; |
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284 | asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); |
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285 | asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); |
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286 | |
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287 | } |
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288 | #endif |
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289 | |
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290 | #define _CPU_MSR_GET( _msr_value ) \ |
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291 | do { \ |
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292 | _msr_value = 0; \ |
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293 | asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ |
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294 | } while (0) |
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295 | |
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296 | #define _CPU_MSR_SET( _msr_value ) \ |
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297 | { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } |
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298 | |
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299 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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300 | { register unsigned int _disable_mask = MSR_EE; \ |
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301 | _isr_cookie = 0; \ |
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302 | asm volatile ( \ |
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303 | "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
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304 | "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ |
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305 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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306 | ); \ |
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307 | } |
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308 | |
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309 | |
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310 | /* |
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311 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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312 | * This indicates the end of an RTEMS critical section. The parameter |
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313 | * _isr_cookie is not modified. |
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314 | */ |
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315 | |
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316 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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317 | { \ |
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318 | asm volatile ( "mtmsr %0" : \ |
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319 | "=r" ((_isr_cookie)) : \ |
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320 | "0" ((_isr_cookie))); \ |
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321 | } |
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322 | |
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323 | /* |
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324 | * This temporarily restores the interrupt to _isr_cookie before immediately |
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325 | * disabling them again. This is used to divide long RTEMS critical |
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326 | * sections into two or more parts. The parameter _isr_cookie is not |
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327 | * modified. |
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328 | * |
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329 | * NOTE: The version being used is not very optimized but it does |
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330 | * not trip a problem in gcc where the disable mask does not |
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331 | * get loaded. Check this for future (post 10/97 gcc versions. |
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332 | */ |
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333 | |
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334 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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335 | { register unsigned int _disable_mask = MSR_EE; \ |
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336 | asm volatile ( \ |
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337 | "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
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338 | "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ |
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339 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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340 | ); \ |
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341 | } |
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342 | |
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343 | |
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344 | /* end of ISR handler macros */ |
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345 | |
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346 | /* |
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347 | * Simple spin delay in microsecond units for device drivers. |
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348 | * This is very dependent on the clock speed of the target. |
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349 | */ |
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350 | |
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351 | #define CPU_Get_timebase_low( _value ) \ |
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352 | asm volatile( "mftb %0" : "=r" (_value) ) |
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353 | |
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354 | #define rtems_bsp_delay( _microseconds ) \ |
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355 | do { \ |
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356 | uint32_t start, ticks, now; \ |
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357 | CPU_Get_timebase_low( start ) ; \ |
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358 | ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \ |
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359 | do \ |
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360 | CPU_Get_timebase_low( now ) ; \ |
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361 | while (now - start < ticks); \ |
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362 | } while (0) |
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363 | |
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364 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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365 | do { \ |
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366 | uint32_t start, now; \ |
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367 | CPU_Get_timebase_low( start ); \ |
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368 | do \ |
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369 | CPU_Get_timebase_low( now ); \ |
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370 | while (now - start < (_cycles)); \ |
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371 | } while (0) |
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372 | |
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373 | #define PPC_Set_decrementer( _clicks ) \ |
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374 | do { \ |
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375 | asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ |
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376 | } while (0) |
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377 | |
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378 | #define PPC_Get_decrementer( _clicks ) \ |
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379 | asm volatile( "mfdec %0" : "=r" (_clicks) ) |
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380 | |
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381 | #ifdef __cplusplus |
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382 | } |
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383 | #endif |
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384 | |
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385 | #endif /* __rtems_powerpc_registers_h */ |
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