source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ 83d7232

4.104.114.84.95
Last change on this file since 83d7232 was 83d7232, checked in by Eric Norum <WENorum@…>, on Oct 20, 2004 at 3:42:24 PM

Add Kate Feng's MVME5500 BSP.

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1/*
2 * This file contains some powerpc MSR and registers access definitions.
3 *
4 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
5 *                     Canon Centre Recherche France.
6 *
7 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited
9 *
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef __rtems_powerpc_registers_h
19#define __rtems_powerpc_registers_h
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/* Bit encodings for Machine State Register (MSR) */
26#define MSR_POW         (1<<18)         /* Enable Power Management */
27#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
28#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
29#define MSR_EE          (1<<15)         /* External Interrupt enable */
30#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
31#define MSR_FP          (1<<13)         /* Floating Point enable */
32#define MSR_ME          (1<<12)         /* Machine Check enable */
33#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
34#define MSR_SE          (1<<10)         /* Single Step */
35#define MSR_BE          (1<<9)          /* Branch Trace */
36#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
37#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
38#define MSR_IR          (1<<5)          /* Instruction MMU enable */
39#define MSR_DR          (1<<4)          /* Data MMU enable */
40#define MSR_RI          (1<<1)          /* Recoverable Exception */
41#define MSR_LE          (1<<0)          /* Little-Endian enable */
42
43#define MSR_            MSR_ME|MSR_RI
44#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
45#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
46
47/* Bit encodings for Hardware Implementation Register (HID0)
48   on PowerPC 603, 604, etc. processors (not 601). */
49#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
50#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
51#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
52#define HID0_SBCLK      (1<<27)
53#define HID0_TBEN       (1<<26)         /* 7455:this bit must be set
54                                         * and TBEN signal must be asserted
55                                         * to enable the time base and
56                                         * decrementer.
57                                         */
58#define HID0_EICE       (1<<26)
59#define HID0_ECLK       (1<<25)
60#define HID0_PAR        (1<<24)
61#define HID0_DOZE       (1<<23)
62#define HID0_NAP        (1<<22)
63#define HID0_SLEEP      (1<<21)
64#define HID0_DPM        (1<<20)
65#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
66#define HID0_DCE        (1<<14)         /* Data Cache Enable */
67#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
68#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
69#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
70#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
71#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
72#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
73/* S.K. Feng 10/03, added for MPC7455 */
74#define HID0_LRSTK      (1<<4)          /* Link register stack enable (7455) */
75#define HID0_FOLD       (1<<3)          /* Branch folding enable (7455) */
76
77#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
78#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
79
80/* fpscr settings */
81#define FPSCR_FX        (1<<31)
82#define FPSCR_FEX       (1<<30)
83
84#define _MACH_prep     1
85#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
86#define _MACH_chrp     4 /* chrp machine */
87#define _MACH_mbx      8 /* Motorola MBX board */
88#define _MACH_apus    16 /* amiga with phase5 powerup */
89#define _MACH_fads    32 /* Motorola FADS board */
90
91/* see residual.h for these */
92#define _PREP_Motorola 0x01  /* motorola prep */
93#define _PREP_Firm     0x02  /* firmworks prep */
94#define _PREP_IBM      0x00  /* ibm prep */
95#define _PREP_Bull     0x03  /* bull prep */
96
97/* these are arbitrary */
98#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
99#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
100
101#define _GLOBAL(n)\
102        .globl n;\
103n:
104
105#define TBRU    269     /* Time base Upper/Lower (Reading) */
106#define TBRL    268
107#define TBWU    284     /* Time base Upper/Lower (Writing) */
108#define TBWL    285
109#define XER     1
110#define LR      8
111#define CTR     9
112#define HID0    1008    /* Hardware Implementation */
113#define HID1    1009    /* Hardware Implementation */
114#define DABR    1013    /* Data Access Breakpoint  */
115#define PVR     287     /* Processor Version */
116#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
117#define IBAT0L  529
118#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
119#define IBAT1L  531
120#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
121#define IBAT2L  533
122#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
123#define IBAT3L  535
124#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
125#define DBAT0L  537
126#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
127#define DBAT1L  539
128#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
129#define DBAT2L  541
130#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
131#define DBAT3L  543
132#define DMISS   976     /* TLB Lookup/Refresh registers */
133#define DCMP    977
134#define HASH1   978
135#define HASH2   979
136#define IMISS   980
137#define ICMP    981
138#define RPA     982
139#define SDR1    25      /* MMU hash base register */
140#define DAR     19      /* Data Address Register */
141#define SPR0    272     /* Supervisor Private Registers */
142#define SPRG0   272
143#define SPR1    273
144#define SPRG1   273
145#define SPR2    274
146#define SPRG2   274
147#define SPR3    275
148#define SPRG3   275
149#define DSISR   18
150#define SRR0    26      /* Saved Registers (exception) */
151#define SRR1    27
152#define IABR    1010    /* Instruction Address Breakpoint */
153#define DEC     22      /* Decrementer */
154#define EAR     282     /* External Address Register */
155
156#define MSSCR0   1014   /* Memory Subsystem Control Register */
157
158#define L2CR    1017    /* PPC 750 and 74xx L2 control register */
159
160#define L2CR_L2E   (1<<31)      /* enable */
161#define L2CR_L2I   (1<<21)      /* global invalidate */
162
163/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
164/* Oddly, the following L2CR bit defintions in 745x
165 * is different from that of 7400 and 7410.
166 * Though not used in 7400 and 7410, it is appeded with _745x just
167 * to be clarified.
168 */     
169#define L2CR_L2IO_745x  0x100000  /* (1<<20) L2 Instruction-Only  */
170#define L2CR_L2DO_745x  0x10000   /* (1<<16) L2 Data-Only */
171#define L2CR_LOCK_745x  (L2CR_L2IO_745x|L2CR_L2DO_745x)
172#define L2CR_L3OH0      0x00080000 /* 12:L3 output hold 0 */
173       
174#define L3CR    1018    /* PPC 7450/7455 L3 control register */
175#define L3CR_L3IO_745x  0x400000  /* (1<<22) L3 Instruction-Only */
176#define L3CR_L3DO_745x  0x40      /* (1<<6) L3 Data-Only */
177
178#define L3CR_LOCK_745x  (L3CR_L3IO_745x|L3CR_L3DO_745x)
179
180#define   L3CR_RESERVED           0x0438003a /* Reserved bits in L3CR */
181#define   L3CR_L3E                0x80000000 /* 0: L3 enable */
182#define   L3CR_L3PE               0x40000000 /* 1: L3 data parity checking enable */
183#define   L3CR_L3APE              0x20000000 /* 2: L3 address parity checking enable */
184#define   L3CR_L3SIZ              0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
185#define    L3SIZ_1M               0x00000000
186#define    L3SIZ_2M               0x10000000
187#define   L3CR_L3CLKEN            0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
188#define   L3CR_L3CLK              0x03800000 /* 6-8: L3 clock ratio */
189#define    L3CLK_60               0x00000000 /* core clock / 6   */
190#define    L3CLK_20               0x01000000 /*            / 2   */
191#define    L3CLK_25               0x01800000 /*            / 2.5 */
192#define    L3CLK_30               0x02000000 /*            / 3   */
193#define    L3CLK_35               0x02800000 /*            / 3.5 */
194#define    L3CLK_40               0x03000000 /*            / 4   */
195#define    L3CLK_50               0x03800000 /*            / 5   */
196#define   L3CR_L3IO               0x00400000 /* 9: L3 instruction-only mode */
197#define   L3CR_L3SPO              0x00040000 /* 13: L3 sample point override */
198#define   L3CR_L3CKSP             0x00030000 /* 14-15: L3 clock sample point */
199#define    L3CKSP_2               0x00000000 /* 2 clocks */
200#define    L3CKSP_3               0x00010000 /* 3 clocks */
201#define    L3CKSP_4               0x00020000 /* 4 clocks */
202#define    L3CKSP_5               0x00030000 /* 5 clocks */
203#define   L3CR_L3PSP              0x0000e000 /* 16-18: L3 P-clock sample point */
204#define    L3PSP_0                0x00000000 /* 0 clocks */
205#define    L3PSP_1                0x00002000 /* 1 clocks */
206#define    L3PSP_2                0x00004000 /* 2 clocks */
207#define    L3PSP_3                0x00006000 /* 3 clocks */
208#define    L3PSP_4                0x00008000 /* 4 clocks */
209#define    L3PSP_5                0x0000a000 /* 5 clocks */
210#define   L3CR_L3REP              0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
211#define   L3CR_L3HWF              0x00000800 /* 20: L3 hardware flush */
212#define   L3CR_L3I                0x00000400 /* 21: L3 global invaregisters.h.orig
213lidate */
214#define   L3CR_L3RT               0x00000300 /* 22-23: L3 SRAM type */
215#define    L3RT_MSUG2_DDR         0x00000000 /* MSUG2 DDR SRAM */
216#define    L3RT_PIPELINE_LATE     0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
217#define    L3RT_PB2_SRAM          0x00000300 /* PB2 SRAM */
218#define   L3CR_L3NIRCA            0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
219#define   L3CR_L3DO               0x00000040 /* 25: L3 data-only mode */
220#define   L3CR_PMEN               0x00000004 /* 29: Private memory enable */
221#define   L3CR_PMSIZ              0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
222
223#define THRM1   1020
224#define THRM2   1021
225#define THRM3   1022
226#define THRM1_TIN (1<<(31-0))
227#define THRM1_TIV (1<<(31-1))
228#define THRM1_THRES (0x7f<<(31-8))
229#define THRM1_TID (1<<(31-29))
230#define THRM1_TIE (1<<(31-30))
231#define THRM1_V   (1<<(31-31))
232#define THRM3_SITV (0x1fff << (31-30))
233#define THRM3_E   (1<<(31-31))
234
235/* Segment Registers */
236#define SR0     0
237#define SR1     1
238#define SR2     2
239#define SR3     3
240#define SR4     4
241#define SR5     5
242#define SR6     6
243#define SR7     7
244#define SR8     8
245#define SR9     9
246#define SR10    10
247#define SR11    11
248#define SR12    12
249#define SR13    13
250#define SR14    14
251#define SR15    15
252
253#ifndef ASM
254/*
255 *  Routines to access the time base register
256 */
257
258static inline unsigned long long PPC_Get_timebase_register( void )
259{
260  unsigned long tbr_low;
261  unsigned long tbr_high;
262  unsigned long tbr_high_old;
263  unsigned long long tbr;
264
265  do {
266    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
267    asm volatile( "mftb  %0" : "=r" (tbr_low));
268    asm volatile( "mftbu %0" : "=r" (tbr_high));
269  } while ( tbr_high_old != tbr_high );
270
271  tbr = tbr_high;
272  tbr <<= 32;
273  tbr |= tbr_low;
274  return tbr;
275}
276
277static inline  void PPC_Set_timebase_register (unsigned long long tbr)
278{
279  unsigned long tbr_low;
280  unsigned long tbr_high;
281
282  tbr_low = (tbr & 0xffffffff) ;
283  tbr_high = (tbr >> 32) & 0xffffffff;
284  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
285  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
286 
287}
288#endif
289
290#define _CPU_MSR_GET( _msr_value ) \
291  do { \
292    _msr_value = 0; \
293    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
294  } while (0)
295
296#define _CPU_MSR_SET( _msr_value ) \
297{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
298
299#define _CPU_ISR_Disable( _isr_cookie ) \
300  { register unsigned int _disable_mask = MSR_EE; \
301    _isr_cookie = 0; \
302    asm volatile ( \
303        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
304        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
305        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
306        ); \
307  }
308
309
310/*
311 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
312 *  This indicates the end of an RTEMS critical section.  The parameter
313 *  _isr_cookie is not modified.
314 */
315
316#define _CPU_ISR_Enable( _isr_cookie )  \
317  { \
318     asm volatile ( "mtmsr %0" : \
319                   "=r" ((_isr_cookie)) : \
320                   "0" ((_isr_cookie))); \
321  }
322
323/*
324 *  This temporarily restores the interrupt to _isr_cookie before immediately
325 *  disabling them again.  This is used to divide long RTEMS critical
326 *  sections into two or more parts.  The parameter _isr_cookie is not
327 *  modified.
328 *
329 *  NOTE:  The version being used is not very optimized but it does
330 *         not trip a problem in gcc where the disable mask does not
331 *         get loaded.  Check this for future (post 10/97 gcc versions.
332 */
333
334#define _CPU_ISR_Flash( _isr_cookie ) \
335  { register unsigned int _disable_mask = MSR_EE; \
336    asm volatile ( \
337      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
338      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
339      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
340    ); \
341  }
342
343
344/* end of ISR handler macros */
345
346/*
347 *  Simple spin delay in microsecond units for device drivers.
348 *  This is very dependent on the clock speed of the target.
349 */
350
351#define CPU_Get_timebase_low( _value ) \
352    asm volatile( "mftb  %0" : "=r" (_value) )
353
354#define rtems_bsp_delay( _microseconds ) \
355  do { \
356    uint32_t   start, ticks, now; \
357    CPU_Get_timebase_low( start ) ; \
358    ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
359    do \
360      CPU_Get_timebase_low( now ) ; \
361    while (now - start < ticks); \
362  } while (0)
363
364#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
365  do { \
366    uint32_t   start, now; \
367    CPU_Get_timebase_low( start ); \
368    do \
369      CPU_Get_timebase_low( now ); \
370    while (now - start < (_cycles)); \
371  } while (0)
372
373#define PPC_Set_decrementer( _clicks ) \
374  do { \
375    asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
376  } while (0)
377
378#define PPC_Get_decrementer( _clicks ) \
379    asm volatile( "mfdec  %0" : "=r" (_clicks) )
380
381#ifdef __cplusplus
382}
383#endif
384
385#endif /* __rtems_powerpc_registers_h */
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