source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ 3c6fe2e

4.104.114.9
Last change on this file since 3c6fe2e was 3c6fe2e, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 14, 2008 at 8:46:06 AM

added haleakala BSP contributed by Michael Hamel

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File size: 13.7 KB
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1/*
2 * This file contains some powerpc MSR and registers access definitions.
3 *
4 * COPYRIGHT (C) 1999  Eric Valette (valette@crf.canon.fr)
5 *                     Canon Centre Recherche France.
6 *
7 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited
9 *
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef _RTEMS_POWERPC_REGISTERS_H
19#define _RTEMS_POWERPC_REGISTERS_H
20
21/* Bit encodings for Machine State Register (MSR) */
22#define MSR_VE          (1<<25)         /* Alti-Vec enable (7400+) */
23#define MSR_POW         (1<<18)         /* Enable Power Management */
24#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
25#define MSR_CE          (1<<17)         /* BookE critical interrupt */
26#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
27#define MSR_EE          (1<<15)         /* External Interrupt enable */
28#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
29#define MSR_FP          (1<<13)         /* Floating Point enable */
30#define MSR_ME          (1<<12)         /* Machine Check enable */
31#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
32#define MSR_SE          (1<<10)         /* Single Step */
33#define MSR_BE          (1<<9)          /* Branch Trace */
34#define MSR_DE          (1<<9)          /* BookE debug exception */
35#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
36#define MSR_E300_CE     (1<<7)          /* e300 critical interrupt */
37#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
38#define MSR_IR          (1<<5)          /* Instruction MMU enable */
39#define MSR_DR          (1<<4)          /* Data MMU enable */
40#define MSR_RI          (1<<1)          /* Recoverable Exception */
41#define MSR_LE          (1<<0)          /* Little-Endian enable */
42
43#define MSR_            MSR_ME|MSR_RI
44#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
45#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
46
47/* Bit encodings for Hardware Implementation Register (HID0)
48   on PowerPC 603, 604, etc. processors (not 601). */
49
50/* WARNING: HID0/HID1 are *truely* implementation dependent!
51 *          you *cannot* rely on the same bits to be present,
52 *          at the same place or even in the same register
53 *          on different CPU familys.
54 *          E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
55 *          on the 7450s. IFFT is XBSEN on 7450 and so on...
56 */
57#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
58#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
59#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
60#define HID0_SBCLK      (1<<27)
61#define HID0_TBEN       (1<<26)         /* 7455:this bit must be set
62                                         * and TBEN signal must be asserted
63                                         * to enable the time base and
64                                         * decrementer.
65                                         */
66#define HID0_EICE       (1<<26)
67#define HID0_ECLK       (1<<25)
68#define HID0_PAR        (1<<24)
69#define HID0_DOZE       (1<<23)
70/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !!          */
71#define HID0_7455_HIGH_BAT_EN (1<<23)
72
73#define HID0_NAP        (1<<22)
74#define HID0_SLEEP      (1<<21)
75#define HID0_DPM        (1<<20)
76#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
77#define HID0_DCE        (1<<14)         /* Data Cache Enable */
78#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
79#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
80#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
81#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
82/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
83#define HID0_7455_XBSEN       (1<<8)
84#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
85#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
86/* S.K. Feng 10/03, added for MPC7455 */
87#define HID0_LRSTK      (1<<4)          /* Link register stack enable (7455) */
88#define HID0_FOLD       (1<<3)          /* Branch folding enable (7455) */
89
90#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
91#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
92
93/* fpscr settings */
94#define FPSCR_FX        (1<<31)
95#define FPSCR_FEX       (1<<30)
96
97#define _MACH_prep     1
98#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
99#define _MACH_chrp     4 /* chrp machine */
100#define _MACH_mbx      8 /* Motorola MBX board */
101#define _MACH_apus    16 /* amiga with phase5 powerup */
102#define _MACH_fads    32 /* Motorola FADS board */
103
104/* see residual.h for these */
105#define _PREP_Motorola 0x01  /* motorola prep */
106#define _PREP_Firm     0x02  /* firmworks prep */
107#define _PREP_IBM      0x00  /* ibm prep */
108#define _PREP_Bull     0x03  /* bull prep */
109
110/* these are arbitrary */
111#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
112#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
113
114#define _GLOBAL(n)\
115        .globl n;\
116n:
117
118#define TBRU    269     /* Time base Upper/Lower (Reading) */
119#define TBRL    268
120#define TBWU    285     /* Time base Upper/Lower (Writing) */
121#define TBWL    284
122#define XER     1
123#define LR      8
124#define CTR     9
125#define HID0    1008    /* Hardware Implementation */
126#define HID1    1009    /* Hardware Implementation */
127#define DABR    1013    /* Data Access Breakpoint  */
128#define PVR     287     /* Processor Version */
129#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
130#define IBAT0L  529
131#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
132#define IBAT1L  531
133#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
134#define IBAT2L  533
135#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
136#define IBAT3L  535
137
138/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
139#define IBAT4U  560     /* Instruction BAT #0 Upper/Lower */
140#define IBAT4L  561
141#define IBAT5U  562     /* Instruction BAT #1 Upper/Lower */
142#define IBAT5L  563
143#define IBAT6U  564     /* Instruction BAT #2 Upper/Lower */
144#define IBAT6L  565
145#define IBAT7U  566     /* Instruction BAT #3 Upper/Lower */
146#define IBAT7L  567
147
148#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
149#define DBAT0L  537
150#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
151#define DBAT1L  539
152#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
153#define DBAT2L  541
154#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
155#define DBAT3L  543
156
157/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
158#define DBAT4U  568     /* Instruction BAT #0 Upper/Lower */
159#define DBAT4L  569
160#define DBAT5U  570     /* Instruction BAT #1 Upper/Lower */
161#define DBAT5L  571
162#define DBAT6U  572     /* Instruction BAT #2 Upper/Lower */
163#define DBAT6L  573
164#define DBAT7U  574     /* Instruction BAT #3 Upper/Lower */
165#define DBAT7L  575
166
167#define DMISS   976     /* TLB Lookup/Refresh registers */
168#define DCMP    977
169#define HASH1   978
170#define HASH2   979
171#define IMISS   980
172#define ICMP    981
173#define RPA     982
174#define SDR1    25      /* MMU hash base register */
175#define DAR     19      /* Data Address Register */
176#define SPR0    272     /* Supervisor Private Registers */
177#define SPRG0   272
178#define SPR1    273
179#define SPRG1   273
180#define SPR2    274
181#define SPRG2   274
182#define SPR3    275
183#define SPRG3   275
184#define SPRG4   276
185#define SPRG5   277
186#define SPRG6   278
187#define SPRG7   279
188#define USPRG0  256
189#define DSISR   18
190#define SRR0    26      /* Saved Registers (exception) */
191#define SRR1    27
192#define IABR    1010    /* Instruction Address Breakpoint */
193#define DEC     22      /* Decrementer */
194#define EAR     282     /* External Address Register */
195
196#define MSSCR0   1014   /* Memory Subsystem Control Register */
197
198#define L2CR    1017    /* PPC 750 and 74xx L2 control register */
199
200#define L2CR_L2E   (1<<31)      /* enable */
201#define L2CR_L2I   (1<<21)      /* global invalidate */
202
203/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
204/* Oddly, the following L2CR bit defintions in 745x
205 * is different from that of 7400 and 7410.
206 * Though not used in 7400 and 7410, it is appeded with _745x just
207 * to be clarified.
208 */     
209#define L2CR_L2IO_745x  0x100000  /* (1<<20) L2 Instruction-Only  */
210#define L2CR_L2DO_745x  0x10000   /* (1<<16) L2 Data-Only */
211#define L2CR_LOCK_745x  (L2CR_L2IO_745x|L2CR_L2DO_745x)
212#define L2CR_L3OH0      0x00080000 /* 12:L3 output hold 0 */
213       
214#define L3CR    1018    /* PPC 7450/7455 L3 control register */
215#define L3CR_L3IO_745x  0x400000  /* (1<<22) L3 Instruction-Only */
216#define L3CR_L3DO_745x  0x40      /* (1<<6) L3 Data-Only */
217
218#define L3CR_LOCK_745x  (L3CR_L3IO_745x|L3CR_L3DO_745x)
219
220#define   L3CR_RESERVED           0x0438003a /* Reserved bits in L3CR */
221#define   L3CR_L3E                0x80000000 /* 0: L3 enable */
222#define   L3CR_L3PE               0x40000000 /* 1: L3 data parity checking enable */
223#define   L3CR_L3APE              0x20000000 /* 2: L3 address parity checking enable */
224#define   L3CR_L3SIZ              0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
225#define    L3SIZ_1M               0x00000000
226#define    L3SIZ_2M               0x10000000
227#define   L3CR_L3CLKEN            0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
228#define   L3CR_L3CLK              0x03800000 /* 6-8: L3 clock ratio */
229#define    L3CLK_60               0x00000000 /* core clock / 6   */
230#define    L3CLK_20               0x01000000 /*            / 2   */
231#define    L3CLK_25               0x01800000 /*            / 2.5 */
232#define    L3CLK_30               0x02000000 /*            / 3   */
233#define    L3CLK_35               0x02800000 /*            / 3.5 */
234#define    L3CLK_40               0x03000000 /*            / 4   */
235#define    L3CLK_50               0x03800000 /*            / 5   */
236#define   L3CR_L3IO               0x00400000 /* 9: L3 instruction-only mode */
237#define   L3CR_L3SPO              0x00040000 /* 13: L3 sample point override */
238#define   L3CR_L3CKSP             0x00030000 /* 14-15: L3 clock sample point */
239#define    L3CKSP_2               0x00000000 /* 2 clocks */
240#define    L3CKSP_3               0x00010000 /* 3 clocks */
241#define    L3CKSP_4               0x00020000 /* 4 clocks */
242#define    L3CKSP_5               0x00030000 /* 5 clocks */
243#define   L3CR_L3PSP              0x0000e000 /* 16-18: L3 P-clock sample point */
244#define    L3PSP_0                0x00000000 /* 0 clocks */
245#define    L3PSP_1                0x00002000 /* 1 clocks */
246#define    L3PSP_2                0x00004000 /* 2 clocks */
247#define    L3PSP_3                0x00006000 /* 3 clocks */
248#define    L3PSP_4                0x00008000 /* 4 clocks */
249#define    L3PSP_5                0x0000a000 /* 5 clocks */
250#define   L3CR_L3REP              0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
251#define   L3CR_L3HWF              0x00000800 /* 20: L3 hardware flush */
252#define   L3CR_L3I                0x00000400 /* 21: L3 global invaregisters.h.orig
253lidate */
254#define   L3CR_L3RT               0x00000300 /* 22-23: L3 SRAM type */
255#define    L3RT_MSUG2_DDR         0x00000000 /* MSUG2 DDR SRAM */
256#define    L3RT_PIPELINE_LATE     0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
257#define    L3RT_PB2_SRAM          0x00000300 /* PB2 SRAM */
258#define   L3CR_L3NIRCA            0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
259#define   L3CR_L3DO               0x00000040 /* 25: L3 data-only mode */
260#define   L3CR_PMEN               0x00000004 /* 29: Private memory enable */
261#define   L3CR_PMSIZ              0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
262
263#define THRM1   1020
264#define THRM2   1021
265#define THRM3   1022
266#define THRM1_TIN (1<<(31-0))
267#define THRM1_TIV (1<<(31-1))
268#define THRM1_THRES (0x7f<<(31-8))
269#define THRM1_TID (1<<(31-29))
270#define THRM1_TIE (1<<(31-30))
271#define THRM1_V   (1<<(31-31))
272#define THRM3_SITV (0x1fff << (31-30))
273#define THRM3_E   (1<<(31-31))
274
275/* Segment Registers */
276#define SR0     0
277#define SR1     1
278#define SR2     2
279#define SR3     3
280#define SR4     4
281#define SR5     5
282#define SR6     6
283#define SR7     7
284#define SR8     8
285#define SR9     9
286#define SR10    10
287#define SR11    11
288#define SR12    12
289#define SR13    13
290#define SR14    14
291#define SR15    15
292
293#define BOOKE_DECAR     54
294
295#define PPC405_TSR      0x3D8
296#define BOOKE_TSR       336
297#define BOOKE_TSR_ENW           (1<<31)
298#define BOOKE_TSR_WIS           (1<<30)
299#define BOOKE_TSR_DIS           (1<<27)
300#define BOOKE_TSR_FIS           (1<<26)
301
302#define PPC405_TCR      0x3DA
303#define BOOKE_TCR       340
304#define BOOKE_TCR_WP(x)         (((x)&3)<<30)
305#define BOOKE_TCR_WRC(x)        (((x)&3)<<28)
306#define BOOKE_TCR_WIE           (1<<27)
307#define BOOKE_TCR_DIE           (1<<26)
308#define BOOKE_TCR_FP(x)         (((x)&3)<<24)
309#define BOOKE_TCR_FIE           (1<<23)
310#define BOOKE_TCR_ARE           (1<<22)
311#define BOOKE_TCR_WPEXT(x)      (((x)&0xf)<<17)
312#define BOOKE_TCR_FPEXT(x)      (((x)&0xf)<<13)
313
314/**
315 * @brief Default value for the interrupt disable mask.
316 *
317 * The interrupt disable mask is stored in the SPRG0 (= special purpose
318 * register 272).
319 */
320#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
321
322#ifndef ASM
323
324#include <stdint.h>
325
326#ifdef __cplusplus
327extern "C" {
328#endif /* __cplusplus */
329
330#define _CPU_MSR_GET( _msr_value ) \
331  do { \
332    _msr_value = 0; \
333    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
334  } while (0)
335
336#define _CPU_MSR_SET( _msr_value ) \
337{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
338
339static inline void ppc_interrupt_set_disable_mask( uint32_t mask)
340{
341  asm volatile (
342    "mtspr 272, %0"
343    :
344    : "r" (mask)
345  );
346}
347
348static inline uint32_t ppc_interrupt_disable()
349{
350  uint32_t level;
351  uint32_t mask;
352
353  asm volatile (
354    "mfmsr %0;"
355    "mfspr %1, 272;"
356    "andc %1, %0, %1;"
357    "mtmsr %1"
358    : "=r" (level), "=r" (mask)
359  );
360
361  return level;
362}
363
364static inline void ppc_interrupt_enable( uint32_t level)
365{
366  asm volatile (
367    "mtmsr %0"
368    :
369    : "r" (level)
370  );
371}
372
373static inline void ppc_interrupt_flash( uint32_t level)
374{
375  uint32_t current_level;
376
377  asm volatile (
378    "mfmsr %0;"
379    "mtmsr %1;"
380    "mtmsr %0"
381    : "=&r" (current_level)
382    : "r" (level)
383  );
384}
385
386#define _CPU_ISR_Disable( _isr_cookie ) \
387  do { \
388    _isr_cookie = ppc_interrupt_disable(); \
389  } while (0)
390
391/*
392 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
393 *  This indicates the end of an RTEMS critical section.  The parameter
394 *  _isr_cookie is not modified.
395 */
396
397#define _CPU_ISR_Enable( _isr_cookie )  \
398  ppc_interrupt_enable( _isr_cookie)
399
400/*
401 *  This temporarily restores the interrupt to _isr_cookie before immediately
402 *  disabling them again.  This is used to divide long RTEMS critical
403 *  sections into two or more parts.  The parameter _isr_cookie is not
404 *  modified.
405 *
406 *  NOTE:  The version being used is not very optimized but it does
407 *         not trip a problem in gcc where the disable mask does not
408 *         get loaded.  Check this for future (post 10/97 gcc versions.
409 */
410
411#define _CPU_ISR_Flash( _isr_cookie ) \
412  ppc_interrupt_flash( _isr_cookie)
413
414/* end of ISR handler macros */
415
416#ifdef __cplusplus
417}
418#endif /* __cplusplus */
419
420#endif /* ASM */
421
422#endif /* _RTEMS_POWERPC_REGISTERS_H */
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