source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ 390dadd

4.115
Last change on this file since 390dadd was 390dadd, checked in by Sebastian Huber <sebastian.huber@…>, on 06/30/10 at 07:43:00

2010-06-30 Peter Dufault <dufault@…>

PR 1588/cpukit

  • rtems/powerpc/registers.h: Renamed defines SR0 .. SR15 in PPC_SR0 .. PPC_SR15.
  • Property mode set to 100644
File size: 14.8 KB
Line 
1/*
2 * This file contains some powerpc MSR and registers access definitions.
3 *
4 * COPYRIGHT (C) 1999  Eric Valette (valette@crf.canon.fr)
5 *                     Canon Centre Recherche France.
6 *
7 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited
9 *
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef _RTEMS_POWERPC_REGISTERS_H
19#define _RTEMS_POWERPC_REGISTERS_H
20
21/* Bit encodings for Machine State Register (MSR) */
22#define MSR_VE          (1<<25)         /* Alti-Vec enable (7400+) */
23#define MSR_POW         (1<<18)         /* Enable Power Management */
24#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
25#define MSR_CE          (1<<17)         /* BookE critical interrupt */
26#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
27#define MSR_EE          (1<<15)         /* External Interrupt enable */
28#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
29#define MSR_FP          (1<<13)         /* Floating Point enable */
30#define MSR_ME          (1<<12)         /* Machine Check enable */
31#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
32#define MSR_SE          (1<<10)         /* Single Step */
33#define MSR_BE          (1<<9)          /* Branch Trace */
34#define MSR_DE          (1<<9)          /* BookE debug exception */
35#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
36#define MSR_E300_CE     (1<<7)          /* e300 critical interrupt */
37#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
38#define MSR_IR          (1<<5)          /* Instruction MMU enable */
39#define MSR_DR          (1<<4)          /* Data MMU enable */
40#define MSR_RI          (1<<1)          /* Recoverable Exception */
41#define MSR_LE          (1<<0)          /* Little-Endian enable */
42
43/* Bit encodings for Hardware Implementation Register (HID0)
44   on PowerPC 603, 604, etc. processors (not 601). */
45
46/* WARNING: HID0/HID1 are *truely* implementation dependent!
47 *          you *cannot* rely on the same bits to be present,
48 *          at the same place or even in the same register
49 *          on different CPU familys.
50 *          E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
51 *          on the 7450s. IFFT is XBSEN on 7450 and so on...
52 */
53#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
54#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
55#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
56#define HID0_SBCLK      (1<<27)
57#define HID0_TBEN       (1<<26)         /* 7455:this bit must be set
58                                         * and TBEN signal must be asserted
59                                         * to enable the time base and
60                                         * decrementer.
61                                         */
62#define HID0_EICE       (1<<26)
63#define HID0_ECLK       (1<<25)
64#define HID0_PAR        (1<<24)
65#define HID0_DOZE       (1<<23)
66/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !!          */
67#define HID0_7455_HIGH_BAT_EN (1<<23)
68
69#define HID0_NAP        (1<<22)
70#define HID0_SLEEP      (1<<21)
71#define HID0_DPM        (1<<20)
72#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
73#define HID0_DCE        (1<<14)         /* Data Cache Enable */
74#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
75#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
76#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
77#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
78/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
79#define HID0_7455_XBSEN       (1<<8)
80#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
81#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
82/* S.K. Feng 10/03, added for MPC7455 */
83#define HID0_LRSTK      (1<<4)          /* Link register stack enable (7455) */
84#define HID0_FOLD       (1<<3)          /* Branch folding enable (7455) */
85
86#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
87#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
88
89/* fpscr settings */
90#define FPSCR_FX        (1<<31)
91#define FPSCR_FEX       (1<<30)
92
93#define _MACH_prep     1
94#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
95#define _MACH_chrp     4 /* chrp machine */
96#define _MACH_mbx      8 /* Motorola MBX board */
97#define _MACH_apus    16 /* amiga with phase5 powerup */
98#define _MACH_fads    32 /* Motorola FADS board */
99
100/* see residual.h for these */
101#define _PREP_Motorola 0x01  /* motorola prep */
102#define _PREP_Firm     0x02  /* firmworks prep */
103#define _PREP_IBM      0x00  /* ibm prep */
104#define _PREP_Bull     0x03  /* bull prep */
105
106/* these are arbitrary */
107#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
108#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
109
110#define _GLOBAL(n)\
111        .globl n;\
112n:
113
114#define TBRU    269     /* Time base Upper/Lower (Reading) */
115#define TBRL    268
116#define TBWU    285     /* Time base Upper/Lower (Writing) */
117#define TBWL    284
118#define XER     1
119#define LR      8
120#define CTR     9
121#define HID0    1008    /* Hardware Implementation */
122#define HID1    1009    /* Hardware Implementation */
123#define DABR    1013    /* Data Access Breakpoint  */
124#define PVR     287     /* Processor Version */
125#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
126#define IBAT0L  529
127#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
128#define IBAT1L  531
129#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
130#define IBAT2L  533
131#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
132#define IBAT3L  535
133
134/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
135#define IBAT4U  560     /* Instruction BAT #0 Upper/Lower */
136#define IBAT4L  561
137#define IBAT5U  562     /* Instruction BAT #1 Upper/Lower */
138#define IBAT5L  563
139#define IBAT6U  564     /* Instruction BAT #2 Upper/Lower */
140#define IBAT6L  565
141#define IBAT7U  566     /* Instruction BAT #3 Upper/Lower */
142#define IBAT7L  567
143
144#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
145#define DBAT0L  537
146#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
147#define DBAT1L  539
148#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
149#define DBAT2L  541
150#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
151#define DBAT3L  543
152
153/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
154#define DBAT4U  568     /* Instruction BAT #0 Upper/Lower */
155#define DBAT4L  569
156#define DBAT5U  570     /* Instruction BAT #1 Upper/Lower */
157#define DBAT5L  571
158#define DBAT6U  572     /* Instruction BAT #2 Upper/Lower */
159#define DBAT6L  573
160#define DBAT7U  574     /* Instruction BAT #3 Upper/Lower */
161#define DBAT7L  575
162
163#define DMISS   976     /* TLB Lookup/Refresh registers */
164#define DCMP    977
165#define HASH1   978
166#define HASH2   979
167#define IMISS   980
168#define ICMP    981
169#define RPA     982
170#define SDR1    25      /* MMU hash base register */
171#define DAR     19      /* Data Address Register */
172#define DEAR_BOOKE 61
173#define DEAR_405 981
174#define SPR0    272     /* Supervisor Private Registers */
175#define SPRG0   272
176#define SPR1    273
177#define SPRG1   273
178#define SPR2    274
179#define SPRG2   274
180#define SPR3    275
181#define SPRG3   275
182#define SPRG4   276
183#define SPRG5   277
184#define SPRG6   278
185#define SPRG7   279
186#define USPRG0  256
187#define DSISR   18
188#define SRR0    26      /* Saved Registers (exception) */
189#define SRR1    27
190#define IABR    1010    /* Instruction Address Breakpoint */
191#define DEC     22      /* Decrementer */
192#define EAR     282     /* External Address Register */
193
194#define MSSCR0   1014   /* Memory Subsystem Control Register */
195
196#define L2CR    1017    /* PPC 750 and 74xx L2 control register */
197
198#define L2CR_L2E   (1<<31)      /* enable */
199#define L2CR_L2I   (1<<21)      /* global invalidate */
200
201/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
202/* Oddly, the following L2CR bit defintions in 745x
203 * is different from that of 7400 and 7410.
204 * Though not used in 7400 and 7410, it is appeded with _745x just
205 * to be clarified.
206 */     
207#define L2CR_L2IO_745x  0x100000  /* (1<<20) L2 Instruction-Only  */
208#define L2CR_L2DO_745x  0x10000   /* (1<<16) L2 Data-Only */
209#define L2CR_LOCK_745x  (L2CR_L2IO_745x|L2CR_L2DO_745x)
210#define L2CR_L3OH0      0x00080000 /* 12:L3 output hold 0 */
211       
212#define L3CR    1018    /* PPC 7450/7455 L3 control register */
213#define L3CR_L3IO_745x  0x400000  /* (1<<22) L3 Instruction-Only */
214#define L3CR_L3DO_745x  0x40      /* (1<<6) L3 Data-Only */
215
216#define L3CR_LOCK_745x  (L3CR_L3IO_745x|L3CR_L3DO_745x)
217
218#define   L3CR_RESERVED           0x0438003a /* Reserved bits in L3CR */
219#define   L3CR_L3E                0x80000000 /* 0: L3 enable */
220#define   L3CR_L3PE               0x40000000 /* 1: L3 data parity checking enable */
221#define   L3CR_L3APE              0x20000000 /* 2: L3 address parity checking enable */
222#define   L3CR_L3SIZ              0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
223#define    L3SIZ_1M               0x00000000
224#define    L3SIZ_2M               0x10000000
225#define   L3CR_L3CLKEN            0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
226#define   L3CR_L3CLK              0x03800000 /* 6-8: L3 clock ratio */
227#define    L3CLK_60               0x00000000 /* core clock / 6   */
228#define    L3CLK_20               0x01000000 /*            / 2   */
229#define    L3CLK_25               0x01800000 /*            / 2.5 */
230#define    L3CLK_30               0x02000000 /*            / 3   */
231#define    L3CLK_35               0x02800000 /*            / 3.5 */
232#define    L3CLK_40               0x03000000 /*            / 4   */
233#define    L3CLK_50               0x03800000 /*            / 5   */
234#define   L3CR_L3IO               0x00400000 /* 9: L3 instruction-only mode */
235#define   L3CR_L3SPO              0x00040000 /* 13: L3 sample point override */
236#define   L3CR_L3CKSP             0x00030000 /* 14-15: L3 clock sample point */
237#define    L3CKSP_2               0x00000000 /* 2 clocks */
238#define    L3CKSP_3               0x00010000 /* 3 clocks */
239#define    L3CKSP_4               0x00020000 /* 4 clocks */
240#define    L3CKSP_5               0x00030000 /* 5 clocks */
241#define   L3CR_L3PSP              0x0000e000 /* 16-18: L3 P-clock sample point */
242#define    L3PSP_0                0x00000000 /* 0 clocks */
243#define    L3PSP_1                0x00002000 /* 1 clocks */
244#define    L3PSP_2                0x00004000 /* 2 clocks */
245#define    L3PSP_3                0x00006000 /* 3 clocks */
246#define    L3PSP_4                0x00008000 /* 4 clocks */
247#define    L3PSP_5                0x0000a000 /* 5 clocks */
248#define   L3CR_L3REP              0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
249#define   L3CR_L3HWF              0x00000800 /* 20: L3 hardware flush */
250#define   L3CR_L3I                0x00000400 /* 21: L3 global invaregisters.h.orig
251lidate */
252#define   L3CR_L3RT               0x00000300 /* 22-23: L3 SRAM type */
253#define    L3RT_MSUG2_DDR         0x00000000 /* MSUG2 DDR SRAM */
254#define    L3RT_PIPELINE_LATE     0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
255#define    L3RT_PB2_SRAM          0x00000300 /* PB2 SRAM */
256#define   L3CR_L3NIRCA            0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
257#define   L3CR_L3DO               0x00000040 /* 25: L3 data-only mode */
258#define   L3CR_PMEN               0x00000004 /* 29: Private memory enable */
259#define   L3CR_PMSIZ              0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
260
261#define THRM1   1020
262#define THRM2   1021
263#define THRM3   1022
264#define THRM1_TIN (1<<(31-0))
265#define THRM1_TIV (1<<(31-1))
266#define THRM1_THRES (0x7f<<(31-8))
267#define THRM1_TID (1<<(31-29))
268#define THRM1_TIE (1<<(31-30))
269#define THRM1_V   (1<<(31-31))
270#define THRM3_SITV (0x1fff << (31-30))
271#define THRM3_E   (1<<(31-31))
272
273/* Segment Registers */
274#define PPC_SR0 0
275#define PPC_SR1 1
276#define PPC_SR2 2
277#define PPC_SR3 3
278#define PPC_SR4 4
279#define PPC_SR5 5
280#define PPC_SR6 6
281#define PPC_SR7 7
282#define PPC_SR8 8
283#define PPC_SR9 9
284#define PPC_SR10        10
285#define PPC_SR11        11
286#define PPC_SR12        12
287#define PPC_SR13        13
288#define PPC_SR14        14
289#define PPC_SR15        15
290
291#define BOOKE_DECAR     54
292
293#define PPC405_TSR      0x3D8
294#define BOOKE_TSR       336
295#define BOOKE_TSR_ENW           (1<<31)
296#define BOOKE_TSR_WIS           (1<<30)
297#define BOOKE_TSR_DIS           (1<<27)
298#define BOOKE_TSR_FIS           (1<<26)
299
300#define PPC405_TCR      0x3DA
301#define BOOKE_TCR       340
302#define BOOKE_TCR_WP(x)         (((x)&3)<<30)
303#define BOOKE_TCR_WP_MASK       (3<<30)
304#define BOOKE_TCR_WRC(x)        (((x)&3)<<28)
305#define BOOKE_TCR_WRC_MASK      (3<<28)
306#define BOOKE_TCR_WIE           (1<<27)
307#define BOOKE_TCR_DIE           (1<<26)
308#define BOOKE_TCR_FP(x)         (((x)&3)<<24)
309#define BOOKE_TCR_FIE           (1<<23)
310#define BOOKE_TCR_ARE           (1<<22)
311#define BOOKE_TCR_WPEXT(x)      (((x)&0xf)<<17)
312#define BOOKE_TCR_WPEXT_MASK    (0xf<<17)
313#define BOOKE_TCR_FPEXT(x)      (((x)&0xf)<<13)
314#define BOOKE_TCR_FPEXT_MASK    (0xf<<13)
315
316#define BOOKE_PID 48
317
318/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */
319
320#define FREESCALE_EIS_MAS0 624
321#define FREESCALE_EIS_MAS1 625
322#define FREESCALE_EIS_MAS2 626
323#define FREESCALE_EIS_MAS3 627
324#define FREESCALE_EIS_MAS4 628
325#define FREESCALE_EIS_MAS5 629
326#define FREESCALE_EIS_MAS6 630
327#define FREESCALE_EIS_MAS7 944
328#define FREESCALE_EIS_MMUCFG 1015
329#define FREESCALE_EIS_MMUCSR0 1012
330#define FREESCALE_EIS_PID0 48
331#define FREESCALE_EIS_PID1 633
332#define FREESCALE_EIS_PID2 634
333#define FREESCALE_EIS_TLB0CFG 688
334#define FREESCALE_EIS_TLB1CFG 689
335
336/* Freescale Book E Implementation Standards (EIS): L1 Cache */
337
338#define FREESCALE_EIS_L1CFG0 515
339#define FREESCALE_EIS_L1CFG1 516
340#define FREESCALE_EIS_L1CSR0 1010
341#define FREESCALE_EIS_L1CSR1 1011
342
343/**
344 * @brief Default value for the interrupt disable mask.
345 *
346 * The interrupt disable mask is stored in the SPRG0 (= special purpose
347 * register 272).
348 */
349#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
350
351#ifndef ASM
352
353#include <stdint.h>
354
355#ifdef __cplusplus
356extern "C" {
357#endif /* __cplusplus */
358
359#define _CPU_MSR_GET( _msr_value ) \
360  do { \
361    _msr_value = 0; \
362    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
363  } while (0)
364
365#define _CPU_MSR_SET( _msr_value ) \
366{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
367
368static inline void ppc_interrupt_set_disable_mask( uint32_t mask )
369{
370  asm volatile (
371    "mtspr 272, %0"
372    :
373    : "r" (mask)
374  );
375}
376
377static inline uint32_t ppc_interrupt_get_disable_mask( void )
378{
379  uint32_t mask;
380
381  asm volatile (
382    "mfspr %0, 272"
383    : "=r" (mask)
384  );
385
386  return mask;
387}
388
389static inline uint32_t ppc_interrupt_disable( void )
390{
391  uint32_t level;
392  uint32_t mask;
393
394  asm volatile (
395    "mfmsr %0;"
396    "mfspr %1, 272;"
397    "andc %1, %0, %1;"
398    "mtmsr %1"
399    : "=r" (level), "=r" (mask)
400  );
401
402  return level;
403}
404
405static inline void ppc_interrupt_enable( uint32_t level )
406{
407  asm volatile (
408    "mtmsr %0"
409    :
410    : "r" (level)
411  );
412}
413
414static inline void ppc_interrupt_flash( uint32_t level )
415{
416  uint32_t current_level;
417
418  asm volatile (
419    "mfmsr %0;"
420    "mtmsr %1;"
421    "mtmsr %0"
422    : "=&r" (current_level)
423    : "r" (level)
424  );
425}
426
427#define _CPU_ISR_Disable( _isr_cookie ) \
428  do { \
429    _isr_cookie = ppc_interrupt_disable(); \
430  } while (0)
431
432/*
433 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
434 *  This indicates the end of an RTEMS critical section.  The parameter
435 *  _isr_cookie is not modified.
436 */
437
438#define _CPU_ISR_Enable( _isr_cookie )  \
439  ppc_interrupt_enable(_isr_cookie)
440
441/*
442 *  This temporarily restores the interrupt to _isr_cookie before immediately
443 *  disabling them again.  This is used to divide long RTEMS critical
444 *  sections into two or more parts.  The parameter _isr_cookie is not
445 *  modified.
446 *
447 *  NOTE:  The version being used is not very optimized but it does
448 *         not trip a problem in gcc where the disable mask does not
449 *         get loaded.  Check this for future (post 10/97 gcc versions.
450 */
451
452#define _CPU_ISR_Flash( _isr_cookie ) \
453  ppc_interrupt_flash(_isr_cookie)
454
455/* end of ISR handler macros */
456
457#ifdef __cplusplus
458}
459#endif /* __cplusplus */
460
461#endif /* ASM */
462
463#endif /* _RTEMS_POWERPC_REGISTERS_H */
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