source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ 2d7ae960

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1/*
2 * This file contains some powerpc MSR and registers access definitions.
3 *
4 * COPYRIGHT (C) 1999  Eric Valette (valette@crf.canon.fr)
5 *                     Canon Centre Recherche France.
6 *
7 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited
9 *
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 */
15
16#ifndef _RTEMS_POWERPC_REGISTERS_H
17#define _RTEMS_POWERPC_REGISTERS_H
18
19/* Bit encodings for Machine State Register (MSR) */
20#define MSR_UCLE        (1<<26)         /* User-mode cache lock enable (e500) */
21#define MSR_VE          (1<<25)         /* Alti-Vec enable (7400+) */
22#define MSR_SPE         (1<<25)         /* SPE enable (e500) */
23#define MSR_POW         (1<<18)         /* Enable Power Management */
24#define MSR_WE          (1<<18)         /* Wait state enable (e500) */
25#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
26#define MSR_CE          (1<<17)         /* BookE critical interrupt */
27#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
28#define MSR_EE          (1<<15)         /* External Interrupt enable */
29#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
30#define MSR_FP          (1<<13)         /* Floating Point enable */
31#define MSR_ME          (1<<12)         /* Machine Check enable */
32#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
33#define MSR_SE          (1<<10)         /* Single Step */
34#define MSR_UBLE        (1<<10)         /* User-mode BTB lock enable (e500) */
35#define MSR_BE          (1<<9)          /* Branch Trace */
36#define MSR_DE          (1<<9)          /* BookE debug exception */
37#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
38#define MSR_E300_CE     (1<<7)          /* e300 critical interrupt */
39#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
40#define MSR_IR          (1<<5)          /* Instruction MMU enable */
41#define MSR_DR          (1<<4)          /* Data MMU enable */
42#define MSR_IS          (1<<5)          /* Instruction address space */
43#define MSR_DS          (1<<4)          /* Data address space */
44#define MSR_PMM         (1<<2)          /* Performance monitor mark */
45#define MSR_RI          (1<<1)          /* Recoverable Exception */
46#define MSR_LE          (1<<0)          /* Little-Endian enable */
47
48/* Bit encodings for Hardware Implementation Register (HID0)
49   on PowerPC 603, 604, etc. processors (not 601). */
50
51/* WARNING: HID0/HID1 are *truely* implementation dependent!
52 *          you *cannot* rely on the same bits to be present,
53 *          at the same place or even in the same register
54 *          on different CPU familys.
55 *          E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
56 *          on the 7450s. IFFT is XBSEN on 7450 and so on...
57 */
58#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
59#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
60#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
61#define HID0_SBCLK      (1<<27)
62#define HID0_TBEN       (1<<26)         /* 7455:this bit must be set
63                                         * and TBEN signal must be asserted
64                                         * to enable the time base and
65                                         * decrementer.
66                                         */
67#define HID0_EICE       (1<<26)
68#define HID0_ECLK       (1<<25)
69#define HID0_PAR        (1<<24)
70#define HID0_DOZE       (1<<23)
71/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !!          */
72#define HID0_7455_HIGH_BAT_EN (1<<23)
73
74#define HID0_NAP        (1<<22)
75#define HID0_SLEEP      (1<<21)
76#define HID0_DPM        (1<<20)
77#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
78#define HID0_DCE        (1<<14)         /* Data Cache Enable */
79#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
80#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
81#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
82#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
83/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
84#define HID0_7455_XBSEN       (1<<8)
85#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
86#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
87/* S.K. Feng 10/03, added for MPC7455 */
88#define HID0_LRSTK      (1<<4)          /* Link register stack enable (7455) */
89#define HID0_FOLD       (1<<3)          /* Branch folding enable (7455) */
90
91#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
92#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
93
94/* fpscr settings */
95#define FPSCR_FX        (1<<31)
96#define FPSCR_FEX       (1<<30)
97
98#define _MACH_prep     1
99#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
100#define _MACH_chrp     4 /* chrp machine */
101#define _MACH_mbx      8 /* Motorola MBX board */
102#define _MACH_apus    16 /* amiga with phase5 powerup */
103#define _MACH_fads    32 /* Motorola FADS board */
104
105/* see residual.h for these */
106#define _PREP_Motorola 0x01  /* motorola prep */
107#define _PREP_Firm     0x02  /* firmworks prep */
108#define _PREP_IBM      0x00  /* ibm prep */
109#define _PREP_Bull     0x03  /* bull prep */
110
111/* these are arbitrary */
112#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
113#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
114
115#define _GLOBAL(n)\
116        .globl n;\
117n:
118
119#define TBRU    269     /* Time base Upper/Lower (Reading) */
120#define TBRL    268
121#define TBWU    285     /* Time base Upper/Lower (Writing) */
122#define TBWL    284
123#define PPC_XER 1
124#define PPC_LR  8
125#define PPC_CTR 9
126#define HID0    1008    /* Hardware Implementation 0 */
127#define HID1    1009    /* Hardware Implementation 1 */
128#define HID2    1011    /* Hardware Implementation 2 */
129#define DABR    1013    /* Data Access Breakpoint  */
130#define PPC_PVR 287     /* Processor Version */
131#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
132#define IBAT0L  529
133#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
134#define IBAT1L  531
135#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
136#define IBAT2L  533
137#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
138#define IBAT3L  535
139
140/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
141#define IBAT4U  560     /* Instruction BAT #4 Upper/Lower */
142#define IBAT4L  561
143#define IBAT5U  562     /* Instruction BAT #5 Upper/Lower */
144#define IBAT5L  563
145#define IBAT6U  564     /* Instruction BAT #6 Upper/Lower */
146#define IBAT6L  565
147#define IBAT7U  566     /* Instruction BAT #7 Upper/Lower */
148#define IBAT7L  567
149
150#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
151#define DBAT0L  537
152#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
153#define DBAT1L  539
154#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
155#define DBAT2L  541
156#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
157#define DBAT3L  543
158
159/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
160#define DBAT4U  568     /* Instruction BAT #4 Upper/Lower */
161#define DBAT4L  569
162#define DBAT5U  570     /* Instruction BAT #5 Upper/Lower */
163#define DBAT5L  571
164#define DBAT6U  572     /* Instruction BAT #6 Upper/Lower */
165#define DBAT6L  573
166#define DBAT7U  574     /* Instruction BAT #7 Upper/Lower */
167#define DBAT7L  575
168
169#define DMISS   976     /* TLB Lookup/Refresh registers */
170#define DCMP    977
171#define HASH1   978
172#define HASH2   979
173#define IMISS   980
174#define ICMP    981
175#define PPC_RPA 982
176#define SDR1    25      /* MMU hash base register */
177#define PPC_DAR 19      /* Data Address Register */
178#define DEAR_BOOKE 61
179#define DEAR_405 981
180#define SPR0    272     /* Supervisor Private Registers */
181#define SPRG0   272
182#define SPR1    273
183#define SPRG1   273
184#define SPR2    274
185#define SPRG2   274
186#define SPR3    275
187#define SPRG3   275
188#define SPRG4   276
189#define SPRG5   277
190#define SPRG6   278
191#define SPRG7   279
192#define USPRG0  256
193#define DSISR   18
194#define SRR0    26      /* Saved Registers (exception) */
195#define SRR1    27
196#define IABR    1010    /* Instruction Address Breakpoint */
197#define PPC_DEC 22      /* Decrementer */
198#define PPC_EAR 282     /* External Address Register */
199
200#define MSSCR0   1014   /* Memory Subsystem Control Register */
201
202#define L2CR    1017    /* PPC 750 and 74xx L2 control register */
203
204#define L2CR_L2E   (1<<31)      /* enable */
205#define L2CR_L2I   (1<<21)      /* global invalidate */
206
207/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
208/* Oddly, the following L2CR bit defintions in 745x
209 * is different from that of 7400 and 7410.
210 * Though not used in 7400 and 7410, it is appeded with _745x just
211 * to be clarified.
212 */     
213#define L2CR_L2IO_745x  0x100000  /* (1<<20) L2 Instruction-Only  */
214#define L2CR_L2DO_745x  0x10000   /* (1<<16) L2 Data-Only */
215#define L2CR_LOCK_745x  (L2CR_L2IO_745x|L2CR_L2DO_745x)
216#define L2CR_L3OH0      0x00080000 /* 12:L3 output hold 0 */
217       
218#define L3CR    1018    /* PPC 7450/7455 L3 control register */
219#define L3CR_L3IO_745x  0x400000  /* (1<<22) L3 Instruction-Only */
220#define L3CR_L3DO_745x  0x40      /* (1<<6) L3 Data-Only */
221
222#define L3CR_LOCK_745x  (L3CR_L3IO_745x|L3CR_L3DO_745x)
223
224#define   L3CR_RESERVED           0x0438003a /* Reserved bits in L3CR */
225#define   L3CR_L3E                0x80000000 /* 0: L3 enable */
226#define   L3CR_L3PE               0x40000000 /* 1: L3 data parity checking enable */
227#define   L3CR_L3APE              0x20000000 /* 2: L3 address parity checking enable */
228#define   L3CR_L3SIZ              0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
229#define    L3SIZ_1M               0x00000000
230#define    L3SIZ_2M               0x10000000
231#define   L3CR_L3CLKEN            0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
232#define   L3CR_L3CLK              0x03800000 /* 6-8: L3 clock ratio */
233#define    L3CLK_60               0x00000000 /* core clock / 6   */
234#define    L3CLK_20               0x01000000 /*            / 2   */
235#define    L3CLK_25               0x01800000 /*            / 2.5 */
236#define    L3CLK_30               0x02000000 /*            / 3   */
237#define    L3CLK_35               0x02800000 /*            / 3.5 */
238#define    L3CLK_40               0x03000000 /*            / 4   */
239#define    L3CLK_50               0x03800000 /*            / 5   */
240#define   L3CR_L3IO               0x00400000 /* 9: L3 instruction-only mode */
241#define   L3CR_L3SPO              0x00040000 /* 13: L3 sample point override */
242#define   L3CR_L3CKSP             0x00030000 /* 14-15: L3 clock sample point */
243#define    L3CKSP_2               0x00000000 /* 2 clocks */
244#define    L3CKSP_3               0x00010000 /* 3 clocks */
245#define    L3CKSP_4               0x00020000 /* 4 clocks */
246#define    L3CKSP_5               0x00030000 /* 5 clocks */
247#define   L3CR_L3PSP              0x0000e000 /* 16-18: L3 P-clock sample point */
248#define    L3PSP_0                0x00000000 /* 0 clocks */
249#define    L3PSP_1                0x00002000 /* 1 clocks */
250#define    L3PSP_2                0x00004000 /* 2 clocks */
251#define    L3PSP_3                0x00006000 /* 3 clocks */
252#define    L3PSP_4                0x00008000 /* 4 clocks */
253#define    L3PSP_5                0x0000a000 /* 5 clocks */
254#define   L3CR_L3REP              0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
255#define   L3CR_L3HWF              0x00000800 /* 20: L3 hardware flush */
256#define   L3CR_L3I                0x00000400 /* 21: L3 global invaregisters.h.orig
257lidate */
258#define   L3CR_L3RT               0x00000300 /* 22-23: L3 SRAM type */
259#define    L3RT_MSUG2_DDR         0x00000000 /* MSUG2 DDR SRAM */
260#define    L3RT_PIPELINE_LATE     0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
261#define    L3RT_PB2_SRAM          0x00000300 /* PB2 SRAM */
262#define   L3CR_L3NIRCA            0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
263#define   L3CR_L3DO               0x00000040 /* 25: L3 data-only mode */
264#define   L3CR_PMEN               0x00000004 /* 29: Private memory enable */
265#define   L3CR_PMSIZ              0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
266
267#define THRM1   1020
268#define THRM2   1021
269#define THRM3   1022
270#define THRM1_TIN (1<<(31-0))
271#define THRM1_TIV (1<<(31-1))
272#define THRM1_THRES (0x7f<<(31-8))
273#define THRM1_TID (1<<(31-29))
274#define THRM1_TIE (1<<(31-30))
275#define THRM1_V   (1<<(31-31))
276#define THRM3_SITV (0x1fff << (31-30))
277#define THRM3_E   (1<<(31-31))
278
279/* Segment Registers */
280#define PPC_SR0 0
281#define PPC_SR1 1
282#define PPC_SR2 2
283#define PPC_SR3 3
284#define PPC_SR4 4
285#define PPC_SR5 5
286#define PPC_SR6 6
287#define PPC_SR7 7
288#define PPC_SR8 8
289#define PPC_SR9 9
290#define PPC_SR10        10
291#define PPC_SR11        11
292#define PPC_SR12        12
293#define PPC_SR13        13
294#define PPC_SR14        14
295#define PPC_SR15        15
296
297#define BOOKE_DECAR     54
298
299#define PPC405_TSR      0x3D8
300#define BOOKE_TSR       336
301#define BOOKE_TSR_ENW           (1<<31)
302#define BOOKE_TSR_WIS           (1<<30)
303#define BOOKE_TSR_DIS           (1<<27)
304#define BOOKE_TSR_FIS           (1<<26)
305
306#define PPC405_TCR      0x3DA
307#define BOOKE_TCR       340
308#define BOOKE_TCR_WP(x)         (((x)&3)<<30)
309#define BOOKE_TCR_WP_MASK       (3<<30)
310#define BOOKE_TCR_WRC(x)        (((x)&3)<<28)
311#define BOOKE_TCR_WRC_MASK      (3<<28)
312#define BOOKE_TCR_WIE           (1<<27)
313#define BOOKE_TCR_DIE           (1<<26)
314#define BOOKE_TCR_FP(x)         (((x)&3)<<24)
315#define BOOKE_TCR_FIE           (1<<23)
316#define BOOKE_TCR_ARE           (1<<22)
317#define BOOKE_TCR_WPEXT(x)      (((x)&0xf)<<17)
318#define BOOKE_TCR_WPEXT_MASK    (0xf<<17)
319#define BOOKE_TCR_FPEXT(x)      (((x)&0xf)<<13)
320#define BOOKE_TCR_FPEXT_MASK    (0xf<<13)
321
322#define BOOKE_PID 48
323#define BOOKE_ESR 62
324#define BOOKE_IVPR 63
325#define BOOKE_PIR 286
326#define BOOKE_DBSR 304
327#define BOOKE_DBCR0 308
328#define BOOKE_DBCR1 309
329#define BOOKE_DBCR2 310
330#define BOOKE_DAC1 316
331#define BOOKE_DAC2 317
332#define BOOKE_DVC1 318
333#define BOOKE_DVC2 319
334
335/* Freescale Book E Implementation Standards (EIS): Branch Operations */
336
337#define FSL_EIS_BUCSR 1013
338#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54))
339#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63))
340
341/* Freescale Book E Implementation Standards (EIS): Hardware Implementation-Dependent Registers */
342
343#define FSL_EIS_SVR 1023
344
345/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */
346
347#define FSL_EIS_MAS0 624
348#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35))
349#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47))
350#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf)
351#define FSL_EIS_MAS0_NV (1 << (63 - 63))
352
353#define FSL_EIS_MAS1 625
354#define FSL_EIS_MAS1_V (1 << (63 - 32))
355#define FSL_EIS_MAS1_IPROT (1 << (63 - 33))
356#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47))
357#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff)
358#define FSL_EIS_MAS1_TS (1 << (63 - 51))
359#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55))
360#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf)
361
362#define FSL_EIS_MAS2 626
363#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51))
364#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff)
365#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12)
366#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12)
367#define FSL_EIS_MAS2_X0 (1 << (63 - 57))
368#define FSL_EIS_MAS2_X1 (1 << (63 - 58))
369#define FSL_EIS_MAS2_W (1 << (63 - 59))
370#define FSL_EIS_MAS2_I (1 << (63 - 60))
371#define FSL_EIS_MAS2_M (1 << (63 - 61))
372#define FSL_EIS_MAS2_G (1 << (63 - 62))
373#define FSL_EIS_MAS2_E (1 << (63 - 63))
374#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f)
375#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f)
376
377#define FSL_EIS_MAS3 627
378#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51))
379#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff)
380#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12)
381#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12)
382#define FSL_EIS_MAS3_U0 (1 << (63 - 54))
383#define FSL_EIS_MAS3_U1 (1 << (63 - 55))
384#define FSL_EIS_MAS3_U2 (1 << (63 - 56))
385#define FSL_EIS_MAS3_U3 (1 << (63 - 57))
386#define FSL_EIS_MAS3_UX (1 << (63 - 58))
387#define FSL_EIS_MAS3_SX (1 << (63 - 59))
388#define FSL_EIS_MAS3_UW (1 << (63 - 60))
389#define FSL_EIS_MAS3_SW (1 << (63 - 61))
390#define FSL_EIS_MAS3_UR (1 << (63 - 62))
391#define FSL_EIS_MAS3_SR (1 << (63 - 63))
392#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff)
393#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff)
394
395#define FSL_EIS_MAS4 628
396#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35))
397#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47))
398#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55))
399#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0
400#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1
401#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W
402#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I
403#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M
404#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G
405#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E
406
407#define FSL_EIS_MAS5 629
408
409#define FSL_EIS_MAS6 630
410#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55))
411#define FSL_EIS_MAS6_SAS (1 << (63 - 63))
412
413#define FSL_EIS_MAS7 944
414
415#define FSL_EIS_MMUCFG 1015
416#define FSL_EIS_MMUCSR0 1012
417#define FSL_EIS_PID0 48
418#define FSL_EIS_PID1 633
419#define FSL_EIS_PID2 634
420#define FSL_EIS_TLB0CFG 688
421#define FSL_EIS_TLB1CFG 689
422
423/* Freescale Book E Implementation Standards (EIS): L1 Cache */
424
425#define FSL_EIS_L1CFG0 515
426#define FSL_EIS_L1CFG1 516
427#define FSL_EIS_L1CSR0 1010
428#define FSL_EIS_L1CSR1 1011
429
430/* Freescale Book E Implementation Standards (EIS): Timer */
431
432#define FSL_EIS_ATBL 526
433#define FSL_EIS_ATBU 527
434
435/* Freescale Book E Implementation Standards (EIS): Interrupt */
436
437#define FSL_EIS_MCAR 573
438#define FSL_EIS_DSRR0 574
439#define FSL_EIS_DSRR1 575
440
441/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */
442
443#define FSL_EIS_SPEFSCR 512
444
445/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */
446
447#define FSL_EIS_SPRG8 604
448#define FSL_EIS_SPRG9 605
449
450/* Freescale Book E Implementation Standards (EIS): Debug */
451
452#define FSL_EIS_DBCR3 561
453#define FSL_EIS_DBCR4 563
454#define FSL_EIS_DBCR5 564
455#define FSL_EIS_DBCR6 603
456#define FSL_EIS_DBCNT 562
457
458/**
459 * @brief Default value for the interrupt disable mask.
460 *
461 * The interrupt disable mask is stored in the SPRG0 (= special purpose
462 * register 272).
463 */
464#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
465
466#ifndef ASM
467
468#include <stdint.h>
469
470#ifdef __cplusplus
471extern "C" {
472#endif /* __cplusplus */
473
474#define _CPU_MSR_GET( _msr_value ) \
475  do { \
476    _msr_value = 0; \
477    __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
478  } while (0)
479
480#define _CPU_MSR_SET( _msr_value ) \
481{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
482
483static inline void ppc_interrupt_set_disable_mask( uint32_t mask )
484{
485  __asm__ volatile (
486    "mtspr 272, %0"
487    :
488    : "r" (mask)
489  );
490}
491
492static inline uint32_t ppc_interrupt_get_disable_mask( void )
493{
494  uint32_t mask;
495
496  __asm__ volatile (
497    "mfspr %0, 272"
498    : "=r" (mask)
499  );
500
501  return mask;
502}
503
504static inline uint32_t ppc_interrupt_disable( void )
505{
506  uint32_t level;
507  uint32_t mask;
508
509  __asm__ volatile (
510    "mfmsr %0;"
511    "mfspr %1, 272;"
512    "andc %1, %0, %1;"
513    "mtmsr %1"
514    : "=r" (level), "=r" (mask)
515  );
516
517  return level;
518}
519
520static inline void ppc_interrupt_enable( uint32_t level )
521{
522  __asm__ volatile (
523    "mtmsr %0"
524    :
525    : "r" (level)
526  );
527}
528
529static inline void ppc_interrupt_flash( uint32_t level )
530{
531  uint32_t current_level;
532
533  __asm__ volatile (
534    "mfmsr %0;"
535    "mtmsr %1;"
536    "mtmsr %0"
537    : "=&r" (current_level)
538    : "r" (level)
539  );
540}
541
542#define _CPU_ISR_Disable( _isr_cookie ) \
543  do { \
544    _isr_cookie = ppc_interrupt_disable(); \
545  } while (0)
546
547/*
548 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
549 *  This indicates the end of an RTEMS critical section.  The parameter
550 *  _isr_cookie is not modified.
551 */
552
553#define _CPU_ISR_Enable( _isr_cookie )  \
554  ppc_interrupt_enable(_isr_cookie)
555
556/*
557 *  This temporarily restores the interrupt to _isr_cookie before immediately
558 *  disabling them again.  This is used to divide long RTEMS critical
559 *  sections into two or more parts.  The parameter _isr_cookie is not
560 *  modified.
561 *
562 *  NOTE:  The version being used is not very optimized but it does
563 *         not trip a problem in gcc where the disable mask does not
564 *         get loaded.  Check this for future (post 10/97 gcc versions.
565 */
566
567#define _CPU_ISR_Flash( _isr_cookie ) \
568  ppc_interrupt_flash(_isr_cookie)
569
570/* end of ISR handler macros */
571
572#ifdef __cplusplus
573}
574#endif /* __cplusplus */
575
576#endif /* ASM */
577
578#endif /* _RTEMS_POWERPC_REGISTERS_H */
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