source: rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @ 2628ebb

4.104.114.84.95
Last change on this file since 2628ebb was 2628ebb, checked in by Till Straumann <strauman@…>, on 11/02/05 at 23:25:39

2005-11-02 straumanatslacdotstanford.edu

  • rtems/powerpc/registers.h: recognize mpc7457 CPU; added definitions for high bats (#4..7) on 7450 CPUs
  • Property mode set to 100644
File size: 12.4 KB
Line 
1/*
2 * This file contains some powerpc MSR and registers access definitions.
3 *
4 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
5 *                     Canon Centre Recherche France.
6 *
7 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited
9 *
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef _RTEMS_POWERPC_REGISTERS_H
19#define _RTEMS_POWERPC_REGISTERS_H
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/* Bit encodings for Machine State Register (MSR) */
26#define MSR_VE          (1<<25)         /* Alti-Vec enable (7400+) */
27#define MSR_POW         (1<<18)         /* Enable Power Management */
28#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
29#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
30#define MSR_EE          (1<<15)         /* External Interrupt enable */
31#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
32#define MSR_FP          (1<<13)         /* Floating Point enable */
33#define MSR_ME          (1<<12)         /* Machine Check enable */
34#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
35#define MSR_SE          (1<<10)         /* Single Step */
36#define MSR_BE          (1<<9)          /* Branch Trace */
37#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
38#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
39#define MSR_IR          (1<<5)          /* Instruction MMU enable */
40#define MSR_DR          (1<<4)          /* Data MMU enable */
41#define MSR_RI          (1<<1)          /* Recoverable Exception */
42#define MSR_LE          (1<<0)          /* Little-Endian enable */
43
44#define MSR_            MSR_ME|MSR_RI
45#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
46#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
47
48/* Bit encodings for Hardware Implementation Register (HID0)
49   on PowerPC 603, 604, etc. processors (not 601). */
50
51/* WARNING: HID0/HID1 are *truely* implementation dependent!
52 *          you *cannot* rely on the same bits to be present,
53 *          at the same place or even in the same register
54 *          on different CPU familys.
55 *          E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
56 *          on the 7450s. IFFT is XBSEN on 7450 and so on...
57 */
58#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
59#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
60#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
61#define HID0_SBCLK      (1<<27)
62#define HID0_TBEN       (1<<26)         /* 7455:this bit must be set
63                                         * and TBEN signal must be asserted
64                                         * to enable the time base and
65                                         * decrementer.
66                                         */
67#define HID0_EICE       (1<<26)
68#define HID0_ECLK       (1<<25)
69#define HID0_PAR        (1<<24)
70#define HID0_DOZE       (1<<23)
71/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !!          */
72#define HID0_7455_HIGH_BAT_EN (1<<23)
73
74#define HID0_NAP        (1<<22)
75#define HID0_SLEEP      (1<<21)
76#define HID0_DPM        (1<<20)
77#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
78#define HID0_DCE        (1<<14)         /* Data Cache Enable */
79#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
80#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
81#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
82#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
83/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
84#define HID0_7455_XBSEN       (1<<8)
85#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
86#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
87/* S.K. Feng 10/03, added for MPC7455 */
88#define HID0_LRSTK      (1<<4)          /* Link register stack enable (7455) */
89#define HID0_FOLD       (1<<3)          /* Branch folding enable (7455) */
90
91#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
92#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
93
94/* fpscr settings */
95#define FPSCR_FX        (1<<31)
96#define FPSCR_FEX       (1<<30)
97
98#define _MACH_prep     1
99#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
100#define _MACH_chrp     4 /* chrp machine */
101#define _MACH_mbx      8 /* Motorola MBX board */
102#define _MACH_apus    16 /* amiga with phase5 powerup */
103#define _MACH_fads    32 /* Motorola FADS board */
104
105/* see residual.h for these */
106#define _PREP_Motorola 0x01  /* motorola prep */
107#define _PREP_Firm     0x02  /* firmworks prep */
108#define _PREP_IBM      0x00  /* ibm prep */
109#define _PREP_Bull     0x03  /* bull prep */
110
111/* these are arbitrary */
112#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
113#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
114
115#define _GLOBAL(n)\
116        .globl n;\
117n:
118
119#define TBRU    269     /* Time base Upper/Lower (Reading) */
120#define TBRL    268
121#define TBWU    284     /* Time base Upper/Lower (Writing) */
122#define TBWL    285
123#define XER     1
124#define LR      8
125#define CTR     9
126#define HID0    1008    /* Hardware Implementation */
127#define HID1    1009    /* Hardware Implementation */
128#define DABR    1013    /* Data Access Breakpoint  */
129#define PVR     287     /* Processor Version */
130#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
131#define IBAT0L  529
132#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
133#define IBAT1L  531
134#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
135#define IBAT2L  533
136#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
137#define IBAT3L  535
138
139/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
140#define IBAT4U  560     /* Instruction BAT #0 Upper/Lower */
141#define IBAT4L  561
142#define IBAT5U  562     /* Instruction BAT #1 Upper/Lower */
143#define IBAT5L  563
144#define IBAT6U  564     /* Instruction BAT #2 Upper/Lower */
145#define IBAT6L  565
146#define IBAT7U  566     /* Instruction BAT #3 Upper/Lower */
147#define IBAT7L  567
148
149#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
150#define DBAT0L  537
151#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
152#define DBAT1L  539
153#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
154#define DBAT2L  541
155#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
156#define DBAT3L  543
157
158/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
159#define DBAT4U  568     /* Instruction BAT #0 Upper/Lower */
160#define DBAT4L  569
161#define DBAT5U  570     /* Instruction BAT #1 Upper/Lower */
162#define DBAT5L  571
163#define DBAT6U  572     /* Instruction BAT #2 Upper/Lower */
164#define DBAT6L  573
165#define DBAT7U  574     /* Instruction BAT #3 Upper/Lower */
166#define DBAT7L  575
167
168#define DMISS   976     /* TLB Lookup/Refresh registers */
169#define DCMP    977
170#define HASH1   978
171#define HASH2   979
172#define IMISS   980
173#define ICMP    981
174#define RPA     982
175#define SDR1    25      /* MMU hash base register */
176#define DAR     19      /* Data Address Register */
177#define SPR0    272     /* Supervisor Private Registers */
178#define SPRG0   272
179#define SPR1    273
180#define SPRG1   273
181#define SPR2    274
182#define SPRG2   274
183#define SPR3    275
184#define SPRG3   275
185#define DSISR   18
186#define SRR0    26      /* Saved Registers (exception) */
187#define SRR1    27
188#define IABR    1010    /* Instruction Address Breakpoint */
189#define DEC     22      /* Decrementer */
190#define EAR     282     /* External Address Register */
191
192#define MSSCR0   1014   /* Memory Subsystem Control Register */
193
194#define L2CR    1017    /* PPC 750 and 74xx L2 control register */
195
196#define L2CR_L2E   (1<<31)      /* enable */
197#define L2CR_L2I   (1<<21)      /* global invalidate */
198
199/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
200/* Oddly, the following L2CR bit defintions in 745x
201 * is different from that of 7400 and 7410.
202 * Though not used in 7400 and 7410, it is appeded with _745x just
203 * to be clarified.
204 */     
205#define L2CR_L2IO_745x  0x100000  /* (1<<20) L2 Instruction-Only  */
206#define L2CR_L2DO_745x  0x10000   /* (1<<16) L2 Data-Only */
207#define L2CR_LOCK_745x  (L2CR_L2IO_745x|L2CR_L2DO_745x)
208#define L2CR_L3OH0      0x00080000 /* 12:L3 output hold 0 */
209       
210#define L3CR    1018    /* PPC 7450/7455 L3 control register */
211#define L3CR_L3IO_745x  0x400000  /* (1<<22) L3 Instruction-Only */
212#define L3CR_L3DO_745x  0x40      /* (1<<6) L3 Data-Only */
213
214#define L3CR_LOCK_745x  (L3CR_L3IO_745x|L3CR_L3DO_745x)
215
216#define   L3CR_RESERVED           0x0438003a /* Reserved bits in L3CR */
217#define   L3CR_L3E                0x80000000 /* 0: L3 enable */
218#define   L3CR_L3PE               0x40000000 /* 1: L3 data parity checking enable */
219#define   L3CR_L3APE              0x20000000 /* 2: L3 address parity checking enable */
220#define   L3CR_L3SIZ              0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
221#define    L3SIZ_1M               0x00000000
222#define    L3SIZ_2M               0x10000000
223#define   L3CR_L3CLKEN            0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
224#define   L3CR_L3CLK              0x03800000 /* 6-8: L3 clock ratio */
225#define    L3CLK_60               0x00000000 /* core clock / 6   */
226#define    L3CLK_20               0x01000000 /*            / 2   */
227#define    L3CLK_25               0x01800000 /*            / 2.5 */
228#define    L3CLK_30               0x02000000 /*            / 3   */
229#define    L3CLK_35               0x02800000 /*            / 3.5 */
230#define    L3CLK_40               0x03000000 /*            / 4   */
231#define    L3CLK_50               0x03800000 /*            / 5   */
232#define   L3CR_L3IO               0x00400000 /* 9: L3 instruction-only mode */
233#define   L3CR_L3SPO              0x00040000 /* 13: L3 sample point override */
234#define   L3CR_L3CKSP             0x00030000 /* 14-15: L3 clock sample point */
235#define    L3CKSP_2               0x00000000 /* 2 clocks */
236#define    L3CKSP_3               0x00010000 /* 3 clocks */
237#define    L3CKSP_4               0x00020000 /* 4 clocks */
238#define    L3CKSP_5               0x00030000 /* 5 clocks */
239#define   L3CR_L3PSP              0x0000e000 /* 16-18: L3 P-clock sample point */
240#define    L3PSP_0                0x00000000 /* 0 clocks */
241#define    L3PSP_1                0x00002000 /* 1 clocks */
242#define    L3PSP_2                0x00004000 /* 2 clocks */
243#define    L3PSP_3                0x00006000 /* 3 clocks */
244#define    L3PSP_4                0x00008000 /* 4 clocks */
245#define    L3PSP_5                0x0000a000 /* 5 clocks */
246#define   L3CR_L3REP              0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
247#define   L3CR_L3HWF              0x00000800 /* 20: L3 hardware flush */
248#define   L3CR_L3I                0x00000400 /* 21: L3 global invaregisters.h.orig
249lidate */
250#define   L3CR_L3RT               0x00000300 /* 22-23: L3 SRAM type */
251#define    L3RT_MSUG2_DDR         0x00000000 /* MSUG2 DDR SRAM */
252#define    L3RT_PIPELINE_LATE     0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
253#define    L3RT_PB2_SRAM          0x00000300 /* PB2 SRAM */
254#define   L3CR_L3NIRCA            0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
255#define   L3CR_L3DO               0x00000040 /* 25: L3 data-only mode */
256#define   L3CR_PMEN               0x00000004 /* 29: Private memory enable */
257#define   L3CR_PMSIZ              0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
258
259#define THRM1   1020
260#define THRM2   1021
261#define THRM3   1022
262#define THRM1_TIN (1<<(31-0))
263#define THRM1_TIV (1<<(31-1))
264#define THRM1_THRES (0x7f<<(31-8))
265#define THRM1_TID (1<<(31-29))
266#define THRM1_TIE (1<<(31-30))
267#define THRM1_V   (1<<(31-31))
268#define THRM3_SITV (0x1fff << (31-30))
269#define THRM3_E   (1<<(31-31))
270
271/* Segment Registers */
272#define SR0     0
273#define SR1     1
274#define SR2     2
275#define SR3     3
276#define SR4     4
277#define SR5     5
278#define SR6     6
279#define SR7     7
280#define SR8     8
281#define SR9     9
282#define SR10    10
283#define SR11    11
284#define SR12    12
285#define SR13    13
286#define SR14    14
287#define SR15    15
288
289#define _CPU_MSR_GET( _msr_value ) \
290  do { \
291    _msr_value = 0; \
292    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
293  } while (0)
294
295#define _CPU_MSR_SET( _msr_value ) \
296{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
297
298#define _CPU_ISR_Disable( _isr_cookie ) \
299  { register unsigned int _disable_mask = MSR_EE; \
300    _isr_cookie = 0; \
301    asm volatile ( \
302        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
303        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
304        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
305        ); \
306  }
307
308
309/*
310 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
311 *  This indicates the end of an RTEMS critical section.  The parameter
312 *  _isr_cookie is not modified.
313 */
314
315#define _CPU_ISR_Enable( _isr_cookie )  \
316  { \
317     asm volatile ( "mtmsr %0" : \
318                   "=r" ((_isr_cookie)) : \
319                   "0" ((_isr_cookie))); \
320  }
321
322/*
323 *  This temporarily restores the interrupt to _isr_cookie before immediately
324 *  disabling them again.  This is used to divide long RTEMS critical
325 *  sections into two or more parts.  The parameter _isr_cookie is not
326 *  modified.
327 *
328 *  NOTE:  The version being used is not very optimized but it does
329 *         not trip a problem in gcc where the disable mask does not
330 *         get loaded.  Check this for future (post 10/97 gcc versions.
331 */
332
333#define _CPU_ISR_Flash( _isr_cookie ) \
334  { register unsigned int _disable_mask = MSR_EE; \
335    asm volatile ( \
336      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
337      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
338      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
339    ); \
340  }
341
342
343/* end of ISR handler macros */
344
345#ifdef __cplusplus
346}
347#endif
348
349#endif /* _RTEMS_POWERPC_REGISTERS_H */
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