[4a0d87e] | 1 | /* |
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| 2 | * This file contains some powerpc MSR and registers access definitions. |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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| 5 | * Canon Centre Recherche France. |
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| 6 | * |
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| 7 | * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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| 8 | * Surrey Satellite Technology Limited |
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| 9 | * |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in found in the file LICENSE in this distribution or at |
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| 13 | * http://www.OARcorp.com/rtems/license.html. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef __rtems_powerpc_registers_h |
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| 19 | #define __rtems_powerpc_registers_h |
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| 20 | |
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| 21 | #ifdef __cplusplus |
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| 22 | extern "C" { |
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| 23 | #endif |
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| 24 | |
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| 25 | /* Bit encodings for Machine State Register (MSR) */ |
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| 26 | #define MSR_POW (1<<18) /* Enable Power Management */ |
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| 27 | #define MSR_TGPR (1<<17) /* TLB Update registers in use */ |
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| 28 | #define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ |
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| 29 | #define MSR_EE (1<<15) /* External Interrupt enable */ |
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| 30 | #define MSR_PR (1<<14) /* Supervisor/User privilege */ |
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| 31 | #define MSR_FP (1<<13) /* Floating Point enable */ |
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| 32 | #define MSR_ME (1<<12) /* Machine Check enable */ |
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| 33 | #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ |
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| 34 | #define MSR_SE (1<<10) /* Single Step */ |
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| 35 | #define MSR_BE (1<<9) /* Branch Trace */ |
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| 36 | #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ |
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| 37 | #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ |
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| 38 | #define MSR_IR (1<<5) /* Instruction MMU enable */ |
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| 39 | #define MSR_DR (1<<4) /* Data MMU enable */ |
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| 40 | #define MSR_RI (1<<1) /* Recoverable Exception */ |
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| 41 | #define MSR_LE (1<<0) /* Little-Endian enable */ |
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| 42 | |
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| 43 | #define MSR_ MSR_ME|MSR_RI |
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| 44 | #define MSR_KERNEL MSR_|MSR_IR|MSR_DR |
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| 45 | #define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE |
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| 46 | |
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| 47 | /* Bit encodings for Hardware Implementation Register (HID0) |
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| 48 | on PowerPC 603, 604, etc. processors (not 601). */ |
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| 49 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ |
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| 50 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ |
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| 51 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ |
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| 52 | #define HID0_SBCLK (1<<27) |
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| 53 | #define HID0_EICE (1<<26) |
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| 54 | #define HID0_ECLK (1<<25) |
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| 55 | #define HID0_PAR (1<<24) |
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| 56 | #define HID0_DOZE (1<<23) |
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| 57 | #define HID0_NAP (1<<22) |
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| 58 | #define HID0_SLEEP (1<<21) |
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| 59 | #define HID0_DPM (1<<20) |
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| 60 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ |
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| 61 | #define HID0_DCE (1<<14) /* Data Cache Enable */ |
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| 62 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ |
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| 63 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ |
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| 64 | #define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ |
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| 65 | #define HID0_DCI (1<<10) /* Data Cache Invalidate */ |
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| 66 | #define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ |
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[78f8c91] | 67 | #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ |
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[4a0d87e] | 68 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ |
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| 69 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ |
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| 70 | |
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| 71 | /* fpscr settings */ |
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| 72 | #define FPSCR_FX (1<<31) |
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| 73 | #define FPSCR_FEX (1<<30) |
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| 74 | |
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| 75 | #define _MACH_prep 1 |
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| 76 | #define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ |
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| 77 | #define _MACH_chrp 4 /* chrp machine */ |
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| 78 | #define _MACH_mbx 8 /* Motorola MBX board */ |
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| 79 | #define _MACH_apus 16 /* amiga with phase5 powerup */ |
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| 80 | #define _MACH_fads 32 /* Motorola FADS board */ |
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| 81 | |
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| 82 | /* see residual.h for these */ |
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| 83 | #define _PREP_Motorola 0x01 /* motorola prep */ |
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| 84 | #define _PREP_Firm 0x02 /* firmworks prep */ |
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| 85 | #define _PREP_IBM 0x00 /* ibm prep */ |
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| 86 | #define _PREP_Bull 0x03 /* bull prep */ |
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| 87 | |
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| 88 | /* these are arbitrary */ |
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| 89 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ |
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| 90 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ |
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| 91 | |
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| 92 | #define _GLOBAL(n)\ |
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| 93 | .globl n;\ |
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| 94 | n: |
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| 95 | |
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| 96 | #define TBRU 269 /* Time base Upper/Lower (Reading) */ |
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| 97 | #define TBRL 268 |
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| 98 | #define TBWU 284 /* Time base Upper/Lower (Writing) */ |
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| 99 | #define TBWL 285 |
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| 100 | #define XER 1 |
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| 101 | #define LR 8 |
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| 102 | #define CTR 9 |
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| 103 | #define HID0 1008 /* Hardware Implementation */ |
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| 104 | #define PVR 287 /* Processor Version */ |
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| 105 | #define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ |
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| 106 | #define IBAT0L 529 |
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| 107 | #define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ |
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| 108 | #define IBAT1L 531 |
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| 109 | #define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ |
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| 110 | #define IBAT2L 533 |
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| 111 | #define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ |
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| 112 | #define IBAT3L 535 |
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| 113 | #define DBAT0U 536 /* Data BAT #0 Upper/Lower */ |
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| 114 | #define DBAT0L 537 |
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| 115 | #define DBAT1U 538 /* Data BAT #1 Upper/Lower */ |
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| 116 | #define DBAT1L 539 |
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| 117 | #define DBAT2U 540 /* Data BAT #2 Upper/Lower */ |
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| 118 | #define DBAT2L 541 |
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| 119 | #define DBAT3U 542 /* Data BAT #3 Upper/Lower */ |
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| 120 | #define DBAT3L 543 |
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| 121 | #define DMISS 976 /* TLB Lookup/Refresh registers */ |
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| 122 | #define DCMP 977 |
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| 123 | #define HASH1 978 |
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| 124 | #define HASH2 979 |
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| 125 | #define IMISS 980 |
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| 126 | #define ICMP 981 |
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| 127 | #define RPA 982 |
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| 128 | #define SDR1 25 /* MMU hash base register */ |
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| 129 | #define DAR 19 /* Data Address Register */ |
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| 130 | #define SPR0 272 /* Supervisor Private Registers */ |
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| 131 | #define SPRG0 272 |
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| 132 | #define SPR1 273 |
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| 133 | #define SPRG1 273 |
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| 134 | #define SPR2 274 |
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| 135 | #define SPRG2 274 |
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| 136 | #define SPR3 275 |
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| 137 | #define SPRG3 275 |
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| 138 | #define DSISR 18 |
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| 139 | #define SRR0 26 /* Saved Registers (exception) */ |
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| 140 | #define SRR1 27 |
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| 141 | #define IABR 1010 /* Instruction Address Breakpoint */ |
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| 142 | #define DEC 22 /* Decrementer */ |
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| 143 | #define EAR 282 /* External Address Register */ |
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| 144 | #define L2CR 1017 /* PPC 750 L2 control register */ |
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| 145 | |
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| 146 | #define THRM1 1020 |
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| 147 | #define THRM2 1021 |
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| 148 | #define THRM3 1022 |
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| 149 | #define THRM1_TIN 0x1 |
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| 150 | #define THRM1_TIV 0x2 |
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| 151 | #define THRM1_THRES (0x7f<<2) |
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| 152 | #define THRM1_TID (1<<29) |
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| 153 | #define THRM1_TIE (1<<30) |
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| 154 | #define THRM1_V (1<<31) |
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| 155 | #define THRM3_E (1<<31) |
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| 156 | |
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| 157 | /* Segment Registers */ |
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| 158 | #define SR0 0 |
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| 159 | #define SR1 1 |
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| 160 | #define SR2 2 |
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| 161 | #define SR3 3 |
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| 162 | #define SR4 4 |
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| 163 | #define SR5 5 |
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| 164 | #define SR6 6 |
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| 165 | #define SR7 7 |
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| 166 | #define SR8 8 |
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| 167 | #define SR9 9 |
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| 168 | #define SR10 10 |
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| 169 | #define SR11 11 |
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| 170 | #define SR12 12 |
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| 171 | #define SR13 13 |
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| 172 | #define SR14 14 |
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| 173 | #define SR15 15 |
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| 174 | |
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| 175 | #ifndef ASM |
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| 176 | /* |
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| 177 | * Routines to access the time base register |
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| 178 | */ |
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| 179 | |
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| 180 | static inline unsigned long long PPC_Get_timebase_register( void ) |
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| 181 | { |
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| 182 | unsigned long tbr_low; |
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| 183 | unsigned long tbr_high; |
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| 184 | unsigned long tbr_high_old; |
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| 185 | unsigned long long tbr; |
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| 186 | |
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| 187 | do { |
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| 188 | asm volatile( "mftbu %0" : "=r" (tbr_high_old)); |
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| 189 | asm volatile( "mftb %0" : "=r" (tbr_low)); |
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| 190 | asm volatile( "mftbu %0" : "=r" (tbr_high)); |
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| 191 | } while ( tbr_high_old != tbr_high ); |
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| 192 | |
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| 193 | tbr = tbr_high; |
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| 194 | tbr <<= 32; |
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| 195 | tbr |= tbr_low; |
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| 196 | return tbr; |
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| 197 | } |
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| 198 | |
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| 199 | static inline void PPC_Set_timebase_register (unsigned long long tbr) |
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| 200 | { |
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| 201 | unsigned long tbr_low; |
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| 202 | unsigned long tbr_high; |
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| 203 | |
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| 204 | tbr_low = (tbr & 0xffffffff) ; |
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| 205 | tbr_high = (tbr >> 32) & 0xffffffff; |
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| 206 | asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); |
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| 207 | asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); |
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| 208 | |
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| 209 | } |
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| 210 | #endif |
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| 211 | |
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| 212 | #define _CPU_MSR_GET( _msr_value ) \ |
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| 213 | do { \ |
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| 214 | _msr_value = 0; \ |
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| 215 | asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ |
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| 216 | } while (0) |
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| 217 | |
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| 218 | #define _CPU_MSR_SET( _msr_value ) \ |
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| 219 | { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } |
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| 220 | |
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| 221 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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| 222 | { register unsigned int _disable_mask = MSR_EE; \ |
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| 223 | _isr_cookie = 0; \ |
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| 224 | asm volatile ( \ |
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| 225 | "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
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| 226 | "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ |
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| 227 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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| 228 | ); \ |
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| 229 | } |
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| 230 | |
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| 231 | |
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| 232 | /* |
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| 233 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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| 234 | * This indicates the end of an RTEMS critical section. The parameter |
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| 235 | * _isr_cookie is not modified. |
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| 236 | */ |
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| 237 | |
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| 238 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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| 239 | { \ |
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| 240 | asm volatile ( "mtmsr %0" : \ |
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| 241 | "=r" ((_isr_cookie)) : \ |
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| 242 | "0" ((_isr_cookie))); \ |
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| 243 | } |
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| 244 | |
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| 245 | /* |
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| 246 | * This temporarily restores the interrupt to _isr_cookie before immediately |
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| 247 | * disabling them again. This is used to divide long RTEMS critical |
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| 248 | * sections into two or more parts. The parameter _isr_cookie is not |
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| 249 | * modified. |
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| 250 | * |
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| 251 | * NOTE: The version being used is not very optimized but it does |
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| 252 | * not trip a problem in gcc where the disable mask does not |
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| 253 | * get loaded. Check this for future (post 10/97 gcc versions. |
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| 254 | */ |
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| 255 | |
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| 256 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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| 257 | { register unsigned int _disable_mask = MSR_EE; \ |
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| 258 | asm volatile ( \ |
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| 259 | "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
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| 260 | "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ |
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| 261 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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| 262 | ); \ |
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| 263 | } |
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| 264 | |
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| 265 | |
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| 266 | /* end of ISR handler macros */ |
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| 267 | |
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| 268 | /* |
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| 269 | * Simple spin delay in microsecond units for device drivers. |
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| 270 | * This is very dependent on the clock speed of the target. |
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| 271 | */ |
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| 272 | |
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| 273 | #define CPU_Get_timebase_low( _value ) \ |
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| 274 | asm volatile( "mftb %0" : "=r" (_value) ) |
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| 275 | |
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| 276 | #define rtems_bsp_delay( _microseconds ) \ |
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| 277 | do { \ |
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| 278 | unsigned32 start, ticks, now; \ |
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| 279 | CPU_Get_timebase_low( start ) ; \ |
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| 280 | ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \ |
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| 281 | do \ |
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| 282 | CPU_Get_timebase_low( now ) ; \ |
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| 283 | while (now - start < ticks); \ |
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| 284 | } while (0) |
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| 285 | |
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| 286 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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| 287 | do { \ |
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| 288 | unsigned32 start, now; \ |
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| 289 | CPU_Get_timebase_low( start ); \ |
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| 290 | do \ |
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| 291 | CPU_Get_timebase_low( now ); \ |
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| 292 | while (now - start < (_cycles)); \ |
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| 293 | } while (0) |
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| 294 | |
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| 295 | #define PPC_Set_decrementer( _clicks ) \ |
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| 296 | do { \ |
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[b07906fd] | 297 | asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ |
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[4a0d87e] | 298 | } while (0) |
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| 299 | |
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| 300 | #define PPC_Get_decrementer( _clicks ) \ |
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| 301 | asm volatile( "mfdec %0" : "=r" (_clicks) ) |
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| 302 | |
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| 303 | #ifdef __cplusplus |
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| 304 | } |
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| 305 | #endif |
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| 306 | |
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| 307 | #endif /* __rtems_powerpc_registers_h */ |
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