source: rtems/cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h @ b2a41060

4.104.114.84.95
Last change on this file since b2a41060 was b2a41060, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 9, 2005 at 3:50:38 PM

2005-02-09 Ralf Corsepius <ralf.corsepius@…>

  • rtems/old-exceptions/cpu.h, rtems/score/powerpc.h: Remove PPC_ABI_GCC27.
  • Property mode set to 100644
File size: 36.4 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may in
27 *  the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#ifndef _RTEMS_OLD_EXCEPTIONS_CPU_H
34#define _RTEMS_OLD_EXCEPTIONS_CPU_H
35
36#ifndef _RTEMS_SCORE_CPU_H
37#error "You should include <rtems/score/cpu.h>"
38#endif
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44#ifndef ASM
45struct CPU_Interrupt_frame;
46typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
47#endif
48
49/* conditional compilation parameters */
50
51/*
52 *  Does RTEMS manage a dedicated interrupt stack in software?
53 *
54 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
55 *  If FALSE, nothing is done.
56 *
57 *  If the CPU supports a dedicated interrupt stack in hardware,
58 *  then it is generally the responsibility of the BSP to allocate it
59 *  and set it up.
60 *
61 *  If the CPU does not support a dedicated interrupt stack, then
62 *  the porter has two options: (1) execute interrupts on the
63 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
64 *  interrupt stack.
65 *
66 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
67 *
68 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
69 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
70 *  possible that both are FALSE for a particular CPU.  Although it
71 *  is unclear what that would imply about the interrupt processing
72 *  procedure on that CPU.
73 */
74
75#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
76
77/*
78 *  Does this CPU have hardware support for a dedicated interrupt stack?
79 *
80 *  If TRUE, then it must be installed during initialization.
81 *  If FALSE, then no installation is performed.
82 *
83 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
84 *
85 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
86 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
87 *  possible that both are FALSE for a particular CPU.  Although it
88 *  is unclear what that would imply about the interrupt processing
89 *  procedure on that CPU.
90 */
91
92/*
93 *  ACB: This is a lie, but it gets us a handle on a call to set up
94 *  a variable derived from the top of the interrupt stack.
95 */
96
97#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
98
99/*
100 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
101 *
102 *  If TRUE, then the memory is allocated during initialization.
103 *  If FALSE, then the memory is allocated during initialization.
104 *
105 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
106 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
107 */
108
109#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
110
111/*
112 *  Does the RTEMS invoke the user's ISR with the vector number and
113 *  a pointer to the saved interrupt frame (1) or just the vector
114 *  number (0)?
115 */
116
117#define CPU_ISR_PASSES_FRAME_POINTER 1
118
119/*
120 *  Does the CPU have hardware floating point?
121 *
122 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
123 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
124 *
125 *  If there is a FP coprocessor such as the i387 or mc68881, then
126 *  the answer is TRUE.
127 *
128 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
129 *  It indicates whether or not this CPU model has FP support.  For
130 *  example, it would be possible to have an i386_nofp CPU model
131 *  which set this to false to indicate that you have an i386 without
132 *  an i387 and wish to leave floating point support out of RTEMS.
133 */
134
135#if ( PPC_HAS_FPU == 1 )
136#define CPU_HARDWARE_FP     TRUE
137#else
138#define CPU_HARDWARE_FP     FALSE
139#endif
140
141/*
142 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
143 *
144 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
145 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
146 *
147 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
148 */
149
150#define CPU_ALL_TASKS_ARE_FP     FALSE
151
152/*
153 *  Should the IDLE task have a floating point context?
154 *
155 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
156 *  and it has a floating point context which is switched in and out.
157 *  If FALSE, then the IDLE task does not have a floating point context.
158 *
159 *  Setting this to TRUE negatively impacts the time required to preempt
160 *  the IDLE task from an interrupt because the floating point context
161 *  must be saved as part of the preemption.
162 */
163
164#define CPU_IDLE_TASK_IS_FP      FALSE
165
166/*
167 *  Should the saving of the floating point registers be deferred
168 *  until a context switch is made to another different floating point
169 *  task?
170 *
171 *  If TRUE, then the floating point context will not be stored until
172 *  necessary.  It will remain in the floating point registers and not
173 *  disturned until another floating point task is switched to.
174 *
175 *  If FALSE, then the floating point context is saved when a floating
176 *  point task is switched out and restored when the next floating point
177 *  task is restored.  The state of the floating point registers between
178 *  those two operations is not specified.
179 *
180 *  If the floating point context does NOT have to be saved as part of
181 *  interrupt dispatching, then it should be safe to set this to TRUE.
182 *
183 *  Setting this flag to TRUE results in using a different algorithm
184 *  for deciding when to save and restore the floating point context.
185 *  The deferred FP switch algorithm minimizes the number of times
186 *  the FP context is saved and restored.  The FP context is not saved
187 *  until a context switch is made to another, different FP task.
188 *  Thus in a system with only one FP task, the FP context will never
189 *  be saved or restored.
190 */
191/*
192 *  ACB Note:  This could make debugging tricky..
193 */
194
195#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
196
197/*
198 *  Does this port provide a CPU dependent IDLE task implementation?
199 *
200 *  If TRUE, then the routine _CPU_Thread_Idle_body
201 *  must be provided and is the default IDLE thread body instead of
202 *  _CPU_Thread_Idle_body.
203 *
204 *  If FALSE, then use the generic IDLE thread body if the BSP does
205 *  not provide one.
206 *
207 *  This is intended to allow for supporting processors which have
208 *  a low power or idle mode.  When the IDLE thread is executed, then
209 *  the CPU can be powered down.
210 *
211 *  The order of precedence for selecting the IDLE thread body is:
212 *
213 *    1.  BSP provided
214 *    2.  CPU dependent (if provided)
215 *    3.  generic (if no BSP and no CPU dependent)
216 */
217
218#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
219
220/*
221 *  Does the stack grow up (toward higher addresses) or down
222 *  (toward lower addresses)?
223 *
224 *  If TRUE, then the grows upward.
225 *  If FALSE, then the grows toward smaller addresses.
226 */
227
228#define CPU_STACK_GROWS_UP               FALSE
229
230/*
231 *  The following is the variable attribute used to force alignment
232 *  of critical RTEMS structures.  On some processors it may make
233 *  sense to have these aligned on tighter boundaries than
234 *  the minimum requirements of the compiler in order to have as
235 *  much of the critical data area as possible in a cache line.
236 *
237 *  The placement of this macro in the declaration of the variables
238 *  is based on the syntactically requirements of the GNU C
239 *  "__attribute__" extension.  For example with GNU C, use
240 *  the following to force a structures to a 32 byte boundary.
241 *
242 *      __attribute__ ((aligned (32)))
243 *
244 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
245 *         To benefit from using this, the data must be heavily
246 *         used so it will stay in the cache and used frequently enough
247 *         in the executive to justify turning this on.
248 */
249
250#define CPU_STRUCTURE_ALIGNMENT \
251  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
252
253/*
254 *  Define what is required to specify how the network to host conversion
255 *  routines are handled.
256 */
257
258#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
259#define CPU_BIG_ENDIAN                           TRUE
260#define CPU_LITTLE_ENDIAN                        FALSE
261
262/*
263 *  The following defines the number of bits actually used in the
264 *  interrupt field of the task mode.  How those bits map to the
265 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
266 *
267 *  The interrupt level is bit mapped for the PowerPC family. The
268 *  bits are set to 0 to indicate that a particular exception source
269 *  enabled and 1 if it is disabled.  This keeps with RTEMS convention
270 *  that interrupt level 0 means all sources are enabled.
271 *
272 *  The bits are assigned to correspond to enable bits in the MSR.
273 */
274
275#define PPC_INTERRUPT_LEVEL_ME   0x01
276#define PPC_INTERRUPT_LEVEL_EE   0x02
277#define PPC_INTERRUPT_LEVEL_CE   0x04
278
279/* XXX should these be maskable? */
280#if 0
281#define PPC_INTERRUPT_LEVEL_DE   0x08
282#define PPC_INTERRUPT_LEVEL_BE   0x10
283#define PPC_INTERRUPT_LEVEL_SE   0x20
284#endif
285
286#define CPU_MODES_INTERRUPT_MASK   0x00000007
287
288/*
289 *  Processor defined structures required for cpukit/score.
290 */
291
292/* may need to put some structures here.  */
293
294/*
295 * Contexts
296 *
297 *  Generally there are 2 types of context to save.
298 *     1. Interrupt registers to save
299 *     2. Task level registers to save
300 *
301 *  This means we have the following 3 context items:
302 *     1. task level context stuff::  Context_Control
303 *     2. floating point task stuff:: Context_Control_fp
304 *     3. special interrupt level context :: Context_Control_interrupt
305 *
306 *  On some processors, it is cost-effective to save only the callee
307 *  preserved registers during a task context switch.  This means
308 *  that the ISR code needs to save those registers which do not
309 *  persist across function calls.  It is not mandatory to make this
310 *  distinctions between the caller/callee saves registers for the
311 *  purpose of minimizing context saved during task switch and on interrupts.
312 *  If the cost of saving extra registers is minimal, simplicity is the
313 *  choice.  Save the same context on interrupt entry as for tasks in
314 *  this case.
315 *
316 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
317 *  care should be used in designing the context area.
318 *
319 *  On some CPUs with hardware floating point support, the Context_Control_fp
320 *  structure will not be used or it simply consist of an array of a
321 *  fixed number of bytes.   This is done when the floating point context
322 *  is dumped by a "FP save context" type instruction and the format
323 *  is not really defined by the CPU.  In this case, there is no need
324 *  to figure out the exact format -- only the size.  Of course, although
325 *  this is enough information for RTEMS, it is probably not enough for
326 *  a debugger such as gdb.  But that is another problem.
327 */
328
329#ifndef ASM
330typedef struct {
331    uint32_t   gpr1;    /* Stack pointer for all */
332    uint32_t   gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
333    uint32_t   gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
334    uint32_t   gpr14;   /* Non volatile for all */
335    uint32_t   gpr15;   /* Non volatile for all */
336    uint32_t   gpr16;   /* Non volatile for all */
337    uint32_t   gpr17;   /* Non volatile for all */
338    uint32_t   gpr18;   /* Non volatile for all */
339    uint32_t   gpr19;   /* Non volatile for all */
340    uint32_t   gpr20;   /* Non volatile for all */
341    uint32_t   gpr21;   /* Non volatile for all */
342    uint32_t   gpr22;   /* Non volatile for all */
343    uint32_t   gpr23;   /* Non volatile for all */
344    uint32_t   gpr24;   /* Non volatile for all */
345    uint32_t   gpr25;   /* Non volatile for all */
346    uint32_t   gpr26;   /* Non volatile for all */
347    uint32_t   gpr27;   /* Non volatile for all */
348    uint32_t   gpr28;   /* Non volatile for all */
349    uint32_t   gpr29;   /* Non volatile for all */
350    uint32_t   gpr30;   /* Non volatile for all */
351    uint32_t   gpr31;   /* Non volatile for all */
352    uint32_t   cr;      /* PART of the CR is non volatile for all */
353    uint32_t   pc;      /* Program counter/Link register */
354    uint32_t   msr;     /* Initial interrupt level */
355} Context_Control;
356
357typedef struct {
358    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
359     * procedure calls.  However, this would mean that the interrupt
360     * frame had to hold f0-f13, and the fpscr.  And as the majority
361     * of tasks will not have an FP context, we will save the whole
362     * context here.
363     */
364#if (PPC_HAS_DOUBLE == 1)
365    double      f[32];
366    double      fpscr;
367#else
368    float       f[32];
369    float       fpscr;
370#endif
371} Context_Control_fp;
372
373typedef struct CPU_Interrupt_frame {
374    uint32_t   stacklink;       /* Ensure this is a real frame (also reg1 save) */
375#if (PPC_ABI == PPC_ABI_POWEROPEN)
376    uint32_t   dummy[13];       /* Used by callees: PowerOpen ABI */
377#else
378    uint32_t   dummy[1];        /* Used by callees: SVR4/EABI */
379#endif
380    /* This is what is left out of the primary contexts */
381    uint32_t   gpr0;
382    uint32_t   gpr2;            /* play safe */
383    uint32_t   gpr3;
384    uint32_t   gpr4;
385    uint32_t   gpr5;
386    uint32_t   gpr6;
387    uint32_t   gpr7;
388    uint32_t   gpr8;
389    uint32_t   gpr9;
390    uint32_t   gpr10;
391    uint32_t   gpr11;
392    uint32_t   gpr12;
393    uint32_t   gpr13;   /* Play safe */
394    uint32_t   gpr28;   /* For internal use by the IRQ handler */
395    uint32_t   gpr29;   /* For internal use by the IRQ handler */
396    uint32_t   gpr30;   /* For internal use by the IRQ handler */
397    uint32_t   gpr31;   /* For internal use by the IRQ handler */
398    uint32_t   cr;      /* Bits of this are volatile, so no-one may save */
399    uint32_t   ctr;
400    uint32_t   xer;
401    uint32_t   lr;
402    uint32_t   pc;
403    uint32_t   msr;
404    uint32_t   pad[3];
405} CPU_Interrupt_frame;
406
407
408/*
409 *  The following table contains the information required to configure
410 *  the PowerPC processor specific parameters.
411 */
412
413typedef struct {
414  void       (*pretasking_hook)( void );
415  void       (*predriver_hook)( void );
416  void       (*postdriver_hook)( void );
417  void       (*idle_task)( void );
418  boolean      do_zero_of_workspace;
419  uint32_t     idle_task_stack_size;
420  uint32_t     interrupt_stack_size;
421  uint32_t     extra_mpci_receive_server_stack;
422  void *     (*stack_allocate_hook)( uint32_t   );
423  void       (*stack_free_hook)( void* );
424  /* end of fields required on all CPUs */
425
426  uint32_t     clicks_per_usec;        /* Timer clicks per microsecond */
427  void       (*spurious_handler)(uint32_t   vector, CPU_Interrupt_frame *);
428  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
429
430#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
431  uint32_t     serial_per_sec;         /* Serial clocks per second */
432  boolean      serial_external_clock;
433  boolean      serial_xon_xoff;
434  boolean      serial_cts_rts;
435  uint32_t     serial_rate;
436  uint32_t     timer_average_overhead; /* Average overhead of timer in ticks */
437  uint32_t     timer_least_valid;      /* Least valid number from timer      */
438  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
439#endif
440
441#if (defined(mpc860) || defined(mpc821))
442  uint32_t     clock_speed;            /* Speed of CPU in Hz */
443#endif
444}   rtems_cpu_table;
445#endif
446
447/*
448 *  Macros to access required entires in the CPU Table are in
449 *  the file rtems/system.h.
450 */
451
452/*
453 *  Macros to access PowerPC specific additions to the CPU Table
454 */
455
456#ifndef ASM
457#define rtems_cpu_configuration_get_clicks_per_usec() \
458   (_CPU_Table.clicks_per_usec)
459
460#define rtems_cpu_configuration_get_spurious_handler() \
461   (_CPU_Table.spurious_handler)
462
463#define rtems_cpu_configuration_get_exceptions_in_ram() \
464   (_CPU_Table.exceptions_in_RAM)
465
466#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
467
468#define rtems_cpu_configuration_get_serial_per_sec() \
469   (_CPU_Table.serial_per_sec)
470
471#define rtems_cpu_configuration_get_serial_external_clock() \
472   (_CPU_Table.serial_external_clock)
473
474#define rtems_cpu_configuration_get_serial_xon_xoff() \
475   (_CPU_Table.serial_xon_xoff)
476
477#define rtems_cpu_configuration_get_serial_cts_rts() \
478   (_CPU_Table.serial_cts_rts)
479
480#define rtems_cpu_configuration_get_serial_rate() \
481   (_CPU_Table.serial_rate)
482
483#define rtems_cpu_configuration_get_timer_average_overhead() \
484   (_CPU_Table.timer_average_overhead)
485
486#define rtems_cpu_configuration_get_timer_least_valid() \
487   (_CPU_Table.timer_least_valid)
488
489#define rtems_cpu_configuration_get_timer_internal_clock() \
490   (_CPU_Table.timer_internal_clock)
491
492#endif
493
494#if (defined(mpc860) || defined(mpc821))
495#define rtems_cpu_configuration_get_clock_speed() \
496   (_CPU_Table.clock_speed)
497#endif
498
499#endif
500
501/*
502 *  The following type defines an entry in the PPC's trap table.
503 *
504 *  NOTE: The instructions chosen are RTEMS dependent although one is
505 *        obligated to use two of the four instructions to perform a
506 *        long jump.  The other instructions load one register with the
507 *        trap type (a.k.a. vector) and another with the psr.
508 */
509 
510#ifndef ASM
511typedef struct {
512  uint32_t     stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
513  uint32_t     stw_r0;                        /* stw   %r0, IP_0(%r1)       */
514  uint32_t     li_r0_IRQ;                     /* li    %r0, _IRQ            */
515  uint32_t     b_Handler;                     /* b     PROC (_ISR_Handler)  */
516} CPU_Trap_table_entry;
517#endif
518
519/*
520 *  This variable is optional.  It is used on CPUs on which it is difficult
521 *  to generate an "uninitialized" FP context.  It is filled in by
522 *  _CPU_Initialize and copied into the task's FP context area during
523 *  _CPU_Context_Initialize.
524 */
525
526#ifndef ASM
527/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
528#endif
529
530/*
531 *  On some CPUs, RTEMS supports a software managed interrupt stack.
532 *  This stack is allocated by the Interrupt Manager and the switch
533 *  is performed in _ISR_Handler.  These variables contain pointers
534 *  to the lowest and highest addresses in the chunk of memory allocated
535 *  for the interrupt stack.  Since it is unknown whether the stack
536 *  grows up or down (in general), this give the CPU dependent
537 *  code the option of picking the version it wants to use.
538 *
539 *  NOTE: These two variables are required if the macro
540 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
541 */
542
543#ifndef ASM
544SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
545SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
546#endif
547
548/*
549 *  With some compilation systems, it is difficult if not impossible to
550 *  call a high-level language routine from assembly language.  This
551 *  is especially true of commercial Ada compilers and name mangling
552 *  C++ ones.  This variable can be optionally defined by the CPU porter
553 *  and contains the address of the routine _Thread_Dispatch.  This
554 *  can make it easier to invoke that routine at the end of the interrupt
555 *  sequence (if a dispatch is necessary).
556 */
557
558#ifndef ASM
559/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
560#endif
561
562/*
563 *  Nothing prevents the porter from declaring more CPU specific variables.
564 */
565
566
567#ifndef ASM
568SCORE_EXTERN struct {
569  uint32_t   volatile* Nest_level;
570  uint32_t   volatile* Disable_level;
571  void *Vector_table;
572  void *Stack;
573#if (PPC_ABI == PPC_ABI_POWEROPEN)
574  uint32_t   Dispatch_r2;
575#else
576  uint32_t   Default_r2;
577  uint32_t   Default_r13;
578#endif
579  volatile boolean *Switch_necessary;
580  boolean *Signal;
581
582  uint32_t   msr_initial;
583} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
584#endif
585
586/*
587 *  The size of the floating point context area.  On some CPUs this
588 *  will not be a "sizeof" because the format of the floating point
589 *  area is not defined -- only the size is.  This is usually on
590 *  CPUs with a "floating point save context" instruction.
591 */
592
593#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
594
595/*
596 * (Optional) # of bytes for libmisc/stackchk to check
597 * If not specifed, then it defaults to something reasonable
598 * for most architectures.
599 */
600
601#define CPU_STACK_CHECK_SIZE    (128)
602
603/*
604 *  Amount of extra stack (above minimum stack size) required by
605 *  MPCI receive server thread.  Remember that in a multiprocessor
606 *  system this thread must exist and be able to process all directives.
607 */
608
609#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
610
611/*
612 *  This defines the number of entries in the ISR_Vector_table managed
613 *  by RTEMS.
614 */
615
616#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
617#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
618
619/*
620 *  This is defined if the port has a special way to report the ISR nesting
621 *  level.  Most ports maintain the variable _ISR_Nest_level.
622 */
623
624#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
625
626/*
627 *  Should be large enough to run all RTEMS tests.  This insures
628 *  that a "reasonable" small application should not have any problems.
629 */
630
631#define CPU_STACK_MINIMUM_SIZE          (1024*8)
632
633/*
634 *  CPU's worst alignment requirement for data types on a byte boundary.  This
635 *  alignment does not take into account the requirements for the stack.
636 */
637
638#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
639
640/*
641 *  This number corresponds to the byte alignment requirement for the
642 *  heap handler.  This alignment requirement may be stricter than that
643 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
644 *  common for the heap to follow the same alignment requirement as
645 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
646 *  then this should be set to CPU_ALIGNMENT.
647 *
648 *  NOTE:  This does not have to be a power of 2.  It does have to
649 *         be greater or equal to than CPU_ALIGNMENT.
650 */
651
652#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
653
654/*
655 *  This number corresponds to the byte alignment requirement for memory
656 *  buffers allocated by the partition manager.  This alignment requirement
657 *  may be stricter than that for the data types alignment specified by
658 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
659 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
660 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
661 *
662 *  NOTE:  This does not have to be a power of 2.  It does have to
663 *         be greater or equal to than CPU_ALIGNMENT.
664 */
665
666#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
667
668/*
669 *  This number corresponds to the byte alignment requirement for the
670 *  stack.  This alignment requirement may be stricter than that for the
671 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
672 *  is strict enough for the stack, then this should be set to 0.
673 *
674 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
675 */
676
677#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
678
679/*
680 *  ISR handler macros
681 */
682
683#ifndef ASM
684void _CPU_Initialize_vectors(void);
685#endif
686
687/*
688 *  Disable all interrupts for an RTEMS critical section.  The previous
689 *  level is returned in _isr_cookie.
690 */
691
692#ifndef ASM
693#define _CPU_MSR_Value( _msr_value ) \
694  do { \
695    _msr_value = 0; \
696    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
697  } while (0)
698
699#define _CPU_MSR_SET( _msr_value ) \
700{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
701
702#if 0
703#define _CPU_ISR_Disable( _isr_cookie ) \
704  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
705    _isr_cookie = 0; \
706    asm volatile (
707        "mfmsr %0" : \
708        "=r" ((_isr_cookie)) : \
709        "0" ((_isr_cookie)) \
710    ); \
711    asm volatile (
712        "andc %1,%0,%1" : \
713        "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
714        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
715    ); \
716    asm volatile (
717        "mtmsr %1" : \
718        "=r" ((_disable_mask)) : \
719        "0" ((_disable_mask)) \
720    ); \
721  }
722#endif
723
724#define _CPU_ISR_Disable( _isr_cookie ) \
725  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
726    _isr_cookie = 0; \
727    asm volatile ( \
728        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
729        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
730        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
731        ); \
732  }
733#endif
734
735/*
736 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
737 *  This indicates the end of an RTEMS critical section.  The parameter
738 *  _isr_cookie is not modified.
739 */
740
741#ifndef ASM
742#define _CPU_ISR_Enable( _isr_cookie )  \
743  { \
744     asm volatile ( "mtmsr %0" : \
745                   "=r" ((_isr_cookie)) : \
746                   "0" ((_isr_cookie))); \
747  }
748#endif
749
750/*
751 *  This temporarily restores the interrupt to _isr_cookie before immediately
752 *  disabling them again.  This is used to divide long RTEMS critical
753 *  sections into two or more parts.  The parameter _isr_cookie is not
754 *  modified.
755 *
756 *  NOTE:  The version being used is not very optimized but it does
757 *         not trip a problem in gcc where the disable mask does not
758 *         get loaded.  Check this for future (post 10/97 gcc versions.
759 */
760
761#ifndef ASM
762#define _CPU_ISR_Flash( _isr_cookie ) \
763  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
764    asm volatile ( \
765      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
766      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
767      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
768    ); \
769  }
770#endif
771
772/*
773 *  Map interrupt level in task mode onto the hardware that the CPU
774 *  actually provides.  Currently, interrupt levels which do not
775 *  map onto the CPU in a generic fashion are undefined.  Someday,
776 *  it would be nice if these were "mapped" by the application
777 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
778 *  8 - 255 would be available for bsp/application specific meaning.
779 *  This could be used to manage a programmable interrupt controller
780 *  via the rtems_task_mode directive.
781 */
782
783#ifndef ASM
784uint32_t   _CPU_ISR_Calculate_level(
785  uint32_t   new_level
786);
787
788void _CPU_ISR_Set_level(
789  uint32_t   new_level
790);
791 
792uint32_t   _CPU_ISR_Get_level( void );
793
794void _CPU_ISR_install_raw_handler(
795  uint32_t    vector,
796  proc_ptr    new_handler,
797  proc_ptr   *old_handler
798);
799#endif
800
801/* end of ISR handler macros */
802
803/*
804 *  Simple spin delay in microsecond units for device drivers.
805 *  This is very dependent on the clock speed of the target.
806 */
807
808#ifndef ASM
809
810#define CPU_Get_timebase_low( _value ) \
811    asm volatile( "mftb  %0" : "=r" (_value) )
812
813#define rtems_bsp_delay( _microseconds ) \
814  do { \
815    uint32_t   start, ticks, now; \
816    CPU_Get_timebase_low( start ) ; \
817    ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \
818    do \
819      CPU_Get_timebase_low( now ) ; \
820    while (now - start < ticks); \
821  } while (0)
822
823#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
824  do { \
825    uint32_t   start, now; \
826    CPU_Get_timebase_low( start ); \
827    do \
828      CPU_Get_timebase_low( now ); \
829    while (now - start < (_cycles)); \
830  } while (0)
831
832#endif
833
834
835/* Context handler macros */
836
837/*
838 *  Initialize the context to a state suitable for starting a
839 *  task after a context restore operation.  Generally, this
840 *  involves:
841 *
842 *     - setting a starting address
843 *     - preparing the stack
844 *     - preparing the stack and frame pointers
845 *     - setting the proper interrupt level in the context
846 *     - initializing the floating point context
847 *
848 *  This routine generally does not set any unnecessary register
849 *  in the context.  The state of the "general data" registers is
850 *  undefined at task start time.
851 *
852 *  NOTE:  Implemented as a subroutine for the SPARC port.
853 */
854
855#ifndef ASM
856void _CPU_Context_Initialize(
857  Context_Control  *the_context,
858  uint32_t         *stack_base,
859  uint32_t          size,
860  uint32_t          new_level,
861  void             *entry_point,
862  boolean           is_fp
863);
864#endif
865
866/*
867 *  This routine is responsible for somehow restarting the currently
868 *  executing task.  If you are lucky, then all that is necessary
869 *  is restoring the context.  Otherwise, there will need to be
870 *  a special assembly routine which does something special in this
871 *  case.  Context_Restore should work most of the time.  It will
872 *  not work if restarting self conflicts with the stack frame
873 *  assumptions of restoring a context.
874 */
875
876#define _CPU_Context_Restart_self( _the_context ) \
877   _CPU_Context_restore( (_the_context) );
878
879/*
880 *  The purpose of this macro is to allow the initial pointer into
881 *  a floating point context area (used to save the floating point
882 *  context) to be at an arbitrary place in the floating point
883 *  context area.
884 *
885 *  This is necessary because some FP units are designed to have
886 *  their context saved as a stack which grows into lower addresses.
887 *  Other FP units can be saved by simply moving registers into offsets
888 *  from the base of the context area.  Finally some FP units provide
889 *  a "dump context" instruction which could fill in from high to low
890 *  or low to high based on the whim of the CPU designers.
891 */
892
893#define _CPU_Context_Fp_start( _base, _offset ) \
894   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
895
896/*
897 *  This routine initializes the FP context area passed to it to.
898 *  There are a few standard ways in which to initialize the
899 *  floating point context.  The code included for this macro assumes
900 *  that this is a CPU in which a "initial" FP context was saved into
901 *  _CPU_Null_fp_context and it simply copies it to the destination
902 *  context passed to it.
903 *
904 *  Other models include (1) not doing anything, and (2) putting
905 *  a "null FP status word" in the correct place in the FP context.
906 */
907
908#define _CPU_Context_Initialize_fp( _destination ) \
909  { \
910   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
911  }
912
913/* end of Context handler macros */
914
915/* Fatal Error manager macros */
916
917/*
918 *  This routine copies _error into a known place -- typically a stack
919 *  location or a register, optionally disables interrupts, and
920 *  halts/stops the CPU.
921 */
922
923#define _CPU_Fatal_halt( _error ) \
924  _CPU_Fatal_error(_error)
925
926/* end of Fatal Error manager macros */
927
928/* Bitfield handler macros */
929
930/*
931 *  This routine sets _output to the bit number of the first bit
932 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
933 *  This type may be either 16 or 32 bits wide although only the 16
934 *  least significant bits will be used.
935 *
936 *  There are a number of variables in using a "find first bit" type
937 *  instruction.
938 *
939 *    (1) What happens when run on a value of zero?
940 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
941 *    (3) The numbering may be zero or one based.
942 *    (4) The "find first bit" instruction may search from MSB or LSB.
943 *
944 *  RTEMS guarantees that (1) will never happen so it is not a concern.
945 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
946 *  _CPU_Priority_Bits_index().  These three form a set of routines
947 *  which must logically operate together.  Bits in the _value are
948 *  set and cleared based on masks built by _CPU_Priority_mask().
949 *  The basic major and minor values calculated by _Priority_Major()
950 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
951 *  to properly range between the values returned by the "find first bit"
952 *  instruction.  This makes it possible for _Priority_Get_highest() to
953 *  calculate the major and directly index into the minor table.
954 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
955 *  is the first bit found.
956 *
957 *  This entire "find first bit" and mapping process depends heavily
958 *  on the manner in which a priority is broken into a major and minor
959 *  components with the major being the 4 MSB of a priority and minor
960 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
961 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
962 *  to the lowest priority.
963 *
964 *  If your CPU does not have a "find first bit" instruction, then
965 *  there are ways to make do without it.  Here are a handful of ways
966 *  to implement this in software:
967 *
968 *    - a series of 16 bit test instructions
969 *    - a "binary search using if's"
970 *    - _number = 0
971 *      if _value > 0x00ff
972 *        _value >>=8
973 *        _number = 8;
974 *
975 *      if _value > 0x0000f
976 *        _value >=8
977 *        _number += 4
978 *
979 *      _number += bit_set_table[ _value ]
980 *
981 *    where bit_set_table[ 16 ] has values which indicate the first
982 *      bit set
983 */
984
985#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
986  { \
987    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
988                  "1" ((_value))); \
989  }
990
991/* end of Bitfield handler macros */
992
993/*
994 *  This routine builds the mask which corresponds to the bit fields
995 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
996 *  for that routine.
997 */
998
999#define _CPU_Priority_Mask( _bit_number ) \
1000  ( 0x80000000 >> (_bit_number) )
1001
1002/*
1003 *  This routine translates the bit numbers returned by
1004 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1005 *  a major or minor component of a priority.  See the discussion
1006 *  for that routine.
1007 */
1008
1009#define _CPU_Priority_bits_index( _priority ) \
1010  (_priority)
1011
1012/* end of Priority handler macros */
1013
1014/* variables */
1015
1016#ifndef ASM
1017extern const uint32_t   _CPU_msrs[4];
1018#endif
1019
1020/* functions */
1021
1022#ifndef ASM
1023
1024/*
1025 *  _CPU_Initialize
1026 *
1027 *  This routine performs CPU dependent initialization.
1028 */
1029
1030void _CPU_Initialize(
1031  rtems_cpu_table  *cpu_table,
1032  void            (*thread_dispatch)
1033);
1034
1035/*
1036 *  _CPU_ISR_install_vector
1037 *
1038 *  This routine installs an interrupt vector.
1039 */
1040
1041void _CPU_ISR_install_vector(
1042  uint32_t    vector,
1043  proc_ptr    new_handler,
1044  proc_ptr   *old_handler
1045);
1046
1047/*
1048 *  _CPU_Install_interrupt_stack
1049 *
1050 *  This routine installs the hardware interrupt stack pointer.
1051 *
1052 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1053 *         is TRUE.
1054 */
1055
1056void _CPU_Install_interrupt_stack( void );
1057
1058/*
1059 *  _CPU_Context_switch
1060 *
1061 *  This routine switches from the run context to the heir context.
1062 */
1063
1064void _CPU_Context_switch(
1065  Context_Control  *run,
1066  Context_Control  *heir
1067);
1068
1069/*
1070 *  _CPU_Context_restore
1071 *
1072 *  This routine is generallu used only to restart self in an
1073 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1074 *
1075 *  NOTE: May be unnecessary to reload some registers.
1076 */
1077
1078void _CPU_Context_restore(
1079  Context_Control *new_context
1080);
1081
1082/*
1083 *  _CPU_Context_save_fp
1084 *
1085 *  This routine saves the floating point context passed to it.
1086 */
1087
1088void _CPU_Context_save_fp(
1089  void **fp_context_ptr
1090);
1091
1092/*
1093 *  _CPU_Context_restore_fp
1094 *
1095 *  This routine restores the floating point context passed to it.
1096 */
1097
1098void _CPU_Context_restore_fp(
1099  void **fp_context_ptr
1100);
1101
1102void _CPU_Fatal_error(
1103  uint32_t   _error
1104);
1105
1106/*  The following routine swaps the endian format of an unsigned int.
1107 *  It must be static because it is referenced indirectly.
1108 *
1109 *  This version will work on any processor, but if there is a better
1110 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1111 *
1112 *     swap least significant two bytes with 16-bit rotate
1113 *     swap upper and lower 16-bits
1114 *     swap most significant two bytes with 16-bit rotate
1115 *
1116 *  Some CPUs have special instructions which swap a 32-bit quantity in
1117 *  a single instruction (e.g. i486).  It is probably best to avoid
1118 *  an "endian swapping control bit" in the CPU.  One good reason is
1119 *  that interrupts would probably have to be disabled to insure that
1120 *  an interrupt does not try to access the same "chunk" with the wrong
1121 *  endian.  Another good reason is that on some CPUs, the endian bit
1122 *  endianness for ALL fetches -- both code and data -- so the code
1123 *  will be fetched incorrectly.
1124 */
1125 
1126static inline uint32_t CPU_swap_u32(
1127  uint32_t value
1128)
1129{
1130  uint32_t   swapped;
1131 
1132  asm volatile("rlwimi %0,%1,8,24,31;"
1133               "rlwimi %0,%1,24,16,23;"
1134               "rlwimi %0,%1,8,8,15;"
1135               "rlwimi %0,%1,24,0,7;" :
1136               "=&r" ((swapped)) : "r" ((value)));
1137
1138  return( swapped );
1139}
1140
1141#define CPU_swap_u16( value ) \
1142  (((value&0xff) << 8) | ((value >> 8)&0xff))
1143
1144/*
1145 *  Routines to access the decrementer register
1146 */
1147
1148#define PPC_Set_decrementer( _clicks ) \
1149  do { \
1150    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
1151  } while (0)
1152
1153/*
1154 *  Routines to access the time base register
1155 */
1156
1157static inline uint64_t   PPC_Get_timebase_register( void )
1158{
1159  uint32_t   tbr_low;
1160  uint32_t   tbr_high;
1161  uint32_t   tbr_high_old;
1162  uint64_t   tbr;
1163
1164  do {
1165    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
1166    asm volatile( "mftb  %0" : "=r" (tbr_low));
1167    asm volatile( "mftbu %0" : "=r" (tbr_high));
1168  } while ( tbr_high_old != tbr_high );
1169
1170  tbr = tbr_high;
1171  tbr <<= 32;
1172  tbr |= tbr_low;
1173  return tbr;
1174}
1175
1176/* ASM */
1177#endif
1178
1179#ifdef __cplusplus
1180}
1181#endif
1182
1183#endif
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