source: rtems/cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h @ 8ecc042a

4.104.114.84.95
Last change on this file since 8ecc042a was 8ecc042a, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/06/02 at 11:16:48

2002-11-06 Ralf Corsepius <corsepiu@…>

  • rtems/new-exceptions/cpu.h: Remove sections on CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY.
  • rtems/old-exceptions/cpu.h: Remove sections on CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY.
  • rtems/score/cpu.h: Insert sections on CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY.
  • Property mode set to 100644
File size: 36.6 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may in
27 *  the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32
33#ifndef __CPU_h
34#define __CPU_h
35
36#ifndef _rtems_score_cpu_h
37#error "You should include <rtems/score/cpu.h>"
38#endif
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44#ifndef ASM
45struct CPU_Interrupt_frame;
46typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
47#endif
48
49/* conditional compilation parameters */
50
51/*
52 *  Does RTEMS manage a dedicated interrupt stack in software?
53 *
54 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
55 *  If FALSE, nothing is done.
56 *
57 *  If the CPU supports a dedicated interrupt stack in hardware,
58 *  then it is generally the responsibility of the BSP to allocate it
59 *  and set it up.
60 *
61 *  If the CPU does not support a dedicated interrupt stack, then
62 *  the porter has two options: (1) execute interrupts on the
63 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
64 *  interrupt stack.
65 *
66 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
67 *
68 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
69 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
70 *  possible that both are FALSE for a particular CPU.  Although it
71 *  is unclear what that would imply about the interrupt processing
72 *  procedure on that CPU.
73 */
74
75#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
76
77/*
78 *  Does this CPU have hardware support for a dedicated interrupt stack?
79 *
80 *  If TRUE, then it must be installed during initialization.
81 *  If FALSE, then no installation is performed.
82 *
83 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
84 *
85 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
86 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
87 *  possible that both are FALSE for a particular CPU.  Although it
88 *  is unclear what that would imply about the interrupt processing
89 *  procedure on that CPU.
90 */
91
92/*
93 *  ACB: This is a lie, but it gets us a handle on a call to set up
94 *  a variable derived from the top of the interrupt stack.
95 */
96
97#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
98
99/*
100 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
101 *
102 *  If TRUE, then the memory is allocated during initialization.
103 *  If FALSE, then the memory is allocated during initialization.
104 *
105 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
106 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
107 */
108
109#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
110
111/*
112 *  Does the RTEMS invoke the user's ISR with the vector number and
113 *  a pointer to the saved interrupt frame (1) or just the vector
114 *  number (0)?
115 */
116
117#define CPU_ISR_PASSES_FRAME_POINTER 1
118
119/*
120 *  Does the CPU have hardware floating point?
121 *
122 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
123 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
124 *
125 *  If there is a FP coprocessor such as the i387 or mc68881, then
126 *  the answer is TRUE.
127 *
128 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
129 *  It indicates whether or not this CPU model has FP support.  For
130 *  example, it would be possible to have an i386_nofp CPU model
131 *  which set this to false to indicate that you have an i386 without
132 *  an i387 and wish to leave floating point support out of RTEMS.
133 */
134
135#if ( PPC_HAS_FPU == 1 )
136#define CPU_HARDWARE_FP     TRUE
137#else
138#define CPU_HARDWARE_FP     FALSE
139#endif
140
141/*
142 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
143 *
144 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
145 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
146 *
147 *  So far, the only CPU in which this option has been used is the
148 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
149 *  floating point registers to perform integer multiplies.  If
150 *  a function which you would not think utilize the FP unit DOES,
151 *  then one can not easily predict which tasks will use the FP hardware.
152 *  In this case, this option should be TRUE.
153 *
154 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
155 */
156
157#define CPU_ALL_TASKS_ARE_FP     FALSE
158
159/*
160 *  Should the IDLE task have a floating point context?
161 *
162 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
163 *  and it has a floating point context which is switched in and out.
164 *  If FALSE, then the IDLE task does not have a floating point context.
165 *
166 *  Setting this to TRUE negatively impacts the time required to preempt
167 *  the IDLE task from an interrupt because the floating point context
168 *  must be saved as part of the preemption.
169 */
170
171#define CPU_IDLE_TASK_IS_FP      FALSE
172
173/*
174 *  Should the saving of the floating point registers be deferred
175 *  until a context switch is made to another different floating point
176 *  task?
177 *
178 *  If TRUE, then the floating point context will not be stored until
179 *  necessary.  It will remain in the floating point registers and not
180 *  disturned until another floating point task is switched to.
181 *
182 *  If FALSE, then the floating point context is saved when a floating
183 *  point task is switched out and restored when the next floating point
184 *  task is restored.  The state of the floating point registers between
185 *  those two operations is not specified.
186 *
187 *  If the floating point context does NOT have to be saved as part of
188 *  interrupt dispatching, then it should be safe to set this to TRUE.
189 *
190 *  Setting this flag to TRUE results in using a different algorithm
191 *  for deciding when to save and restore the floating point context.
192 *  The deferred FP switch algorithm minimizes the number of times
193 *  the FP context is saved and restored.  The FP context is not saved
194 *  until a context switch is made to another, different FP task.
195 *  Thus in a system with only one FP task, the FP context will never
196 *  be saved or restored.
197 */
198/*
199 *  ACB Note:  This could make debugging tricky..
200 */
201
202#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
203
204/*
205 *  Does this port provide a CPU dependent IDLE task implementation?
206 *
207 *  If TRUE, then the routine _CPU_Thread_Idle_body
208 *  must be provided and is the default IDLE thread body instead of
209 *  _CPU_Thread_Idle_body.
210 *
211 *  If FALSE, then use the generic IDLE thread body if the BSP does
212 *  not provide one.
213 *
214 *  This is intended to allow for supporting processors which have
215 *  a low power or idle mode.  When the IDLE thread is executed, then
216 *  the CPU can be powered down.
217 *
218 *  The order of precedence for selecting the IDLE thread body is:
219 *
220 *    1.  BSP provided
221 *    2.  CPU dependent (if provided)
222 *    3.  generic (if no BSP and no CPU dependent)
223 */
224
225#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
226
227/*
228 *  Does the stack grow up (toward higher addresses) or down
229 *  (toward lower addresses)?
230 *
231 *  If TRUE, then the grows upward.
232 *  If FALSE, then the grows toward smaller addresses.
233 */
234
235#define CPU_STACK_GROWS_UP               FALSE
236
237/*
238 *  The following is the variable attribute used to force alignment
239 *  of critical RTEMS structures.  On some processors it may make
240 *  sense to have these aligned on tighter boundaries than
241 *  the minimum requirements of the compiler in order to have as
242 *  much of the critical data area as possible in a cache line.
243 *
244 *  The placement of this macro in the declaration of the variables
245 *  is based on the syntactically requirements of the GNU C
246 *  "__attribute__" extension.  For example with GNU C, use
247 *  the following to force a structures to a 32 byte boundary.
248 *
249 *      __attribute__ ((aligned (32)))
250 *
251 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
252 *         To benefit from using this, the data must be heavily
253 *         used so it will stay in the cache and used frequently enough
254 *         in the executive to justify turning this on.
255 */
256
257#define CPU_STRUCTURE_ALIGNMENT \
258  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
259
260/*
261 *  Define what is required to specify how the network to host conversion
262 *  routines are handled.
263 */
264
265#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
266#define CPU_BIG_ENDIAN                           TRUE
267#define CPU_LITTLE_ENDIAN                        FALSE
268
269/*
270 *  The following defines the number of bits actually used in the
271 *  interrupt field of the task mode.  How those bits map to the
272 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
273 *
274 *  The interrupt level is bit mapped for the PowerPC family. The
275 *  bits are set to 0 to indicate that a particular exception source
276 *  enabled and 1 if it is disabled.  This keeps with RTEMS convention
277 *  that interrupt level 0 means all sources are enabled.
278 *
279 *  The bits are assigned to correspond to enable bits in the MSR.
280 */
281
282#define PPC_INTERRUPT_LEVEL_ME   0x01
283#define PPC_INTERRUPT_LEVEL_EE   0x02
284#define PPC_INTERRUPT_LEVEL_CE   0x04
285
286/* XXX should these be maskable? */
287#if 0
288#define PPC_INTERRUPT_LEVEL_DE   0x08
289#define PPC_INTERRUPT_LEVEL_BE   0x10
290#define PPC_INTERRUPT_LEVEL_SE   0x20
291#endif
292
293#define CPU_MODES_INTERRUPT_MASK   0x00000007
294
295/*
296 *  Processor defined structures
297 *
298 *  Examples structures include the descriptor tables from the i386
299 *  and the processor control structure on the i960ca.
300 */
301
302/* may need to put some structures here.  */
303
304/*
305 * Contexts
306 *
307 *  Generally there are 2 types of context to save.
308 *     1. Interrupt registers to save
309 *     2. Task level registers to save
310 *
311 *  This means we have the following 3 context items:
312 *     1. task level context stuff::  Context_Control
313 *     2. floating point task stuff:: Context_Control_fp
314 *     3. special interrupt level context :: Context_Control_interrupt
315 *
316 *  On some processors, it is cost-effective to save only the callee
317 *  preserved registers during a task context switch.  This means
318 *  that the ISR code needs to save those registers which do not
319 *  persist across function calls.  It is not mandatory to make this
320 *  distinctions between the caller/callee saves registers for the
321 *  purpose of minimizing context saved during task switch and on interrupts.
322 *  If the cost of saving extra registers is minimal, simplicity is the
323 *  choice.  Save the same context on interrupt entry as for tasks in
324 *  this case.
325 *
326 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
327 *  care should be used in designing the context area.
328 *
329 *  On some CPUs with hardware floating point support, the Context_Control_fp
330 *  structure will not be used or it simply consist of an array of a
331 *  fixed number of bytes.   This is done when the floating point context
332 *  is dumped by a "FP save context" type instruction and the format
333 *  is not really defined by the CPU.  In this case, there is no need
334 *  to figure out the exact format -- only the size.  Of course, although
335 *  this is enough information for RTEMS, it is probably not enough for
336 *  a debugger such as gdb.  But that is another problem.
337 */
338
339typedef struct {
340    unsigned32 gpr1;    /* Stack pointer for all */
341    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
342    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
343    unsigned32 gpr14;   /* Non volatile for all */
344    unsigned32 gpr15;   /* Non volatile for all */
345    unsigned32 gpr16;   /* Non volatile for all */
346    unsigned32 gpr17;   /* Non volatile for all */
347    unsigned32 gpr18;   /* Non volatile for all */
348    unsigned32 gpr19;   /* Non volatile for all */
349    unsigned32 gpr20;   /* Non volatile for all */
350    unsigned32 gpr21;   /* Non volatile for all */
351    unsigned32 gpr22;   /* Non volatile for all */
352    unsigned32 gpr23;   /* Non volatile for all */
353    unsigned32 gpr24;   /* Non volatile for all */
354    unsigned32 gpr25;   /* Non volatile for all */
355    unsigned32 gpr26;   /* Non volatile for all */
356    unsigned32 gpr27;   /* Non volatile for all */
357    unsigned32 gpr28;   /* Non volatile for all */
358    unsigned32 gpr29;   /* Non volatile for all */
359    unsigned32 gpr30;   /* Non volatile for all */
360    unsigned32 gpr31;   /* Non volatile for all */
361    unsigned32 cr;      /* PART of the CR is non volatile for all */
362    unsigned32 pc;      /* Program counter/Link register */
363    unsigned32 msr;     /* Initial interrupt level */
364} Context_Control;
365
366typedef struct {
367    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
368     * procedure calls.  However, this would mean that the interrupt
369     * frame had to hold f0-f13, and the fpscr.  And as the majority
370     * of tasks will not have an FP context, we will save the whole
371     * context here.
372     */
373#if (PPC_HAS_DOUBLE == 1)
374    double      f[32];
375    double      fpscr;
376#else
377    float       f[32];
378    float       fpscr;
379#endif
380} Context_Control_fp;
381
382typedef struct CPU_Interrupt_frame {
383    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
384#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
385    unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
386#else
387    unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
388#endif
389    /* This is what is left out of the primary contexts */
390    unsigned32 gpr0;
391    unsigned32 gpr2;            /* play safe */
392    unsigned32 gpr3;
393    unsigned32 gpr4;
394    unsigned32 gpr5;
395    unsigned32 gpr6;
396    unsigned32 gpr7;
397    unsigned32 gpr8;
398    unsigned32 gpr9;
399    unsigned32 gpr10;
400    unsigned32 gpr11;
401    unsigned32 gpr12;
402    unsigned32 gpr13;   /* Play safe */
403    unsigned32 gpr28;   /* For internal use by the IRQ handler */
404    unsigned32 gpr29;   /* For internal use by the IRQ handler */
405    unsigned32 gpr30;   /* For internal use by the IRQ handler */
406    unsigned32 gpr31;   /* For internal use by the IRQ handler */
407    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
408    unsigned32 ctr;
409    unsigned32 xer;
410    unsigned32 lr;
411    unsigned32 pc;
412    unsigned32 msr;
413    unsigned32 pad[3];
414} CPU_Interrupt_frame;
415
416
417/*
418 *  The following table contains the information required to configure
419 *  the PowerPC processor specific parameters.
420 */
421
422typedef struct {
423  void       (*pretasking_hook)( void );
424  void       (*predriver_hook)( void );
425  void       (*postdriver_hook)( void );
426  void       (*idle_task)( void );
427  boolean      do_zero_of_workspace;
428  unsigned32   idle_task_stack_size;
429  unsigned32   interrupt_stack_size;
430  unsigned32   extra_mpci_receive_server_stack;
431  void *     (*stack_allocate_hook)( unsigned32 );
432  void       (*stack_free_hook)( void* );
433  /* end of fields required on all CPUs */
434
435  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
436  void       (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
437  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
438
439#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
440  unsigned32   serial_per_sec;         /* Serial clocks per second */
441  boolean      serial_external_clock;
442  boolean      serial_xon_xoff;
443  boolean      serial_cts_rts;
444  unsigned32   serial_rate;
445  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
446  unsigned32   timer_least_valid;      /* Least valid number from timer      */
447  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
448#endif
449
450#if (defined(mpc860) || defined(mpc821))
451  unsigned32   clock_speed;            /* Speed of CPU in Hz */
452#endif
453}   rtems_cpu_table;
454
455/*
456 *  Macros to access required entires in the CPU Table are in
457 *  the file rtems/system.h.
458 */
459
460/*
461 *  Macros to access PowerPC specific additions to the CPU Table
462 */
463
464#define rtems_cpu_configuration_get_clicks_per_usec() \
465   (_CPU_Table.clicks_per_usec)
466
467#define rtems_cpu_configuration_get_spurious_handler() \
468   (_CPU_Table.spurious_handler)
469
470#define rtems_cpu_configuration_get_exceptions_in_ram() \
471   (_CPU_Table.exceptions_in_RAM)
472
473#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
474
475#define rtems_cpu_configuration_get_serial_per_sec() \
476   (_CPU_Table.serial_per_sec)
477
478#define rtems_cpu_configuration_get_serial_external_clock() \
479   (_CPU_Table.serial_external_clock)
480
481#define rtems_cpu_configuration_get_serial_xon_xoff() \
482   (_CPU_Table.serial_xon_xoff)
483
484#define rtems_cpu_configuration_get_serial_cts_rts() \
485   (_CPU_Table.serial_cts_rts)
486
487#define rtems_cpu_configuration_get_serial_rate() \
488   (_CPU_Table.serial_rate)
489
490#define rtems_cpu_configuration_get_timer_average_overhead() \
491   (_CPU_Table.timer_average_overhead)
492
493#define rtems_cpu_configuration_get_timer_least_valid() \
494   (_CPU_Table.timer_least_valid)
495
496#define rtems_cpu_configuration_get_timer_internal_clock() \
497   (_CPU_Table.timer_internal_clock)
498
499#endif
500
501#if (defined(mpc860) || defined(mpc821))
502#define rtems_cpu_configuration_get_clock_speed() \
503   (_CPU_Table.clock_speed)
504#endif
505
506
507/*
508 *  The following type defines an entry in the PPC's trap table.
509 *
510 *  NOTE: The instructions chosen are RTEMS dependent although one is
511 *        obligated to use two of the four instructions to perform a
512 *        long jump.  The other instructions load one register with the
513 *        trap type (a.k.a. vector) and another with the psr.
514 */
515 
516typedef struct {
517  unsigned32   stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
518  unsigned32   stw_r0;                        /* stw   %r0, IP_0(%r1)       */
519  unsigned32   li_r0_IRQ;                     /* li    %r0, _IRQ            */
520  unsigned32   b_Handler;                     /* b     PROC (_ISR_Handler)  */
521} CPU_Trap_table_entry;
522
523/*
524 *  This variable is optional.  It is used on CPUs on which it is difficult
525 *  to generate an "uninitialized" FP context.  It is filled in by
526 *  _CPU_Initialize and copied into the task's FP context area during
527 *  _CPU_Context_Initialize.
528 */
529
530/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
531
532/*
533 *  On some CPUs, RTEMS supports a software managed interrupt stack.
534 *  This stack is allocated by the Interrupt Manager and the switch
535 *  is performed in _ISR_Handler.  These variables contain pointers
536 *  to the lowest and highest addresses in the chunk of memory allocated
537 *  for the interrupt stack.  Since it is unknown whether the stack
538 *  grows up or down (in general), this give the CPU dependent
539 *  code the option of picking the version it wants to use.
540 *
541 *  NOTE: These two variables are required if the macro
542 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
543 */
544
545SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
546SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
547
548/*
549 *  With some compilation systems, it is difficult if not impossible to
550 *  call a high-level language routine from assembly language.  This
551 *  is especially true of commercial Ada compilers and name mangling
552 *  C++ ones.  This variable can be optionally defined by the CPU porter
553 *  and contains the address of the routine _Thread_Dispatch.  This
554 *  can make it easier to invoke that routine at the end of the interrupt
555 *  sequence (if a dispatch is necessary).
556 */
557
558/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
559
560/*
561 *  Nothing prevents the porter from declaring more CPU specific variables.
562 */
563
564
565SCORE_EXTERN struct {
566  unsigned32 volatile* Nest_level;
567  unsigned32 volatile* Disable_level;
568  void *Vector_table;
569  void *Stack;
570#if (PPC_ABI == PPC_ABI_POWEROPEN)
571  unsigned32 Dispatch_r2;
572#else
573  unsigned32 Default_r2;
574#if (PPC_ABI != PPC_ABI_GCC27)
575  unsigned32 Default_r13;
576#endif
577#endif
578  volatile boolean *Switch_necessary;
579  boolean *Signal;
580
581  unsigned32 msr_initial;
582} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
583
584/*
585 *  The size of the floating point context area.  On some CPUs this
586 *  will not be a "sizeof" because the format of the floating point
587 *  area is not defined -- only the size is.  This is usually on
588 *  CPUs with a "floating point save context" instruction.
589 */
590
591#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
592
593/*
594 * (Optional) # of bytes for libmisc/stackchk to check
595 * If not specifed, then it defaults to something reasonable
596 * for most architectures.
597 */
598
599#define CPU_STACK_CHECK_SIZE    (128)
600
601/*
602 *  Amount of extra stack (above minimum stack size) required by
603 *  MPCI receive server thread.  Remember that in a multiprocessor
604 *  system this thread must exist and be able to process all directives.
605 */
606
607#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
608
609/*
610 *  This defines the number of entries in the ISR_Vector_table managed
611 *  by RTEMS.
612 */
613
614#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
615#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
616
617/*
618 *  This is defined if the port has a special way to report the ISR nesting
619 *  level.  Most ports maintain the variable _ISR_Nest_level.
620 */
621
622#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
623
624/*
625 *  Should be large enough to run all RTEMS tests.  This insures
626 *  that a "reasonable" small application should not have any problems.
627 */
628
629#define CPU_STACK_MINIMUM_SIZE          (1024*8)
630
631/*
632 *  CPU's worst alignment requirement for data types on a byte boundary.  This
633 *  alignment does not take into account the requirements for the stack.
634 */
635
636#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
637
638/*
639 *  This number corresponds to the byte alignment requirement for the
640 *  heap handler.  This alignment requirement may be stricter than that
641 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
642 *  common for the heap to follow the same alignment requirement as
643 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
644 *  then this should be set to CPU_ALIGNMENT.
645 *
646 *  NOTE:  This does not have to be a power of 2.  It does have to
647 *         be greater or equal to than CPU_ALIGNMENT.
648 */
649
650#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
651
652/*
653 *  This number corresponds to the byte alignment requirement for memory
654 *  buffers allocated by the partition manager.  This alignment requirement
655 *  may be stricter than that for the data types alignment specified by
656 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
657 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
658 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
659 *
660 *  NOTE:  This does not have to be a power of 2.  It does have to
661 *         be greater or equal to than CPU_ALIGNMENT.
662 */
663
664#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
665
666/*
667 *  This number corresponds to the byte alignment requirement for the
668 *  stack.  This alignment requirement may be stricter than that for the
669 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
670 *  is strict enough for the stack, then this should be set to 0.
671 *
672 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
673 */
674
675#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
676
677/*
678 *  ISR handler macros
679 */
680
681void _CPU_Initialize_vectors(void);
682
683/*
684 *  Disable all interrupts for an RTEMS critical section.  The previous
685 *  level is returned in _isr_cookie.
686 */
687
688#define _CPU_MSR_Value( _msr_value ) \
689  do { \
690    _msr_value = 0; \
691    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
692  } while (0)
693
694#define _CPU_MSR_SET( _msr_value ) \
695{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
696
697#if 0
698#define _CPU_ISR_Disable( _isr_cookie ) \
699  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
700    _isr_cookie = 0; \
701    asm volatile (
702        "mfmsr %0" : \
703        "=r" ((_isr_cookie)) : \
704        "0" ((_isr_cookie)) \
705    ); \
706    asm volatile (
707        "andc %1,%0,%1" : \
708        "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
709        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
710    ); \
711    asm volatile (
712        "mtmsr %1" : \
713        "=r" ((_disable_mask)) : \
714        "0" ((_disable_mask)) \
715    ); \
716  }
717#endif
718
719#define _CPU_ISR_Disable( _isr_cookie ) \
720  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
721    _isr_cookie = 0; \
722    asm volatile ( \
723        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
724        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
725        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
726        ); \
727  }
728
729/*
730 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
731 *  This indicates the end of an RTEMS critical section.  The parameter
732 *  _isr_cookie is not modified.
733 */
734
735#define _CPU_ISR_Enable( _isr_cookie )  \
736  { \
737     asm volatile ( "mtmsr %0" : \
738                   "=r" ((_isr_cookie)) : \
739                   "0" ((_isr_cookie))); \
740  }
741
742/*
743 *  This temporarily restores the interrupt to _isr_cookie before immediately
744 *  disabling them again.  This is used to divide long RTEMS critical
745 *  sections into two or more parts.  The parameter _isr_cookie is not
746 *  modified.
747 *
748 *  NOTE:  The version being used is not very optimized but it does
749 *         not trip a problem in gcc where the disable mask does not
750 *         get loaded.  Check this for future (post 10/97 gcc versions.
751 */
752
753#define _CPU_ISR_Flash( _isr_cookie ) \
754  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
755    asm volatile ( \
756      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
757      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
758      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
759    ); \
760  }
761
762/*
763 *  Map interrupt level in task mode onto the hardware that the CPU
764 *  actually provides.  Currently, interrupt levels which do not
765 *  map onto the CPU in a generic fashion are undefined.  Someday,
766 *  it would be nice if these were "mapped" by the application
767 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
768 *  8 - 255 would be available for bsp/application specific meaning.
769 *  This could be used to manage a programmable interrupt controller
770 *  via the rtems_task_mode directive.
771 */
772
773unsigned32 _CPU_ISR_Calculate_level(
774  unsigned32 new_level
775);
776
777void _CPU_ISR_Set_level(
778  unsigned32 new_level
779);
780 
781unsigned32 _CPU_ISR_Get_level( void );
782
783void _CPU_ISR_install_raw_handler(
784  unsigned32  vector,
785  proc_ptr    new_handler,
786  proc_ptr   *old_handler
787);
788
789/* end of ISR handler macros */
790
791/*
792 *  Simple spin delay in microsecond units for device drivers.
793 *  This is very dependent on the clock speed of the target.
794 */
795
796#define CPU_Get_timebase_low( _value ) \
797    asm volatile( "mftb  %0" : "=r" (_value) )
798
799#define rtems_bsp_delay( _microseconds ) \
800  do { \
801    unsigned32 start, ticks, now; \
802    CPU_Get_timebase_low( start ) ; \
803    ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \
804    do \
805      CPU_Get_timebase_low( now ) ; \
806    while (now - start < ticks); \
807  } while (0)
808
809#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
810  do { \
811    unsigned32 start, now; \
812    CPU_Get_timebase_low( start ); \
813    do \
814      CPU_Get_timebase_low( now ); \
815    while (now - start < (_cycles)); \
816  } while (0)
817
818
819
820/* Context handler macros */
821
822/*
823 *  Initialize the context to a state suitable for starting a
824 *  task after a context restore operation.  Generally, this
825 *  involves:
826 *
827 *     - setting a starting address
828 *     - preparing the stack
829 *     - preparing the stack and frame pointers
830 *     - setting the proper interrupt level in the context
831 *     - initializing the floating point context
832 *
833 *  This routine generally does not set any unnecessary register
834 *  in the context.  The state of the "general data" registers is
835 *  undefined at task start time.
836 *
837 *  NOTE:  Implemented as a subroutine for the SPARC port.
838 */
839
840void _CPU_Context_Initialize(
841  Context_Control  *the_context,
842  unsigned32       *stack_base,
843  unsigned32        size,
844  unsigned32        new_level,
845  void             *entry_point,
846  boolean           is_fp
847);
848
849/*
850 *  This routine is responsible for somehow restarting the currently
851 *  executing task.  If you are lucky, then all that is necessary
852 *  is restoring the context.  Otherwise, there will need to be
853 *  a special assembly routine which does something special in this
854 *  case.  Context_Restore should work most of the time.  It will
855 *  not work if restarting self conflicts with the stack frame
856 *  assumptions of restoring a context.
857 */
858
859#define _CPU_Context_Restart_self( _the_context ) \
860   _CPU_Context_restore( (_the_context) );
861
862/*
863 *  The purpose of this macro is to allow the initial pointer into
864 *  a floating point context area (used to save the floating point
865 *  context) to be at an arbitrary place in the floating point
866 *  context area.
867 *
868 *  This is necessary because some FP units are designed to have
869 *  their context saved as a stack which grows into lower addresses.
870 *  Other FP units can be saved by simply moving registers into offsets
871 *  from the base of the context area.  Finally some FP units provide
872 *  a "dump context" instruction which could fill in from high to low
873 *  or low to high based on the whim of the CPU designers.
874 */
875
876#define _CPU_Context_Fp_start( _base, _offset ) \
877   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
878
879/*
880 *  This routine initializes the FP context area passed to it to.
881 *  There are a few standard ways in which to initialize the
882 *  floating point context.  The code included for this macro assumes
883 *  that this is a CPU in which a "initial" FP context was saved into
884 *  _CPU_Null_fp_context and it simply copies it to the destination
885 *  context passed to it.
886 *
887 *  Other models include (1) not doing anything, and (2) putting
888 *  a "null FP status word" in the correct place in the FP context.
889 */
890
891#define _CPU_Context_Initialize_fp( _destination ) \
892  { \
893   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
894  }
895
896/* end of Context handler macros */
897
898/* Fatal Error manager macros */
899
900/*
901 *  This routine copies _error into a known place -- typically a stack
902 *  location or a register, optionally disables interrupts, and
903 *  halts/stops the CPU.
904 */
905
906#define _CPU_Fatal_halt( _error ) \
907  _CPU_Fatal_error(_error)
908
909/* end of Fatal Error manager macros */
910
911/* Bitfield handler macros */
912
913/*
914 *  This routine sets _output to the bit number of the first bit
915 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
916 *  This type may be either 16 or 32 bits wide although only the 16
917 *  least significant bits will be used.
918 *
919 *  There are a number of variables in using a "find first bit" type
920 *  instruction.
921 *
922 *    (1) What happens when run on a value of zero?
923 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
924 *    (3) The numbering may be zero or one based.
925 *    (4) The "find first bit" instruction may search from MSB or LSB.
926 *
927 *  RTEMS guarantees that (1) will never happen so it is not a concern.
928 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
929 *  _CPU_Priority_Bits_index().  These three form a set of routines
930 *  which must logically operate together.  Bits in the _value are
931 *  set and cleared based on masks built by _CPU_Priority_mask().
932 *  The basic major and minor values calculated by _Priority_Major()
933 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
934 *  to properly range between the values returned by the "find first bit"
935 *  instruction.  This makes it possible for _Priority_Get_highest() to
936 *  calculate the major and directly index into the minor table.
937 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
938 *  is the first bit found.
939 *
940 *  This entire "find first bit" and mapping process depends heavily
941 *  on the manner in which a priority is broken into a major and minor
942 *  components with the major being the 4 MSB of a priority and minor
943 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
944 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
945 *  to the lowest priority.
946 *
947 *  If your CPU does not have a "find first bit" instruction, then
948 *  there are ways to make do without it.  Here are a handful of ways
949 *  to implement this in software:
950 *
951 *    - a series of 16 bit test instructions
952 *    - a "binary search using if's"
953 *    - _number = 0
954 *      if _value > 0x00ff
955 *        _value >>=8
956 *        _number = 8;
957 *
958 *      if _value > 0x0000f
959 *        _value >=8
960 *        _number += 4
961 *
962 *      _number += bit_set_table[ _value ]
963 *
964 *    where bit_set_table[ 16 ] has values which indicate the first
965 *      bit set
966 */
967
968#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
969  { \
970    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
971                  "1" ((_value))); \
972  }
973
974/* end of Bitfield handler macros */
975
976/*
977 *  This routine builds the mask which corresponds to the bit fields
978 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
979 *  for that routine.
980 */
981
982#define _CPU_Priority_Mask( _bit_number ) \
983  ( 0x80000000 >> (_bit_number) )
984
985/*
986 *  This routine translates the bit numbers returned by
987 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
988 *  a major or minor component of a priority.  See the discussion
989 *  for that routine.
990 */
991
992#define _CPU_Priority_bits_index( _priority ) \
993  (_priority)
994
995/* end of Priority handler macros */
996
997/* variables */
998
999extern const unsigned32 _CPU_msrs[4];
1000
1001/* functions */
1002
1003/*
1004 *  _CPU_Initialize
1005 *
1006 *  This routine performs CPU dependent initialization.
1007 */
1008
1009void _CPU_Initialize(
1010  rtems_cpu_table  *cpu_table,
1011  void            (*thread_dispatch)
1012);
1013
1014/*
1015 *  _CPU_ISR_install_vector
1016 *
1017 *  This routine installs an interrupt vector.
1018 */
1019
1020void _CPU_ISR_install_vector(
1021  unsigned32  vector,
1022  proc_ptr    new_handler,
1023  proc_ptr   *old_handler
1024);
1025
1026/*
1027 *  _CPU_Install_interrupt_stack
1028 *
1029 *  This routine installs the hardware interrupt stack pointer.
1030 *
1031 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1032 *         is TRUE.
1033 */
1034
1035void _CPU_Install_interrupt_stack( void );
1036
1037/*
1038 *  _CPU_Context_switch
1039 *
1040 *  This routine switches from the run context to the heir context.
1041 */
1042
1043void _CPU_Context_switch(
1044  Context_Control  *run,
1045  Context_Control  *heir
1046);
1047
1048/*
1049 *  _CPU_Context_restore
1050 *
1051 *  This routine is generallu used only to restart self in an
1052 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1053 *
1054 *  NOTE: May be unnecessary to reload some registers.
1055 */
1056
1057void _CPU_Context_restore(
1058  Context_Control *new_context
1059);
1060
1061/*
1062 *  _CPU_Context_save_fp
1063 *
1064 *  This routine saves the floating point context passed to it.
1065 */
1066
1067void _CPU_Context_save_fp(
1068  void **fp_context_ptr
1069);
1070
1071/*
1072 *  _CPU_Context_restore_fp
1073 *
1074 *  This routine restores the floating point context passed to it.
1075 */
1076
1077void _CPU_Context_restore_fp(
1078  void **fp_context_ptr
1079);
1080
1081void _CPU_Fatal_error(
1082  unsigned32 _error
1083);
1084
1085/*  The following routine swaps the endian format of an unsigned int.
1086 *  It must be static because it is referenced indirectly.
1087 *
1088 *  This version will work on any processor, but if there is a better
1089 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1090 *
1091 *     swap least significant two bytes with 16-bit rotate
1092 *     swap upper and lower 16-bits
1093 *     swap most significant two bytes with 16-bit rotate
1094 *
1095 *  Some CPUs have special instructions which swap a 32-bit quantity in
1096 *  a single instruction (e.g. i486).  It is probably best to avoid
1097 *  an "endian swapping control bit" in the CPU.  One good reason is
1098 *  that interrupts would probably have to be disabled to insure that
1099 *  an interrupt does not try to access the same "chunk" with the wrong
1100 *  endian.  Another good reason is that on some CPUs, the endian bit
1101 *  endianness for ALL fetches -- both code and data -- so the code
1102 *  will be fetched incorrectly.
1103 */
1104 
1105static inline unsigned int CPU_swap_u32(
1106  unsigned int value
1107)
1108{
1109  unsigned32 swapped;
1110 
1111  asm volatile("rlwimi %0,%1,8,24,31;"
1112               "rlwimi %0,%1,24,16,23;"
1113               "rlwimi %0,%1,8,8,15;"
1114               "rlwimi %0,%1,24,0,7;" :
1115               "=&r" ((swapped)) : "r" ((value)));
1116
1117  return( swapped );
1118}
1119
1120#define CPU_swap_u16( value ) \
1121  (((value&0xff) << 8) | ((value >> 8)&0xff))
1122
1123/*
1124 *  Routines to access the decrementer register
1125 */
1126
1127#define PPC_Set_decrementer( _clicks ) \
1128  do { \
1129    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
1130  } while (0)
1131
1132/*
1133 *  Routines to access the time base register
1134 */
1135
1136static inline unsigned64 PPC_Get_timebase_register( void )
1137{
1138  unsigned32 tbr_low;
1139  unsigned32 tbr_high;
1140  unsigned32 tbr_high_old;
1141  unsigned64 tbr;
1142
1143  do {
1144    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
1145    asm volatile( "mftb  %0" : "=r" (tbr_low));
1146    asm volatile( "mftbu %0" : "=r" (tbr_high));
1147  } while ( tbr_high_old != tbr_high );
1148
1149  tbr = tbr_high;
1150  tbr <<= 32;
1151  tbr |= tbr_low;
1152  return tbr;
1153}
1154
1155#ifdef __cplusplus
1156}
1157#endif
1158
1159#endif
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