1 | /* cpu.h |
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2 | * |
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3 | * This include file contains information pertaining to the PowerPC |
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4 | * processor. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/exec/cpu/no_cpu/cpu.h: |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * |
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26 | * The license and distribution terms for this file may in |
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27 | * the file LICENSE in this distribution or at |
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28 | * http://www.rtems.com/license/LICENSE. |
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29 | * |
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30 | * $Id$ |
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31 | */ |
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32 | |
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33 | #ifndef _RTEMS_OLD_EXCEPTIONS_CPU_H |
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34 | #define _RTEMS_OLD_EXCEPTIONS_CPU_H |
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35 | |
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36 | #ifndef _RTEMS_SCORE_CPU_H |
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37 | #error "You should include <rtems/score/cpu.h>" |
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38 | #endif |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | #ifndef ASM |
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45 | struct CPU_Interrupt_frame; |
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46 | typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * ); |
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47 | #endif |
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48 | |
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49 | /* conditional compilation parameters */ |
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50 | |
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51 | /* |
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52 | * Does RTEMS manage a dedicated interrupt stack in software? |
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53 | * |
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54 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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55 | * If FALSE, nothing is done. |
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56 | * |
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57 | * If the CPU supports a dedicated interrupt stack in hardware, |
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58 | * then it is generally the responsibility of the BSP to allocate it |
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59 | * and set it up. |
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60 | * |
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61 | * If the CPU does not support a dedicated interrupt stack, then |
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62 | * the porter has two options: (1) execute interrupts on the |
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63 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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64 | * interrupt stack. |
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65 | * |
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66 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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67 | * |
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68 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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69 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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70 | * possible that both are FALSE for a particular CPU. Although it |
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71 | * is unclear what that would imply about the interrupt processing |
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72 | * procedure on that CPU. |
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73 | */ |
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74 | |
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75 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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76 | |
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77 | /* |
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78 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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79 | * |
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80 | * If TRUE, then it must be installed during initialization. |
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81 | * If FALSE, then no installation is performed. |
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82 | * |
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83 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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84 | * |
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85 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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86 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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87 | * possible that both are FALSE for a particular CPU. Although it |
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88 | * is unclear what that would imply about the interrupt processing |
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89 | * procedure on that CPU. |
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90 | */ |
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91 | |
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92 | /* |
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93 | * ACB: This is a lie, but it gets us a handle on a call to set up |
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94 | * a variable derived from the top of the interrupt stack. |
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95 | */ |
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96 | |
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97 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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98 | |
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99 | /* |
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100 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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101 | * |
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102 | * If TRUE, then the memory is allocated during initialization. |
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103 | * If FALSE, then the memory is allocated during initialization. |
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104 | * |
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105 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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106 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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107 | */ |
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108 | |
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109 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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110 | |
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111 | /* |
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112 | * Does the RTEMS invoke the user's ISR with the vector number and |
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113 | * a pointer to the saved interrupt frame (1) or just the vector |
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114 | * number (0)? |
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115 | */ |
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116 | |
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117 | #define CPU_ISR_PASSES_FRAME_POINTER 1 |
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118 | |
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119 | /* |
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120 | * Should the saving of the floating point registers be deferred |
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121 | * until a context switch is made to another different floating point |
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122 | * task? |
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123 | * |
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124 | * If TRUE, then the floating point context will not be stored until |
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125 | * necessary. It will remain in the floating point registers and not |
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126 | * disturned until another floating point task is switched to. |
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127 | * |
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128 | * If FALSE, then the floating point context is saved when a floating |
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129 | * point task is switched out and restored when the next floating point |
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130 | * task is restored. The state of the floating point registers between |
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131 | * those two operations is not specified. |
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132 | * |
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133 | * If the floating point context does NOT have to be saved as part of |
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134 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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135 | * |
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136 | * Setting this flag to TRUE results in using a different algorithm |
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137 | * for deciding when to save and restore the floating point context. |
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138 | * The deferred FP switch algorithm minimizes the number of times |
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139 | * the FP context is saved and restored. The FP context is not saved |
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140 | * until a context switch is made to another, different FP task. |
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141 | * Thus in a system with only one FP task, the FP context will never |
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142 | * be saved or restored. |
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143 | */ |
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144 | /* |
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145 | * ACB Note: This could make debugging tricky.. |
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146 | */ |
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147 | |
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148 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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149 | |
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150 | /* |
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151 | * The following defines the number of bits actually used in the |
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152 | * interrupt field of the task mode. How those bits map to the |
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153 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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154 | * |
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155 | * The interrupt level is bit mapped for the PowerPC family. The |
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156 | * bits are set to 0 to indicate that a particular exception source |
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157 | * enabled and 1 if it is disabled. This keeps with RTEMS convention |
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158 | * that interrupt level 0 means all sources are enabled. |
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159 | * |
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160 | * The bits are assigned to correspond to enable bits in the MSR. |
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161 | */ |
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162 | |
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163 | #define PPC_INTERRUPT_LEVEL_ME 0x01 |
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164 | #define PPC_INTERRUPT_LEVEL_EE 0x02 |
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165 | #define PPC_INTERRUPT_LEVEL_CE 0x04 |
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166 | |
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167 | /* XXX should these be maskable? */ |
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168 | #if 0 |
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169 | #define PPC_INTERRUPT_LEVEL_DE 0x08 |
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170 | #define PPC_INTERRUPT_LEVEL_BE 0x10 |
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171 | #define PPC_INTERRUPT_LEVEL_SE 0x20 |
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172 | #endif |
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173 | |
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174 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 |
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175 | |
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176 | /* |
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177 | * Processor defined structures required for cpukit/score. |
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178 | */ |
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179 | |
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180 | #ifndef ASM |
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181 | /* |
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182 | * The following table contains the information required to configure |
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183 | * the PowerPC processor specific parameters. |
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184 | */ |
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185 | |
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186 | typedef struct { |
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187 | void (*pretasking_hook)( void ); |
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188 | void (*predriver_hook)( void ); |
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189 | void (*postdriver_hook)( void ); |
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190 | void (*idle_task)( void ); |
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191 | boolean do_zero_of_workspace; |
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192 | uint32_t idle_task_stack_size; |
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193 | uint32_t interrupt_stack_size; |
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194 | uint32_t extra_mpci_receive_server_stack; |
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195 | void * (*stack_allocate_hook)( uint32_t ); |
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196 | void (*stack_free_hook)( void* ); |
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197 | /* end of fields required on all CPUs */ |
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198 | |
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199 | uint32_t clicks_per_usec; /* Timer clicks per microsecond */ |
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200 | void (*spurious_handler)(uint32_t vector, CPU_Interrupt_frame *); |
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201 | boolean exceptions_in_RAM; /* TRUE if in RAM */ |
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202 | |
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203 | #if (defined(ppc403) || defined(ppc405) \ |
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204 | || defined(mpc860) || defined(mpc821) || defined(mpc8260)) |
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205 | uint32_t serial_per_sec; /* Serial clocks per second */ |
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206 | boolean serial_external_clock; |
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207 | boolean serial_xon_xoff; |
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208 | boolean serial_cts_rts; |
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209 | uint32_t serial_rate; |
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210 | uint32_t timer_average_overhead; /* Average overhead of timer in ticks */ |
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211 | uint32_t timer_least_valid; /* Least valid number from timer */ |
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212 | boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
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213 | #endif |
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214 | |
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215 | #if (defined(mpc555) \ |
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216 | || defined(mpc860) || defined(mpc821) || defined(mpc8260)) |
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217 | uint32_t clock_speed; /* Speed of CPU in Hz */ |
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218 | #endif |
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219 | } rtems_cpu_table; |
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220 | #endif |
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221 | |
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222 | /* |
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223 | * Macros to access required entires in the CPU Table are in |
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224 | * the file rtems/system.h. |
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225 | */ |
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226 | |
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227 | /* |
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228 | * Macros to access PowerPC specific additions to the CPU Table |
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229 | */ |
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230 | |
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231 | #ifndef ASM |
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232 | #define rtems_cpu_configuration_get_spurious_handler() \ |
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233 | (_CPU_Table.spurious_handler) |
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234 | #endif /* ASM */ |
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235 | |
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236 | /* |
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237 | * The following type defines an entry in the PPC's trap table. |
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238 | * |
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239 | * NOTE: The instructions chosen are RTEMS dependent although one is |
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240 | * obligated to use two of the four instructions to perform a |
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241 | * long jump. The other instructions load one register with the |
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242 | * trap type (a.k.a. vector) and another with the psr. |
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243 | */ |
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244 | |
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245 | #ifndef ASM |
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246 | typedef struct { |
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247 | uint32_t stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/ |
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248 | uint32_t stw_r0; /* stw %r0, IP_0(%r1) */ |
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249 | uint32_t li_r0_IRQ; /* li %r0, _IRQ */ |
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250 | uint32_t b_Handler; /* b PROC (_ISR_Handler) */ |
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251 | } CPU_Trap_table_entry; |
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252 | #endif |
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253 | |
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254 | /* |
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255 | * This variable is optional. It is used on CPUs on which it is difficult |
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256 | * to generate an "uninitialized" FP context. It is filled in by |
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257 | * _CPU_Initialize and copied into the task's FP context area during |
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258 | * _CPU_Context_Initialize. |
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259 | */ |
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260 | |
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261 | #ifndef ASM |
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262 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
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263 | #endif |
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264 | |
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265 | /* |
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266 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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267 | * This stack is allocated by the Interrupt Manager and the switch |
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268 | * is performed in _ISR_Handler. These variables contain pointers |
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269 | * to the lowest and highest addresses in the chunk of memory allocated |
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270 | * for the interrupt stack. Since it is unknown whether the stack |
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271 | * grows up or down (in general), this give the CPU dependent |
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272 | * code the option of picking the version it wants to use. |
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273 | * |
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274 | * NOTE: These two variables are required if the macro |
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275 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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276 | */ |
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277 | |
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278 | #ifndef ASM |
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279 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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280 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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281 | #endif |
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282 | |
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283 | /* |
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284 | * With some compilation systems, it is difficult if not impossible to |
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285 | * call a high-level language routine from assembly language. This |
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286 | * is especially true of commercial Ada compilers and name mangling |
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287 | * C++ ones. This variable can be optionally defined by the CPU porter |
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288 | * and contains the address of the routine _Thread_Dispatch. This |
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289 | * can make it easier to invoke that routine at the end of the interrupt |
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290 | * sequence (if a dispatch is necessary). |
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291 | */ |
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292 | |
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293 | #ifndef ASM |
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294 | /* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ |
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295 | #endif |
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296 | |
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297 | /* |
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298 | * Nothing prevents the porter from declaring more CPU specific variables. |
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299 | */ |
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300 | |
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301 | |
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302 | #ifndef ASM |
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303 | SCORE_EXTERN struct { |
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304 | uint32_t volatile* Nest_level; |
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305 | uint32_t volatile* Disable_level; |
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306 | void *Vector_table; |
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307 | void *Stack; |
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308 | uint32_t Default_r2; |
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309 | uint32_t Default_r13; |
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310 | volatile boolean *Switch_necessary; |
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311 | boolean *Signal; |
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312 | |
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313 | uint32_t msr_initial; |
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314 | } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; |
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315 | #endif |
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316 | |
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317 | /* |
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318 | * The size of the floating point context area. On some CPUs this |
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319 | * will not be a "sizeof" because the format of the floating point |
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320 | * area is not defined -- only the size is. This is usually on |
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321 | * CPUs with a "floating point save context" instruction. |
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322 | */ |
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323 | |
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324 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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325 | |
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326 | /* |
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327 | * (Optional) # of bytes for libmisc/stackchk to check |
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328 | * If not specifed, then it defaults to something reasonable |
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329 | * for most architectures. |
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330 | */ |
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331 | |
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332 | #define CPU_STACK_CHECK_SIZE (128) |
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333 | |
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334 | /* |
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335 | * Amount of extra stack (above minimum stack size) required by |
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336 | * MPCI receive server thread. Remember that in a multiprocessor |
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337 | * system this thread must exist and be able to process all directives. |
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338 | */ |
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339 | |
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340 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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341 | |
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342 | /* |
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343 | * This defines the number of entries in the ISR_Vector_table managed |
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344 | * by RTEMS. |
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345 | */ |
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346 | |
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347 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) |
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348 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1) |
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349 | |
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350 | /* |
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351 | * This is defined if the port has a special way to report the ISR nesting |
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352 | * level. Most ports maintain the variable _ISR_Nest_level. |
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353 | */ |
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354 | |
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355 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE |
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356 | |
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357 | /* |
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358 | * ISR handler macros |
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359 | */ |
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360 | |
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361 | #ifndef ASM |
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362 | void _CPU_Initialize_vectors(void); |
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363 | #endif |
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364 | |
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365 | /* |
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366 | * Disable all interrupts for an RTEMS critical section. The previous |
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367 | * level is returned in _isr_cookie. |
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368 | */ |
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369 | |
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370 | #ifndef ASM |
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371 | extern const unsigned int _PPC_MSR_DISABLE_MASK; |
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372 | |
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373 | #define _CPU_MSR_GET( _msr_value ) \ |
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374 | do { \ |
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375 | _msr_value = 0; \ |
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376 | asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ |
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377 | } while (0) |
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378 | |
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379 | /* FIXME: Backward compatibility |
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380 | * new-exception-processing uses _CPU_MSR_GET |
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381 | * old-exception-processing had used _CPU_MSR_Value |
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382 | */ |
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383 | #define _CPU_MSR_Value(_msr_value) _CPU_MSR_GET(_msr_value) |
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384 | |
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385 | #define _CPU_MSR_SET( _msr_value ) \ |
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386 | { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } |
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387 | |
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388 | #if 0 |
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389 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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390 | { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \ |
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391 | _isr_cookie = 0; \ |
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392 | asm volatile ( |
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393 | "mfmsr %0" : \ |
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394 | "=r" ((_isr_cookie)) : \ |
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395 | "0" ((_isr_cookie)) \ |
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396 | ); \ |
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397 | asm volatile ( |
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398 | "andc %1,%0,%1" : \ |
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399 | "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ |
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400 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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401 | ); \ |
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402 | asm volatile ( |
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403 | "mtmsr %1" : \ |
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404 | "=r" ((_disable_mask)) : \ |
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405 | "0" ((_disable_mask)) \ |
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406 | ); \ |
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407 | } |
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408 | #endif |
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409 | |
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410 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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411 | { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \ |
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412 | _isr_cookie = 0; \ |
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413 | asm volatile ( \ |
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414 | "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
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415 | "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ |
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416 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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417 | ); \ |
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418 | } |
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419 | #endif |
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420 | |
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421 | /* |
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422 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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423 | * This indicates the end of an RTEMS critical section. The parameter |
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424 | * _isr_cookie is not modified. |
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425 | */ |
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426 | |
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427 | #ifndef ASM |
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428 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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429 | { \ |
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430 | asm volatile ( "mtmsr %0" : \ |
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431 | "=r" ((_isr_cookie)) : \ |
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432 | "0" ((_isr_cookie))); \ |
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433 | } |
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434 | #endif |
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435 | |
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436 | /* |
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437 | * This temporarily restores the interrupt to _isr_cookie before immediately |
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438 | * disabling them again. This is used to divide long RTEMS critical |
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439 | * sections into two or more parts. The parameter _isr_cookie is not |
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440 | * modified. |
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441 | * |
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442 | * NOTE: The version being used is not very optimized but it does |
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443 | * not trip a problem in gcc where the disable mask does not |
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444 | * get loaded. Check this for future (post 10/97 gcc versions. |
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445 | */ |
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446 | |
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447 | #ifndef ASM |
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448 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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449 | { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \ |
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450 | asm volatile ( \ |
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451 | "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
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452 | "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ |
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453 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
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454 | ); \ |
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455 | } |
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456 | #endif |
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457 | |
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458 | /* |
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459 | * Map interrupt level in task mode onto the hardware that the CPU |
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460 | * actually provides. Currently, interrupt levels which do not |
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461 | * map onto the CPU in a generic fashion are undefined. Someday, |
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462 | * it would be nice if these were "mapped" by the application |
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463 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
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464 | * 8 - 255 would be available for bsp/application specific meaning. |
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465 | * This could be used to manage a programmable interrupt controller |
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466 | * via the rtems_task_mode directive. |
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467 | */ |
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468 | |
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469 | #ifndef ASM |
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470 | uint32_t _CPU_ISR_Calculate_level( |
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471 | uint32_t new_level |
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472 | ); |
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473 | |
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474 | void _CPU_ISR_Set_level( |
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475 | uint32_t new_level |
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476 | ); |
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477 | |
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478 | uint32_t _CPU_ISR_Get_level( void ); |
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479 | |
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480 | void _CPU_ISR_install_raw_handler( |
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481 | uint32_t vector, |
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482 | proc_ptr new_handler, |
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483 | proc_ptr *old_handler |
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484 | ); |
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485 | #endif |
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486 | |
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487 | /* end of ISR handler macros */ |
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488 | |
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489 | /* Fatal Error manager macros */ |
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490 | |
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491 | /* |
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492 | * This routine copies _error into a known place -- typically a stack |
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493 | * location or a register, optionally disables interrupts, and |
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494 | * halts/stops the CPU. |
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495 | */ |
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496 | |
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497 | #define _CPU_Fatal_halt( _error ) \ |
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498 | _CPU_Fatal_error(_error) |
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499 | |
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500 | /* end of Fatal Error manager macros */ |
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501 | |
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502 | |
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503 | #ifdef __cplusplus |
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504 | } |
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505 | #endif |
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506 | |
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507 | #endif |
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