source: rtems/cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h @ 2b3f641

4.104.114.84.95
Last change on this file since 2b3f641 was 2b3f641, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 3, 2002 at 2:08:10 PM

2001-04-03 Joel Sherrill <joel@…>

  • Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
  • rtems/score/cpu.h: Account for name change.
  • Property mode set to 100644
File size: 38.9 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may in
27 *  the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32
33#ifndef __CPU_h
34#define __CPU_h
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/ppc.h>               /* pick up machine definitions */
41#ifndef ASM
42struct CPU_Interrupt_frame;
43typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
44
45#include <rtems/score/types.h>
46#endif
47
48/* conditional compilation parameters */
49
50/*
51 *  Should the calls to _Thread_Enable_dispatch be inlined?
52 *
53 *  If TRUE, then they are inlined.
54 *  If FALSE, then a subroutine call is made.
55 *
56 *  Basically this is an example of the classic trade-off of size
57 *  versus speed.  Inlining the call (TRUE) typically increases the
58 *  size of RTEMS while speeding up the enabling of dispatching.
59 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
60 *  only be 0 or 1 unless you are in an interrupt handler and that
61 *  interrupt handler invokes the executive.]  When not inlined
62 *  something calls _Thread_Enable_dispatch which in turns calls
63 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
64 *  one subroutine call is avoided entirely.]
65 */
66
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/*
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 */
86
87#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
88
89/*
90 *  Does RTEMS manage a dedicated interrupt stack in software?
91 *
92 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
93 *  If FALSE, nothing is done.
94 *
95 *  If the CPU supports a dedicated interrupt stack in hardware,
96 *  then it is generally the responsibility of the BSP to allocate it
97 *  and set it up.
98 *
99 *  If the CPU does not support a dedicated interrupt stack, then
100 *  the porter has two options: (1) execute interrupts on the
101 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
102 *  interrupt stack.
103 *
104 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
107 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 *  possible that both are FALSE for a particular CPU.  Although it
109 *  is unclear what that would imply about the interrupt processing
110 *  procedure on that CPU.
111 */
112
113#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
114
115/*
116 *  Does this CPU have hardware support for a dedicated interrupt stack?
117 *
118 *  If TRUE, then it must be installed during initialization.
119 *  If FALSE, then no installation is performed.
120 *
121 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
122 *
123 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
124 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
125 *  possible that both are FALSE for a particular CPU.  Although it
126 *  is unclear what that would imply about the interrupt processing
127 *  procedure on that CPU.
128 */
129
130/*
131 *  ACB: This is a lie, but it gets us a handle on a call to set up
132 *  a variable derived from the top of the interrupt stack.
133 */
134
135#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
136
137/*
138 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
139 *
140 *  If TRUE, then the memory is allocated during initialization.
141 *  If FALSE, then the memory is allocated during initialization.
142 *
143 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
144 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
145 */
146
147#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
148
149/*
150 *  Does the RTEMS invoke the user's ISR with the vector number and
151 *  a pointer to the saved interrupt frame (1) or just the vector
152 *  number (0)?
153 */
154
155#define CPU_ISR_PASSES_FRAME_POINTER 1
156
157/*
158 *  Does the CPU have hardware floating point?
159 *
160 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
161 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
162 *
163 *  If there is a FP coprocessor such as the i387 or mc68881, then
164 *  the answer is TRUE.
165 *
166 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
167 *  It indicates whether or not this CPU model has FP support.  For
168 *  example, it would be possible to have an i386_nofp CPU model
169 *  which set this to false to indicate that you have an i386 without
170 *  an i387 and wish to leave floating point support out of RTEMS.
171 */
172
173#if ( PPC_HAS_FPU == 1 )
174#define CPU_HARDWARE_FP     TRUE
175#else
176#define CPU_HARDWARE_FP     FALSE
177#endif
178
179/*
180 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
181 *
182 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
183 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
184 *
185 *  So far, the only CPU in which this option has been used is the
186 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
187 *  floating point registers to perform integer multiplies.  If
188 *  a function which you would not think utilize the FP unit DOES,
189 *  then one can not easily predict which tasks will use the FP hardware.
190 *  In this case, this option should be TRUE.
191 *
192 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
193 */
194
195#define CPU_ALL_TASKS_ARE_FP     FALSE
196
197/*
198 *  Should the IDLE task have a floating point context?
199 *
200 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
201 *  and it has a floating point context which is switched in and out.
202 *  If FALSE, then the IDLE task does not have a floating point context.
203 *
204 *  Setting this to TRUE negatively impacts the time required to preempt
205 *  the IDLE task from an interrupt because the floating point context
206 *  must be saved as part of the preemption.
207 */
208
209#define CPU_IDLE_TASK_IS_FP      FALSE
210
211/*
212 *  Should the saving of the floating point registers be deferred
213 *  until a context switch is made to another different floating point
214 *  task?
215 *
216 *  If TRUE, then the floating point context will not be stored until
217 *  necessary.  It will remain in the floating point registers and not
218 *  disturned until another floating point task is switched to.
219 *
220 *  If FALSE, then the floating point context is saved when a floating
221 *  point task is switched out and restored when the next floating point
222 *  task is restored.  The state of the floating point registers between
223 *  those two operations is not specified.
224 *
225 *  If the floating point context does NOT have to be saved as part of
226 *  interrupt dispatching, then it should be safe to set this to TRUE.
227 *
228 *  Setting this flag to TRUE results in using a different algorithm
229 *  for deciding when to save and restore the floating point context.
230 *  The deferred FP switch algorithm minimizes the number of times
231 *  the FP context is saved and restored.  The FP context is not saved
232 *  until a context switch is made to another, different FP task.
233 *  Thus in a system with only one FP task, the FP context will never
234 *  be saved or restored.
235 */
236/*
237 *  ACB Note:  This could make debugging tricky..
238 */
239
240#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
241
242/*
243 *  Does this port provide a CPU dependent IDLE task implementation?
244 *
245 *  If TRUE, then the routine _CPU_Thread_Idle_body
246 *  must be provided and is the default IDLE thread body instead of
247 *  _CPU_Thread_Idle_body.
248 *
249 *  If FALSE, then use the generic IDLE thread body if the BSP does
250 *  not provide one.
251 *
252 *  This is intended to allow for supporting processors which have
253 *  a low power or idle mode.  When the IDLE thread is executed, then
254 *  the CPU can be powered down.
255 *
256 *  The order of precedence for selecting the IDLE thread body is:
257 *
258 *    1.  BSP provided
259 *    2.  CPU dependent (if provided)
260 *    3.  generic (if no BSP and no CPU dependent)
261 */
262
263#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
264
265/*
266 *  Does the stack grow up (toward higher addresses) or down
267 *  (toward lower addresses)?
268 *
269 *  If TRUE, then the grows upward.
270 *  If FALSE, then the grows toward smaller addresses.
271 */
272
273#define CPU_STACK_GROWS_UP               FALSE
274
275/*
276 *  The following is the variable attribute used to force alignment
277 *  of critical RTEMS structures.  On some processors it may make
278 *  sense to have these aligned on tighter boundaries than
279 *  the minimum requirements of the compiler in order to have as
280 *  much of the critical data area as possible in a cache line.
281 *
282 *  The placement of this macro in the declaration of the variables
283 *  is based on the syntactically requirements of the GNU C
284 *  "__attribute__" extension.  For example with GNU C, use
285 *  the following to force a structures to a 32 byte boundary.
286 *
287 *      __attribute__ ((aligned (32)))
288 *
289 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
290 *         To benefit from using this, the data must be heavily
291 *         used so it will stay in the cache and used frequently enough
292 *         in the executive to justify turning this on.
293 */
294
295#define CPU_STRUCTURE_ALIGNMENT \
296  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
297
298/*
299 *  Define what is required to specify how the network to host conversion
300 *  routines are handled.
301 */
302
303#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
304#define CPU_BIG_ENDIAN                           TRUE
305#define CPU_LITTLE_ENDIAN                        FALSE
306
307/*
308 *  The following defines the number of bits actually used in the
309 *  interrupt field of the task mode.  How those bits map to the
310 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
311 *
312 *  The interrupt level is bit mapped for the PowerPC family. The
313 *  bits are set to 0 to indicate that a particular exception source
314 *  enabled and 1 if it is disabled.  This keeps with RTEMS convention
315 *  that interrupt level 0 means all sources are enabled.
316 *
317 *  The bits are assigned to correspond to enable bits in the MSR.
318 */
319
320#define PPC_INTERRUPT_LEVEL_ME   0x01
321#define PPC_INTERRUPT_LEVEL_EE   0x02
322#define PPC_INTERRUPT_LEVEL_CE   0x04
323
324/* XXX should these be maskable? */
325#if 0
326#define PPC_INTERRUPT_LEVEL_DE   0x08
327#define PPC_INTERRUPT_LEVEL_BE   0x10
328#define PPC_INTERRUPT_LEVEL_SE   0x20
329#endif
330
331#define CPU_MODES_INTERRUPT_MASK   0x00000007
332
333/*
334 *  Processor defined structures
335 *
336 *  Examples structures include the descriptor tables from the i386
337 *  and the processor control structure on the i960ca.
338 */
339
340/* may need to put some structures here.  */
341
342/*
343 * Contexts
344 *
345 *  Generally there are 2 types of context to save.
346 *     1. Interrupt registers to save
347 *     2. Task level registers to save
348 *
349 *  This means we have the following 3 context items:
350 *     1. task level context stuff::  Context_Control
351 *     2. floating point task stuff:: Context_Control_fp
352 *     3. special interrupt level context :: Context_Control_interrupt
353 *
354 *  On some processors, it is cost-effective to save only the callee
355 *  preserved registers during a task context switch.  This means
356 *  that the ISR code needs to save those registers which do not
357 *  persist across function calls.  It is not mandatory to make this
358 *  distinctions between the caller/callee saves registers for the
359 *  purpose of minimizing context saved during task switch and on interrupts.
360 *  If the cost of saving extra registers is minimal, simplicity is the
361 *  choice.  Save the same context on interrupt entry as for tasks in
362 *  this case.
363 *
364 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
365 *  care should be used in designing the context area.
366 *
367 *  On some CPUs with hardware floating point support, the Context_Control_fp
368 *  structure will not be used or it simply consist of an array of a
369 *  fixed number of bytes.   This is done when the floating point context
370 *  is dumped by a "FP save context" type instruction and the format
371 *  is not really defined by the CPU.  In this case, there is no need
372 *  to figure out the exact format -- only the size.  Of course, although
373 *  this is enough information for RTEMS, it is probably not enough for
374 *  a debugger such as gdb.  But that is another problem.
375 */
376
377typedef struct {
378    unsigned32 gpr1;    /* Stack pointer for all */
379    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
380    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
381    unsigned32 gpr14;   /* Non volatile for all */
382    unsigned32 gpr15;   /* Non volatile for all */
383    unsigned32 gpr16;   /* Non volatile for all */
384    unsigned32 gpr17;   /* Non volatile for all */
385    unsigned32 gpr18;   /* Non volatile for all */
386    unsigned32 gpr19;   /* Non volatile for all */
387    unsigned32 gpr20;   /* Non volatile for all */
388    unsigned32 gpr21;   /* Non volatile for all */
389    unsigned32 gpr22;   /* Non volatile for all */
390    unsigned32 gpr23;   /* Non volatile for all */
391    unsigned32 gpr24;   /* Non volatile for all */
392    unsigned32 gpr25;   /* Non volatile for all */
393    unsigned32 gpr26;   /* Non volatile for all */
394    unsigned32 gpr27;   /* Non volatile for all */
395    unsigned32 gpr28;   /* Non volatile for all */
396    unsigned32 gpr29;   /* Non volatile for all */
397    unsigned32 gpr30;   /* Non volatile for all */
398    unsigned32 gpr31;   /* Non volatile for all */
399    unsigned32 cr;      /* PART of the CR is non volatile for all */
400    unsigned32 pc;      /* Program counter/Link register */
401    unsigned32 msr;     /* Initial interrupt level */
402} Context_Control;
403
404typedef struct {
405    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
406     * procedure calls.  However, this would mean that the interrupt
407     * frame had to hold f0-f13, and the fpscr.  And as the majority
408     * of tasks will not have an FP context, we will save the whole
409     * context here.
410     */
411#if (PPC_HAS_DOUBLE == 1)
412    double      f[32];
413    double      fpscr;
414#else
415    float       f[32];
416    float       fpscr;
417#endif
418} Context_Control_fp;
419
420typedef struct CPU_Interrupt_frame {
421    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
422#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
423    unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
424#else
425    unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
426#endif
427    /* This is what is left out of the primary contexts */
428    unsigned32 gpr0;
429    unsigned32 gpr2;            /* play safe */
430    unsigned32 gpr3;
431    unsigned32 gpr4;
432    unsigned32 gpr5;
433    unsigned32 gpr6;
434    unsigned32 gpr7;
435    unsigned32 gpr8;
436    unsigned32 gpr9;
437    unsigned32 gpr10;
438    unsigned32 gpr11;
439    unsigned32 gpr12;
440    unsigned32 gpr13;   /* Play safe */
441    unsigned32 gpr28;   /* For internal use by the IRQ handler */
442    unsigned32 gpr29;   /* For internal use by the IRQ handler */
443    unsigned32 gpr30;   /* For internal use by the IRQ handler */
444    unsigned32 gpr31;   /* For internal use by the IRQ handler */
445    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
446    unsigned32 ctr;
447    unsigned32 xer;
448    unsigned32 lr;
449    unsigned32 pc;
450    unsigned32 msr;
451    unsigned32 pad[3];
452} CPU_Interrupt_frame;
453
454
455/*
456 *  The following table contains the information required to configure
457 *  the PowerPC processor specific parameters.
458 */
459
460typedef struct {
461  void       (*pretasking_hook)( void );
462  void       (*predriver_hook)( void );
463  void       (*postdriver_hook)( void );
464  void       (*idle_task)( void );
465  boolean      do_zero_of_workspace;
466  unsigned32   idle_task_stack_size;
467  unsigned32   interrupt_stack_size;
468  unsigned32   extra_mpci_receive_server_stack;
469  void *     (*stack_allocate_hook)( unsigned32 );
470  void       (*stack_free_hook)( void* );
471  /* end of fields required on all CPUs */
472
473  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
474  void       (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
475  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
476
477#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
478  unsigned32   serial_per_sec;         /* Serial clocks per second */
479  boolean      serial_external_clock;
480  boolean      serial_xon_xoff;
481  boolean      serial_cts_rts;
482  unsigned32   serial_rate;
483  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
484  unsigned32   timer_least_valid;      /* Least valid number from timer      */
485  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
486#endif
487
488#if (defined(mpc860) || defined(mpc821))
489  unsigned32   clock_speed;            /* Speed of CPU in Hz */
490#endif
491}   rtems_cpu_table;
492
493/*
494 *  Macros to access required entires in the CPU Table are in
495 *  the file rtems/system.h.
496 */
497
498/*
499 *  Macros to access PowerPC specific additions to the CPU Table
500 */
501
502#define rtems_cpu_configuration_get_clicks_per_usec() \
503   (_CPU_Table.clicks_per_usec)
504
505#define rtems_cpu_configuration_get_spurious_handler() \
506   (_CPU_Table.spurious_handler)
507
508#define rtems_cpu_configuration_get_exceptions_in_ram() \
509   (_CPU_Table.exceptions_in_RAM)
510
511#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
512
513#define rtems_cpu_configuration_get_serial_per_sec() \
514   (_CPU_Table.serial_per_sec)
515
516#define rtems_cpu_configuration_get_serial_external_clock() \
517   (_CPU_Table.serial_external_clock)
518
519#define rtems_cpu_configuration_get_serial_xon_xoff() \
520   (_CPU_Table.serial_xon_xoff)
521
522#define rtems_cpu_configuration_get_serial_cts_rts() \
523   (_CPU_Table.serial_cts_rts)
524
525#define rtems_cpu_configuration_get_serial_rate() \
526   (_CPU_Table.serial_rate)
527
528#define rtems_cpu_configuration_get_timer_average_overhead() \
529   (_CPU_Table.timer_average_overhead)
530
531#define rtems_cpu_configuration_get_timer_least_valid() \
532   (_CPU_Table.timer_least_valid)
533
534#define rtems_cpu_configuration_get_timer_internal_clock() \
535   (_CPU_Table.timer_internal_clock)
536
537#endif
538
539#if (defined(mpc860) || defined(mpc821))
540#define rtems_cpu_configuration_get_clock_speed() \
541   (_CPU_Table.clock_speed)
542#endif
543
544
545/*
546 *  The following type defines an entry in the PPC's trap table.
547 *
548 *  NOTE: The instructions chosen are RTEMS dependent although one is
549 *        obligated to use two of the four instructions to perform a
550 *        long jump.  The other instructions load one register with the
551 *        trap type (a.k.a. vector) and another with the psr.
552 */
553 
554typedef struct {
555  unsigned32   stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
556  unsigned32   stw_r0;                        /* stw   %r0, IP_0(%r1)       */
557  unsigned32   li_r0_IRQ;                     /* li    %r0, _IRQ            */
558  unsigned32   b_Handler;                     /* b     PROC (_ISR_Handler)  */
559} CPU_Trap_table_entry;
560
561/*
562 *  This variable is optional.  It is used on CPUs on which it is difficult
563 *  to generate an "uninitialized" FP context.  It is filled in by
564 *  _CPU_Initialize and copied into the task's FP context area during
565 *  _CPU_Context_Initialize.
566 */
567
568/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
569
570/*
571 *  On some CPUs, RTEMS supports a software managed interrupt stack.
572 *  This stack is allocated by the Interrupt Manager and the switch
573 *  is performed in _ISR_Handler.  These variables contain pointers
574 *  to the lowest and highest addresses in the chunk of memory allocated
575 *  for the interrupt stack.  Since it is unknown whether the stack
576 *  grows up or down (in general), this give the CPU dependent
577 *  code the option of picking the version it wants to use.
578 *
579 *  NOTE: These two variables are required if the macro
580 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
581 */
582
583SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
584SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
585
586/*
587 *  With some compilation systems, it is difficult if not impossible to
588 *  call a high-level language routine from assembly language.  This
589 *  is especially true of commercial Ada compilers and name mangling
590 *  C++ ones.  This variable can be optionally defined by the CPU porter
591 *  and contains the address of the routine _Thread_Dispatch.  This
592 *  can make it easier to invoke that routine at the end of the interrupt
593 *  sequence (if a dispatch is necessary).
594 */
595
596/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
597
598/*
599 *  Nothing prevents the porter from declaring more CPU specific variables.
600 */
601
602
603SCORE_EXTERN struct {
604  unsigned32 volatile* Nest_level;
605  unsigned32 volatile* Disable_level;
606  void *Vector_table;
607  void *Stack;
608#if (PPC_ABI == PPC_ABI_POWEROPEN)
609  unsigned32 Dispatch_r2;
610#else
611  unsigned32 Default_r2;
612#if (PPC_ABI != PPC_ABI_GCC27)
613  unsigned32 Default_r13;
614#endif
615#endif
616  volatile boolean *Switch_necessary;
617  boolean *Signal;
618
619  unsigned32 msr_initial;
620} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
621
622/*
623 *  The size of the floating point context area.  On some CPUs this
624 *  will not be a "sizeof" because the format of the floating point
625 *  area is not defined -- only the size is.  This is usually on
626 *  CPUs with a "floating point save context" instruction.
627 */
628
629#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
630
631/*
632 * (Optional) # of bytes for libmisc/stackchk to check
633 * If not specifed, then it defaults to something reasonable
634 * for most architectures.
635 */
636
637#define CPU_STACK_CHECK_SIZE    (128)
638
639/*
640 *  Amount of extra stack (above minimum stack size) required by
641 *  MPCI receive server thread.  Remember that in a multiprocessor
642 *  system this thread must exist and be able to process all directives.
643 */
644
645#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
646
647/*
648 *  This defines the number of entries in the ISR_Vector_table managed
649 *  by RTEMS.
650 */
651
652#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
653#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
654
655/*
656 *  This is defined if the port has a special way to report the ISR nesting
657 *  level.  Most ports maintain the variable _ISR_Nest_level.
658 */
659
660#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
661
662/*
663 *  Should be large enough to run all RTEMS tests.  This insures
664 *  that a "reasonable" small application should not have any problems.
665 */
666
667#define CPU_STACK_MINIMUM_SIZE          (1024*8)
668
669/*
670 *  CPU's worst alignment requirement for data types on a byte boundary.  This
671 *  alignment does not take into account the requirements for the stack.
672 */
673
674#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
675
676/*
677 *  This number corresponds to the byte alignment requirement for the
678 *  heap handler.  This alignment requirement may be stricter than that
679 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
680 *  common for the heap to follow the same alignment requirement as
681 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
682 *  then this should be set to CPU_ALIGNMENT.
683 *
684 *  NOTE:  This does not have to be a power of 2.  It does have to
685 *         be greater or equal to than CPU_ALIGNMENT.
686 */
687
688#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
689
690/*
691 *  This number corresponds to the byte alignment requirement for memory
692 *  buffers allocated by the partition manager.  This alignment requirement
693 *  may be stricter than that for the data types alignment specified by
694 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
695 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
696 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
697 *
698 *  NOTE:  This does not have to be a power of 2.  It does have to
699 *         be greater or equal to than CPU_ALIGNMENT.
700 */
701
702#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
703
704/*
705 *  This number corresponds to the byte alignment requirement for the
706 *  stack.  This alignment requirement may be stricter than that for the
707 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
708 *  is strict enough for the stack, then this should be set to 0.
709 *
710 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
711 */
712
713#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
714
715/*
716 *  ISR handler macros
717 */
718
719void _CPU_Initialize_vectors(void);
720
721/*
722 *  Disable all interrupts for an RTEMS critical section.  The previous
723 *  level is returned in _isr_cookie.
724 */
725
726#define loc_string(a,b) a " (" #b ")\n"
727
728#define _CPU_MSR_Value( _msr_value ) \
729  do { \
730    _msr_value = 0; \
731    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
732  } while (0)
733
734#define _CPU_MSR_SET( _msr_value ) \
735{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
736
737#if 0
738#define _CPU_ISR_Disable( _isr_cookie ) \
739  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
740    _isr_cookie = 0; \
741    asm volatile (
742        "mfmsr %0" : \
743        "=r" ((_isr_cookie)) : \
744        "0" ((_isr_cookie)) \
745    ); \
746    asm volatile (
747        "andc %1,%0,%1" : \
748        "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
749        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
750    ); \
751    asm volatile (
752        "mtmsr %1" : \
753        "=r" ((_disable_mask)) : \
754        "0" ((_disable_mask)) \
755    ); \
756  }
757#endif
758
759#define _CPU_ISR_Disable( _isr_cookie ) \
760  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
761    _isr_cookie = 0; \
762    asm volatile ( \
763        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
764        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
765        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
766        ); \
767  }
768
769
770#define _CPU_Data_Cache_Block_Flush( _address ) \
771  do { register void *__address = (_address); \
772       register unsigned32 _zero = 0; \
773       asm volatile ( "dcbf %0,%1" : \
774                      "=r" (_zero), "=r" (__address) : \
775                      "0" (_zero), "1" (__address) \
776       ); \
777  } while (0)
778
779#define _CPU_Data_Cache_Block_Invalidate( _address ) \
780  do { register void *__address = (_address); \
781       register unsigned32 _zero = 0; \
782       asm volatile ( "dcbi %0,%1" : \
783                      "=r" (_zero), "=r" (__address) : \
784                      "0" (_zero), "1" (__address) \
785       ); \
786  } while (0)
787
788
789/*
790 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
791 *  This indicates the end of an RTEMS critical section.  The parameter
792 *  _isr_cookie is not modified.
793 */
794
795#define _CPU_ISR_Enable( _isr_cookie )  \
796  { \
797     asm volatile ( "mtmsr %0" : \
798                   "=r" ((_isr_cookie)) : \
799                   "0" ((_isr_cookie))); \
800  }
801
802/*
803 *  This temporarily restores the interrupt to _isr_cookie before immediately
804 *  disabling them again.  This is used to divide long RTEMS critical
805 *  sections into two or more parts.  The parameter _isr_cookie is not
806 *  modified.
807 *
808 *  NOTE:  The version being used is not very optimized but it does
809 *         not trip a problem in gcc where the disable mask does not
810 *         get loaded.  Check this for future (post 10/97 gcc versions.
811 */
812
813#define _CPU_ISR_Flash( _isr_cookie ) \
814  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
815    asm volatile ( \
816      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
817      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
818      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
819    ); \
820  }
821
822/*
823 *  Map interrupt level in task mode onto the hardware that the CPU
824 *  actually provides.  Currently, interrupt levels which do not
825 *  map onto the CPU in a generic fashion are undefined.  Someday,
826 *  it would be nice if these were "mapped" by the application
827 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
828 *  8 - 255 would be available for bsp/application specific meaning.
829 *  This could be used to manage a programmable interrupt controller
830 *  via the rtems_task_mode directive.
831 */
832
833unsigned32 _CPU_ISR_Calculate_level(
834  unsigned32 new_level
835);
836
837void _CPU_ISR_Set_level(
838  unsigned32 new_level
839);
840 
841unsigned32 _CPU_ISR_Get_level( void );
842
843void _CPU_ISR_install_raw_handler(
844  unsigned32  vector,
845  proc_ptr    new_handler,
846  proc_ptr   *old_handler
847);
848
849/* end of ISR handler macros */
850
851/*
852 *  Simple spin delay in microsecond units for device drivers.
853 *  This is very dependent on the clock speed of the target.
854 */
855
856#define CPU_Get_timebase_low( _value ) \
857    asm volatile( "mftb  %0" : "=r" (_value) )
858
859#define rtems_bsp_delay( _microseconds ) \
860  do { \
861    unsigned32 start, ticks, now; \
862    CPU_Get_timebase_low( start ) ; \
863    ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \
864    do \
865      CPU_Get_timebase_low( now ) ; \
866    while (now - start < ticks); \
867  } while (0)
868
869#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
870  do { \
871    unsigned32 start, now; \
872    CPU_Get_timebase_low( start ); \
873    do \
874      CPU_Get_timebase_low( now ); \
875    while (now - start < (_cycles)); \
876  } while (0)
877
878
879
880/* Context handler macros */
881
882/*
883 *  Initialize the context to a state suitable for starting a
884 *  task after a context restore operation.  Generally, this
885 *  involves:
886 *
887 *     - setting a starting address
888 *     - preparing the stack
889 *     - preparing the stack and frame pointers
890 *     - setting the proper interrupt level in the context
891 *     - initializing the floating point context
892 *
893 *  This routine generally does not set any unnecessary register
894 *  in the context.  The state of the "general data" registers is
895 *  undefined at task start time.
896 *
897 *  NOTE:  Implemented as a subroutine for the SPARC port.
898 */
899
900void _CPU_Context_Initialize(
901  Context_Control  *the_context,
902  unsigned32       *stack_base,
903  unsigned32        size,
904  unsigned32        new_level,
905  void             *entry_point,
906  boolean           is_fp
907);
908
909/*
910 *  This routine is responsible for somehow restarting the currently
911 *  executing task.  If you are lucky, then all that is necessary
912 *  is restoring the context.  Otherwise, there will need to be
913 *  a special assembly routine which does something special in this
914 *  case.  Context_Restore should work most of the time.  It will
915 *  not work if restarting self conflicts with the stack frame
916 *  assumptions of restoring a context.
917 */
918
919#define _CPU_Context_Restart_self( _the_context ) \
920   _CPU_Context_restore( (_the_context) );
921
922/*
923 *  The purpose of this macro is to allow the initial pointer into
924 *  a floating point context area (used to save the floating point
925 *  context) to be at an arbitrary place in the floating point
926 *  context area.
927 *
928 *  This is necessary because some FP units are designed to have
929 *  their context saved as a stack which grows into lower addresses.
930 *  Other FP units can be saved by simply moving registers into offsets
931 *  from the base of the context area.  Finally some FP units provide
932 *  a "dump context" instruction which could fill in from high to low
933 *  or low to high based on the whim of the CPU designers.
934 */
935
936#define _CPU_Context_Fp_start( _base, _offset ) \
937   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
938
939/*
940 *  This routine initializes the FP context area passed to it to.
941 *  There are a few standard ways in which to initialize the
942 *  floating point context.  The code included for this macro assumes
943 *  that this is a CPU in which a "initial" FP context was saved into
944 *  _CPU_Null_fp_context and it simply copies it to the destination
945 *  context passed to it.
946 *
947 *  Other models include (1) not doing anything, and (2) putting
948 *  a "null FP status word" in the correct place in the FP context.
949 */
950
951#define _CPU_Context_Initialize_fp( _destination ) \
952  { \
953   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
954  }
955
956/* end of Context handler macros */
957
958/* Fatal Error manager macros */
959
960/*
961 *  This routine copies _error into a known place -- typically a stack
962 *  location or a register, optionally disables interrupts, and
963 *  halts/stops the CPU.
964 */
965
966#define _CPU_Fatal_halt( _error ) \
967  _CPU_Fatal_error(_error)
968
969/* end of Fatal Error manager macros */
970
971/* Bitfield handler macros */
972
973/*
974 *  This routine sets _output to the bit number of the first bit
975 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
976 *  This type may be either 16 or 32 bits wide although only the 16
977 *  least significant bits will be used.
978 *
979 *  There are a number of variables in using a "find first bit" type
980 *  instruction.
981 *
982 *    (1) What happens when run on a value of zero?
983 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
984 *    (3) The numbering may be zero or one based.
985 *    (4) The "find first bit" instruction may search from MSB or LSB.
986 *
987 *  RTEMS guarantees that (1) will never happen so it is not a concern.
988 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
989 *  _CPU_Priority_Bits_index().  These three form a set of routines
990 *  which must logically operate together.  Bits in the _value are
991 *  set and cleared based on masks built by _CPU_Priority_mask().
992 *  The basic major and minor values calculated by _Priority_Major()
993 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
994 *  to properly range between the values returned by the "find first bit"
995 *  instruction.  This makes it possible for _Priority_Get_highest() to
996 *  calculate the major and directly index into the minor table.
997 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
998 *  is the first bit found.
999 *
1000 *  This entire "find first bit" and mapping process depends heavily
1001 *  on the manner in which a priority is broken into a major and minor
1002 *  components with the major being the 4 MSB of a priority and minor
1003 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1004 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1005 *  to the lowest priority.
1006 *
1007 *  If your CPU does not have a "find first bit" instruction, then
1008 *  there are ways to make do without it.  Here are a handful of ways
1009 *  to implement this in software:
1010 *
1011 *    - a series of 16 bit test instructions
1012 *    - a "binary search using if's"
1013 *    - _number = 0
1014 *      if _value > 0x00ff
1015 *        _value >>=8
1016 *        _number = 8;
1017 *
1018 *      if _value > 0x0000f
1019 *        _value >=8
1020 *        _number += 4
1021 *
1022 *      _number += bit_set_table[ _value ]
1023 *
1024 *    where bit_set_table[ 16 ] has values which indicate the first
1025 *      bit set
1026 */
1027
1028#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1029  { \
1030    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
1031                  "1" ((_value))); \
1032  }
1033
1034/* end of Bitfield handler macros */
1035
1036/*
1037 *  This routine builds the mask which corresponds to the bit fields
1038 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
1039 *  for that routine.
1040 */
1041
1042#define _CPU_Priority_Mask( _bit_number ) \
1043  ( 0x80000000 >> (_bit_number) )
1044
1045/*
1046 *  This routine translates the bit numbers returned by
1047 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1048 *  a major or minor component of a priority.  See the discussion
1049 *  for that routine.
1050 */
1051
1052#define _CPU_Priority_bits_index( _priority ) \
1053  (_priority)
1054
1055/* end of Priority handler macros */
1056
1057/* variables */
1058
1059extern const unsigned32 _CPU_msrs[4];
1060
1061/* functions */
1062
1063/*
1064 *  _CPU_Initialize
1065 *
1066 *  This routine performs CPU dependent initialization.
1067 */
1068
1069void _CPU_Initialize(
1070  rtems_cpu_table  *cpu_table,
1071  void            (*thread_dispatch)
1072);
1073
1074/*
1075 *  _CPU_ISR_install_vector
1076 *
1077 *  This routine installs an interrupt vector.
1078 */
1079
1080void _CPU_ISR_install_vector(
1081  unsigned32  vector,
1082  proc_ptr    new_handler,
1083  proc_ptr   *old_handler
1084);
1085
1086/*
1087 *  _CPU_Install_interrupt_stack
1088 *
1089 *  This routine installs the hardware interrupt stack pointer.
1090 *
1091 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1092 *         is TRUE.
1093 */
1094
1095void _CPU_Install_interrupt_stack( void );
1096
1097/*
1098 *  _CPU_Context_switch
1099 *
1100 *  This routine switches from the run context to the heir context.
1101 */
1102
1103void _CPU_Context_switch(
1104  Context_Control  *run,
1105  Context_Control  *heir
1106);
1107
1108/*
1109 *  _CPU_Context_restore
1110 *
1111 *  This routine is generallu used only to restart self in an
1112 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1113 *
1114 *  NOTE: May be unnecessary to reload some registers.
1115 */
1116
1117void _CPU_Context_restore(
1118  Context_Control *new_context
1119);
1120
1121/*
1122 *  _CPU_Context_save_fp
1123 *
1124 *  This routine saves the floating point context passed to it.
1125 */
1126
1127void _CPU_Context_save_fp(
1128  void **fp_context_ptr
1129);
1130
1131/*
1132 *  _CPU_Context_restore_fp
1133 *
1134 *  This routine restores the floating point context passed to it.
1135 */
1136
1137void _CPU_Context_restore_fp(
1138  void **fp_context_ptr
1139);
1140
1141void _CPU_Fatal_error(
1142  unsigned32 _error
1143);
1144
1145/*  The following routine swaps the endian format of an unsigned int.
1146 *  It must be static because it is referenced indirectly.
1147 *
1148 *  This version will work on any processor, but if there is a better
1149 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1150 *
1151 *     swap least significant two bytes with 16-bit rotate
1152 *     swap upper and lower 16-bits
1153 *     swap most significant two bytes with 16-bit rotate
1154 *
1155 *  Some CPUs have special instructions which swap a 32-bit quantity in
1156 *  a single instruction (e.g. i486).  It is probably best to avoid
1157 *  an "endian swapping control bit" in the CPU.  One good reason is
1158 *  that interrupts would probably have to be disabled to insure that
1159 *  an interrupt does not try to access the same "chunk" with the wrong
1160 *  endian.  Another good reason is that on some CPUs, the endian bit
1161 *  endianness for ALL fetches -- both code and data -- so the code
1162 *  will be fetched incorrectly.
1163 */
1164 
1165static inline unsigned int CPU_swap_u32(
1166  unsigned int value
1167)
1168{
1169  unsigned32 swapped;
1170 
1171  asm volatile("rlwimi %0,%1,8,24,31;"
1172               "rlwimi %0,%1,24,16,23;"
1173               "rlwimi %0,%1,8,8,15;"
1174               "rlwimi %0,%1,24,0,7;" :
1175               "=&r" ((swapped)) : "r" ((value)));
1176
1177  return( swapped );
1178}
1179
1180#define CPU_swap_u16( value ) \
1181  (((value&0xff) << 8) | ((value >> 8)&0xff))
1182
1183/*
1184 *  Routines to access the decrementer register
1185 */
1186
1187#define PPC_Set_decrementer( _clicks ) \
1188  do { \
1189    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
1190  } while (0)
1191
1192/*
1193 *  Routines to access the time base register
1194 */
1195
1196static inline unsigned64 PPC_Get_timebase_register( void )
1197{
1198  unsigned32 tbr_low;
1199  unsigned32 tbr_high;
1200  unsigned32 tbr_high_old;
1201  unsigned64 tbr;
1202
1203  do {
1204    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
1205    asm volatile( "mftb  %0" : "=r" (tbr_low));
1206    asm volatile( "mftbu %0" : "=r" (tbr_high));
1207  } while ( tbr_high_old != tbr_high );
1208
1209  tbr = tbr_high;
1210  tbr <<= 32;
1211  tbr |= tbr_low;
1212  return tbr;
1213}
1214
1215#ifdef __cplusplus
1216}
1217#endif
1218
1219#endif
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