source: rtems/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h @ 8ecc042a

4.104.114.84.95
Last change on this file since 8ecc042a was 8ecc042a, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/06/02 at 11:16:48

2002-11-06 Ralf Corsepius <corsepiu@…>

  • rtems/new-exceptions/cpu.h: Remove sections on CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY.
  • rtems/old-exceptions/cpu.h: Remove sections on CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY.
  • rtems/score/cpu.h: Insert sections on CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY.
  • Property mode set to 100644
File size: 30.4 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
7 *  Surrey Satellite Technology Limited (SSTL), 2001
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
25 *
26 *  COPYRIGHT (c) 1989-1997.
27 *  On-Line Applications Research Corporation (OAR).
28 *
29 *  The license and distribution terms for this file may be found in
30 *  the file LICENSE in this distribution or at
31 *  http://www.OARcorp.com/rtems/license.html.
32 *
33 *  $Id$
34 */
35
36#ifndef __CPU_h
37#define __CPU_h
38
39#ifndef _rtems_score_cpu_h
40#error "You should include <rtems/score/cpu.h>"
41#endif
42
43#include <rtems/powerpc/registers.h>
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49/* conditional compilation parameters */
50
51/*
52 *  Does RTEMS manage a dedicated interrupt stack in software?
53 *
54 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
55 *  If FALSE, nothing is done.
56 *
57 *  If the CPU supports a dedicated interrupt stack in hardware,
58 *  then it is generally the responsibility of the BSP to allocate it
59 *  and set it up.
60 *
61 *  If the CPU does not support a dedicated interrupt stack, then
62 *  the porter has two options: (1) execute interrupts on the
63 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
64 *  interrupt stack.
65 *
66 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
67 *
68 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
69 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
70 *  possible that both are FALSE for a particular CPU.  Although it
71 *  is unclear what that would imply about the interrupt processing
72 *  procedure on that CPU.
73 */
74
75#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
76
77/*
78 *  Does this CPU have hardware support for a dedicated interrupt stack?
79 *
80 *  If TRUE, then it must be installed during initialization.
81 *  If FALSE, then no installation is performed.
82 *
83 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
84 *
85 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
86 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
87 *  possible that both are FALSE for a particular CPU.  Although it
88 *  is unclear what that would imply about the interrupt processing
89 *  procedure on that CPU.
90 */
91
92#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
93
94/*
95 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
96 *
97 *  If TRUE, then the memory is allocated during initialization.
98 *  If FALSE, then the memory is allocated during initialization.
99 *
100 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
101 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
102 */
103
104#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
105
106/*
107 *  Does the RTEMS invoke the user's ISR with the vector number and
108 *  a pointer to the saved interrupt frame (1) or just the vector
109 *  number (0)?
110 */
111
112#define CPU_ISR_PASSES_FRAME_POINTER 0
113
114/*
115 *  Does the CPU have hardware floating point?
116 *
117 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
118 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
119 *
120 *  If there is a FP coprocessor such as the i387 or mc68881, then
121 *  the answer is TRUE.
122 *
123 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
124 *  It indicates whether or not this CPU model has FP support.  For
125 *  example, it would be possible to have an i386_nofp CPU model
126 *  which set this to false to indicate that you have an i386 without
127 *  an i387 and wish to leave floating point support out of RTEMS.
128 */
129
130#if ( PPC_HAS_FPU == 1 )
131#define CPU_HARDWARE_FP     TRUE
132#else
133#define CPU_HARDWARE_FP     FALSE
134#endif
135
136/*
137 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
138 *
139 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
140 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
141 *
142 *  So far, the only CPU in which this option has been used is the
143 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
144 *  floating point registers to perform integer multiplies.  If
145 *  a function which you would not think utilize the FP unit DOES,
146 *  then one can not easily predict which tasks will use the FP hardware.
147 *  In this case, this option should be TRUE.
148 *
149 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
150 */
151
152#define CPU_ALL_TASKS_ARE_FP     FALSE
153
154/*
155 *  Should the IDLE task have a floating point context?
156 *
157 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
158 *  and it has a floating point context which is switched in and out.
159 *  If FALSE, then the IDLE task does not have a floating point context.
160 *
161 *  Setting this to TRUE negatively impacts the time required to preempt
162 *  the IDLE task from an interrupt because the floating point context
163 *  must be saved as part of the preemption.
164 */
165
166#define CPU_IDLE_TASK_IS_FP      FALSE
167
168/*
169 *  Should the saving of the floating point registers be deferred
170 *  until a context switch is made to another different floating point
171 *  task?
172 *
173 *  If TRUE, then the floating point context will not be stored until
174 *  necessary.  It will remain in the floating point registers and not
175 *  disturned until another floating point task is switched to.
176 *
177 *  If FALSE, then the floating point context is saved when a floating
178 *  point task is switched out and restored when the next floating point
179 *  task is restored.  The state of the floating point registers between
180 *  those two operations is not specified.
181 *
182 *  If the floating point context does NOT have to be saved as part of
183 *  interrupt dispatching, then it should be safe to set this to TRUE.
184 *
185 *  Setting this flag to TRUE results in using a different algorithm
186 *  for deciding when to save and restore the floating point context.
187 *  The deferred FP switch algorithm minimizes the number of times
188 *  the FP context is saved and restored.  The FP context is not saved
189 *  until a context switch is made to another, different FP task.
190 *  Thus in a system with only one FP task, the FP context will never
191 *  be saved or restored.
192 *
193 *  Note, however that compilers may use floating point registers/
194 *  instructions for optimization or they may save/restore FP registers
195 *  on the stack. You must not use deferred switching in these cases
196 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
197 *  exception.
198 */
199/*
200 *  ACB Note:  This could make debugging tricky..
201 */
202
203/* conservative setting (FALSE); probably doesn't affect performance too much */
204#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
205
206/*
207 *  Does this port provide a CPU dependent IDLE task implementation?
208 *
209 *  If TRUE, then the routine _CPU_Thread_Idle_body
210 *  must be provided and is the default IDLE thread body instead of
211 *  _CPU_Thread_Idle_body.
212 *
213 *  If FALSE, then use the generic IDLE thread body if the BSP does
214 *  not provide one.
215 *
216 *  This is intended to allow for supporting processors which have
217 *  a low power or idle mode.  When the IDLE thread is executed, then
218 *  the CPU can be powered down.
219 *
220 *  The order of precedence for selecting the IDLE thread body is:
221 *
222 *    1.  BSP provided
223 *    2.  CPU dependent (if provided)
224 *    3.  generic (if no BSP and no CPU dependent)
225 */
226
227#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
228
229
230/*
231 *  Does the stack grow up (toward higher addresses) or down
232 *  (toward lower addresses)?
233 *
234 *  If TRUE, then the grows upward.
235 *  If FALSE, then the grows toward smaller addresses.
236 */
237
238#define CPU_STACK_GROWS_UP               FALSE
239
240/*
241 *  The following is the variable attribute used to force alignment
242 *  of critical RTEMS structures.  On some processors it may make
243 *  sense to have these aligned on tighter boundaries than
244 *  the minimum requirements of the compiler in order to have as
245 *  much of the critical data area as possible in a cache line.
246 *
247 *  The placement of this macro in the declaration of the variables
248 *  is based on the syntactically requirements of the GNU C
249 *  "__attribute__" extension.  For example with GNU C, use
250 *  the following to force a structures to a 32 byte boundary.
251 *
252 *      __attribute__ ((aligned (32)))
253 *
254 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
255 *         To benefit from using this, the data must be heavily
256 *         used so it will stay in the cache and used frequently enough
257 *         in the executive to justify turning this on.
258 */
259
260#define CPU_STRUCTURE_ALIGNMENT \
261  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
262
263/*
264 *  Define what is required to specify how the network to host conversion
265 *  routines are handled.
266 */
267
268#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
269#define CPU_BIG_ENDIAN                           TRUE
270#define CPU_LITTLE_ENDIAN                        FALSE
271
272
273/*
274 *  Processor defined structures
275 *
276 *  Examples structures include the descriptor tables from the i386
277 *  and the processor control structure on the i960ca.
278 */
279
280/* may need to put some structures here.  */
281
282/*
283 * Contexts
284 *
285 *  Generally there are 2 types of context to save.
286 *     1. Interrupt registers to save
287 *     2. Task level registers to save
288 *
289 *  This means we have the following 3 context items:
290 *     1. task level context stuff::  Context_Control
291 *     2. floating point task stuff:: Context_Control_fp
292 *     3. special interrupt level context :: Context_Control_interrupt
293 *
294 *  On some processors, it is cost-effective to save only the callee
295 *  preserved registers during a task context switch.  This means
296 *  that the ISR code needs to save those registers which do not
297 *  persist across function calls.  It is not mandatory to make this
298 *  distinctions between the caller/callee saves registers for the
299 *  purpose of minimizing context saved during task switch and on interrupts.
300 *  If the cost of saving extra registers is minimal, simplicity is the
301 *  choice.  Save the same context on interrupt entry as for tasks in
302 *  this case.
303 *
304 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
305 *  care should be used in designing the context area.
306 *
307 *  On some CPUs with hardware floating point support, the Context_Control_fp
308 *  structure will not be used or it simply consist of an array of a
309 *  fixed number of bytes.   This is done when the floating point context
310 *  is dumped by a "FP save context" type instruction and the format
311 *  is not really defined by the CPU.  In this case, there is no need
312 *  to figure out the exact format -- only the size.  Of course, although
313 *  this is enough information for RTEMS, it is probably not enough for
314 *  a debugger such as gdb.  But that is another problem.
315 */
316
317#ifndef ASM
318
319typedef struct {
320    unsigned32 gpr1;    /* Stack pointer for all */
321    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
322    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
323    unsigned32 gpr14;   /* Non volatile for all */
324    unsigned32 gpr15;   /* Non volatile for all */
325    unsigned32 gpr16;   /* Non volatile for all */
326    unsigned32 gpr17;   /* Non volatile for all */
327    unsigned32 gpr18;   /* Non volatile for all */
328    unsigned32 gpr19;   /* Non volatile for all */
329    unsigned32 gpr20;   /* Non volatile for all */
330    unsigned32 gpr21;   /* Non volatile for all */
331    unsigned32 gpr22;   /* Non volatile for all */
332    unsigned32 gpr23;   /* Non volatile for all */
333    unsigned32 gpr24;   /* Non volatile for all */
334    unsigned32 gpr25;   /* Non volatile for all */
335    unsigned32 gpr26;   /* Non volatile for all */
336    unsigned32 gpr27;   /* Non volatile for all */
337    unsigned32 gpr28;   /* Non volatile for all */
338    unsigned32 gpr29;   /* Non volatile for all */
339    unsigned32 gpr30;   /* Non volatile for all */
340    unsigned32 gpr31;   /* Non volatile for all */
341    unsigned32 cr;      /* PART of the CR is non volatile for all */
342    unsigned32 pc;      /* Program counter/Link register */
343    unsigned32 msr;     /* Initial interrupt level */
344} Context_Control;
345
346typedef struct {
347    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
348     * procedure calls.  However, this would mean that the interrupt
349     * frame had to hold f0-f13, and the fpscr.  And as the majority
350     * of tasks will not have an FP context, we will save the whole
351     * context here.
352     */
353#if (PPC_HAS_DOUBLE == 1)
354    double      f[32];
355    double      fpscr;
356#else
357    float       f[32];
358    float       fpscr;
359#endif
360} Context_Control_fp;
361
362typedef struct CPU_Interrupt_frame {
363    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
364    unsigned32 calleeLr;        /* link register used by callees: SVR4/EABI */
365  /* This is what is left out of the primary contexts */
366    unsigned32 gpr0;
367    unsigned32 gpr2;            /* play safe */
368    unsigned32 gpr3;
369    unsigned32 gpr4;
370    unsigned32 gpr5;
371    unsigned32 gpr6;
372    unsigned32 gpr7;
373    unsigned32 gpr8;
374    unsigned32 gpr9;
375    unsigned32 gpr10;
376    unsigned32 gpr11;
377    unsigned32 gpr12;
378    unsigned32 gpr13;   /* Play safe */
379    unsigned32 gpr28;   /* For internal use by the IRQ handler */
380    unsigned32 gpr29;   /* For internal use by the IRQ handler */
381    unsigned32 gpr30;   /* For internal use by the IRQ handler */
382    unsigned32 gpr31;   /* For internal use by the IRQ handler */
383    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
384    unsigned32 ctr;
385    unsigned32 xer;
386    unsigned32 lr;
387    unsigned32 pc;
388    unsigned32 msr;
389    unsigned32 pad[3];
390} CPU_Interrupt_frame;
391 
392/*
393 *  The following table contains the information required to configure
394 *  the PowerPC processor specific parameters.
395 */
396
397typedef struct {
398  void       (*pretasking_hook)( void );
399  void       (*predriver_hook)( void );
400  void       (*postdriver_hook)( void );
401  void       (*idle_task)( void );
402  boolean      do_zero_of_workspace;
403  unsigned32   idle_task_stack_size;
404  unsigned32   interrupt_stack_size;
405  unsigned32   extra_mpci_receive_server_stack;
406  void *     (*stack_allocate_hook)( unsigned32 );
407  void       (*stack_free_hook)( void* );
408  /* end of fields required on all CPUs */
409
410  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
411  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
412
413#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
414  unsigned32   serial_per_sec;         /* Serial clocks per second */
415  boolean      serial_external_clock;
416  boolean      serial_xon_xoff;
417  boolean      serial_cts_rts;
418  unsigned32   serial_rate;
419  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
420  unsigned32   timer_least_valid;      /* Least valid number from timer      */
421  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
422#endif
423
424#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
425  unsigned32   clock_speed;            /* Speed of CPU in Hz */
426#endif
427}   rtems_cpu_table;
428
429/*
430 *  Macros to access required entires in the CPU Table are in
431 *  the file rtems/system.h.
432 */
433
434/*
435 *  Macros to access PowerPC MPC750 specific additions to the CPU Table
436 */
437
438#define rtems_cpu_configuration_get_clicks_per_usec() \
439   (_CPU_Table.clicks_per_usec)
440
441#define rtems_cpu_configuration_get_exceptions_in_ram() \
442   (_CPU_Table.exceptions_in_RAM)
443
444/*
445 *  This variable is optional.  It is used on CPUs on which it is difficult
446 *  to generate an "uninitialized" FP context.  It is filled in by
447 *  _CPU_Initialize and copied into the task's FP context area during
448 *  _CPU_Context_Initialize.
449 */
450
451/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
452
453/*
454 *  On some CPUs, RTEMS supports a software managed interrupt stack.
455 *  This stack is allocated by the Interrupt Manager and the switch
456 *  is performed in _ISR_Handler.  These variables contain pointers
457 *  to the lowest and highest addresses in the chunk of memory allocated
458 *  for the interrupt stack.  Since it is unknown whether the stack
459 *  grows up or down (in general), this give the CPU dependent
460 *  code the option of picking the version it wants to use.
461 *
462 *  NOTE: These two variables are required if the macro
463 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
464 */
465
466SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
467SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
468
469#endif /* ndef ASM */
470
471/*
472 *  This defines the number of levels and the mask used to pick those
473 *  bits out of a thread mode.
474 */
475
476#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
477#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
478
479/*
480 *  With some compilation systems, it is difficult if not impossible to
481 *  call a high-level language routine from assembly language.  This
482 *  is especially true of commercial Ada compilers and name mangling
483 *  C++ ones.  This variable can be optionally defined by the CPU porter
484 *  and contains the address of the routine _Thread_Dispatch.  This
485 *  can make it easier to invoke that routine at the end of the interrupt
486 *  sequence (if a dispatch is necessary).
487 */
488
489/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
490
491/*
492 *  Nothing prevents the porter from declaring more CPU specific variables.
493 */
494
495#ifndef ASM
496 
497SCORE_EXTERN struct {
498  unsigned32 *Disable_level;
499  void *Stack;
500  volatile boolean *Switch_necessary;
501  boolean *Signal;
502
503} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
504
505#endif /* ndef ASM */
506
507/*
508 *  The size of the floating point context area.  On some CPUs this
509 *  will not be a "sizeof" because the format of the floating point
510 *  area is not defined -- only the size is.  This is usually on
511 *  CPUs with a "floating point save context" instruction.
512 */
513
514#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
515
516/*
517 * (Optional) # of bytes for libmisc/stackchk to check
518 * If not specifed, then it defaults to something reasonable
519 * for most architectures.
520 */
521
522#define CPU_STACK_CHECK_SIZE    (128)
523
524/*
525 *  Amount of extra stack (above minimum stack size) required by
526 *  MPCI receive server thread.  Remember that in a multiprocessor
527 *  system this thread must exist and be able to process all directives.
528 */
529
530#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
531
532/*
533 *  This defines the number of entries in the ISR_Vector_table managed
534 *  by RTEMS.
535 */
536
537#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
538#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
539
540/*
541 *  This is defined if the port has a special way to report the ISR nesting
542 *  level.  Most ports maintain the variable _ISR_Nest_level.
543 */
544
545#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
546
547/*
548 *  Should be large enough to run all RTEMS tests.  This insures
549 *  that a "reasonable" small application should not have any problems.
550 */
551
552#define CPU_STACK_MINIMUM_SIZE          (1024*8)
553
554/*
555 *  CPU's worst alignment requirement for data types on a byte boundary.  This
556 *  alignment does not take into account the requirements for the stack.
557 */
558
559#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
560
561/*
562 *  This number corresponds to the byte alignment requirement for the
563 *  heap handler.  This alignment requirement may be stricter than that
564 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
565 *  common for the heap to follow the same alignment requirement as
566 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
567 *  then this should be set to CPU_ALIGNMENT.
568 *
569 *  NOTE:  This does not have to be a power of 2.  It does have to
570 *         be greater or equal to than CPU_ALIGNMENT.
571 */
572
573#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
574
575/*
576 *  This number corresponds to the byte alignment requirement for memory
577 *  buffers allocated by the partition manager.  This alignment requirement
578 *  may be stricter than that for the data types alignment specified by
579 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
580 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
581 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
582 *
583 *  NOTE:  This does not have to be a power of 2.  It does have to
584 *         be greater or equal to than CPU_ALIGNMENT.
585 */
586
587#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
588
589/*
590 *  This number corresponds to the byte alignment requirement for the
591 *  stack.  This alignment requirement may be stricter than that for the
592 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
593 *  is strict enough for the stack, then this should be set to 0.
594 *
595 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
596 */
597
598#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
599
600/*
601 * Needed for Interrupt stack
602 */
603#define CPU_MINIMUM_STACK_FRAME_SIZE 8
604
605
606/*
607 *  ISR handler macros
608 */
609
610#define _CPU_Initialize_vectors()
611
612/*
613 *  Disable all interrupts for an RTEMS critical section.  The previous
614 *  level is returned in _isr_cookie.
615 */
616
617#ifndef ASM
618 
619static inline unsigned32 _CPU_ISR_Get_level( void )
620{
621  register unsigned int msr;
622  _CPU_MSR_GET(msr);
623  if (msr & MSR_EE) return 0;
624  else  return 1;
625}
626
627static inline void _CPU_ISR_Set_level( unsigned32 level )
628{
629  register unsigned int msr;
630  _CPU_MSR_GET(msr);
631  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
632    msr |= MSR_EE;
633  }
634  else {
635    msr &= ~MSR_EE;
636  }
637  _CPU_MSR_SET(msr);
638}
639 
640void BSP_panic(char *);
641#define _CPU_ISR_install_vector(irq, new, old) \
642   {BSP_panic("_CPU_ISR_install_vector called\n");}
643
644/* Context handler macros */
645
646/*
647 *  Initialize the context to a state suitable for starting a
648 *  task after a context restore operation.  Generally, this
649 *  involves:
650 *
651 *     - setting a starting address
652 *     - preparing the stack
653 *     - preparing the stack and frame pointers
654 *     - setting the proper interrupt level in the context
655 *     - initializing the floating point context
656 *
657 *  This routine generally does not set any unnecessary register
658 *  in the context.  The state of the "general data" registers is
659 *  undefined at task start time.
660 *
661 *  NOTE:  Implemented as a subroutine for the SPARC port.
662 */
663
664void _CPU_Context_Initialize(
665  Context_Control  *the_context,
666  unsigned32       *stack_base,
667  unsigned32        size,
668  unsigned32        new_level,
669  void             *entry_point,
670  boolean           is_fp
671);
672
673/*
674 *  This routine is responsible for somehow restarting the currently
675 *  executing task.  If you are lucky, then all that is necessary
676 *  is restoring the context.  Otherwise, there will need to be
677 *  a special assembly routine which does something special in this
678 *  case.  Context_Restore should work most of the time.  It will
679 *  not work if restarting self conflicts with the stack frame
680 *  assumptions of restoring a context.
681 */
682
683#define _CPU_Context_Restart_self( _the_context ) \
684   _CPU_Context_restore( (_the_context) );
685
686/*
687 *  The purpose of this macro is to allow the initial pointer into
688 *  a floating point context area (used to save the floating point
689 *  context) to be at an arbitrary place in the floating point
690 *  context area.
691 *
692 *  This is necessary because some FP units are designed to have
693 *  their context saved as a stack which grows into lower addresses.
694 *  Other FP units can be saved by simply moving registers into offsets
695 *  from the base of the context area.  Finally some FP units provide
696 *  a "dump context" instruction which could fill in from high to low
697 *  or low to high based on the whim of the CPU designers.
698 */
699
700#define _CPU_Context_Fp_start( _base, _offset ) \
701   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
702
703/*
704 *  This routine initializes the FP context area passed to it to.
705 *  There are a few standard ways in which to initialize the
706 *  floating point context.  The code included for this macro assumes
707 *  that this is a CPU in which a "initial" FP context was saved into
708 *  _CPU_Null_fp_context and it simply copies it to the destination
709 *  context passed to it.
710 *
711 *  Other models include (1) not doing anything, and (2) putting
712 *  a "null FP status word" in the correct place in the FP context.
713 */
714
715#define _CPU_Context_Initialize_fp( _destination ) \
716  { \
717   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
718  }
719
720/* end of Context handler macros */
721
722/* Fatal Error manager macros */
723
724/*
725 *  This routine copies _error into a known place -- typically a stack
726 *  location or a register, optionally disables interrupts, and
727 *  halts/stops the CPU.
728 */
729
730void _BSP_Fatal_error(unsigned int);
731
732#define _CPU_Fatal_halt( _error ) \
733  _BSP_Fatal_error(_error)
734
735/* end of Fatal Error manager macros */
736
737/* Bitfield handler macros */
738
739/*
740 *  This routine sets _output to the bit number of the first bit
741 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
742 *  This type may be either 16 or 32 bits wide although only the 16
743 *  least significant bits will be used.
744 *
745 *  There are a number of variables in using a "find first bit" type
746 *  instruction.
747 *
748 *    (1) What happens when run on a value of zero?
749 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
750 *    (3) The numbering may be zero or one based.
751 *    (4) The "find first bit" instruction may search from MSB or LSB.
752 *
753 *  RTEMS guarantees that (1) will never happen so it is not a concern.
754 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
755 *  _CPU_Priority_Bits_index().  These three form a set of routines
756 *  which must logically operate together.  Bits in the _value are
757 *  set and cleared based on masks built by _CPU_Priority_mask().
758 *  The basic major and minor values calculated by _Priority_Major()
759 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
760 *  to properly range between the values returned by the "find first bit"
761 *  instruction.  This makes it possible for _Priority_Get_highest() to
762 *  calculate the major and directly index into the minor table.
763 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
764 *  is the first bit found.
765 *
766 *  This entire "find first bit" and mapping process depends heavily
767 *  on the manner in which a priority is broken into a major and minor
768 *  components with the major being the 4 MSB of a priority and minor
769 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
770 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
771 *  to the lowest priority.
772 *
773 *  If your CPU does not have a "find first bit" instruction, then
774 *  there are ways to make do without it.  Here are a handful of ways
775 *  to implement this in software:
776 *
777 *    - a series of 16 bit test instructions
778 *    - a "binary search using if's"
779 *    - _number = 0
780 *      if _value > 0x00ff
781 *        _value >>=8
782 *        _number = 8;
783 *
784 *      if _value > 0x0000f
785 *        _value >=8
786 *        _number += 4
787 *
788 *      _number += bit_set_table[ _value ]
789 *
790 *    where bit_set_table[ 16 ] has values which indicate the first
791 *      bit set
792 */
793
794#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
795  { \
796    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
797                  "1" ((_value))); \
798  }
799
800/* end of Bitfield handler macros */
801
802/*
803 *  This routine builds the mask which corresponds to the bit fields
804 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
805 *  for that routine.
806 */
807
808#define _CPU_Priority_Mask( _bit_number ) \
809  ( 0x80000000 >> (_bit_number) )
810
811/*
812 *  This routine translates the bit numbers returned by
813 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
814 *  a major or minor component of a priority.  See the discussion
815 *  for that routine.
816 */
817
818#define _CPU_Priority_bits_index( _priority ) \
819  (_priority)
820
821/* end of Priority handler macros */
822
823/* variables */
824
825extern const unsigned32 _CPU_msrs[4];
826
827/* functions */
828
829/*
830 *  _CPU_Initialize
831 *
832 *  This routine performs CPU dependent initialization.
833 */
834
835void _CPU_Initialize(
836  rtems_cpu_table  *cpu_table,
837  void            (*thread_dispatch)
838);
839
840
841/*
842 *  _CPU_Install_interrupt_stack
843 *
844 *  This routine installs the hardware interrupt stack pointer.
845 *
846 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
847 *         is TRUE.
848 */
849
850void _CPU_Install_interrupt_stack( void );
851
852/*
853 *  _CPU_Context_switch
854 *
855 *  This routine switches from the run context to the heir context.
856 */
857
858void _CPU_Context_switch(
859  Context_Control  *run,
860  Context_Control  *heir
861);
862
863/*
864 *  _CPU_Context_restore
865 *
866 *  This routine is generallu used only to restart self in an
867 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
868 *
869 *  NOTE: May be unnecessary to reload some registers.
870 */
871
872void _CPU_Context_restore(
873  Context_Control *new_context
874);
875
876/*
877 *  _CPU_Context_save_fp
878 *
879 *  This routine saves the floating point context passed to it.
880 */
881
882void _CPU_Context_save_fp(
883  void **fp_context_ptr
884);
885
886/*
887 *  _CPU_Context_restore_fp
888 *
889 *  This routine restores the floating point context passed to it.
890 */
891
892void _CPU_Context_restore_fp(
893  void **fp_context_ptr
894);
895
896void _CPU_Fatal_error(
897  unsigned32 _error
898);
899
900/*  The following routine swaps the endian format of an unsigned int.
901 *  It must be static because it is referenced indirectly.
902 *
903 *  This version will work on any processor, but if there is a better
904 *  way for your CPU PLEASE use it.  The most common way to do this is to:
905 *
906 *     swap least significant two bytes with 16-bit rotate
907 *     swap upper and lower 16-bits
908 *     swap most significant two bytes with 16-bit rotate
909 *
910 *  Some CPUs have special instructions which swap a 32-bit quantity in
911 *  a single instruction (e.g. i486).  It is probably best to avoid
912 *  an "endian swapping control bit" in the CPU.  One good reason is
913 *  that interrupts would probably have to be disabled to insure that
914 *  an interrupt does not try to access the same "chunk" with the wrong
915 *  endian.  Another good reason is that on some CPUs, the endian bit
916 *  endianness for ALL fetches -- both code and data -- so the code
917 *  will be fetched incorrectly.
918 */
919 
920static inline unsigned int CPU_swap_u32(
921  unsigned int value
922)
923{
924  unsigned32 swapped;
925 
926  asm volatile("rlwimi %0,%1,8,24,31;"
927               "rlwimi %0,%1,24,16,23;"
928               "rlwimi %0,%1,8,8,15;"
929               "rlwimi %0,%1,24,0,7;" :
930               "=&r" ((swapped)) : "r" ((value)));
931
932  return( swapped );
933}
934
935#define CPU_swap_u16( value ) \
936  (((value&0xff) << 8) | ((value >> 8)&0xff))
937
938#endif /* ndef ASM */
939
940#ifdef __cplusplus
941}
942#endif
943
944#endif
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